Unified Coverage Report :: Module :: rstmgr_sw_rst_sva_if

Module : rstmgr_sw_rst_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_sw_rst_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_sw_rst_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_sw_rst_sva_if

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
21	8	8

---

Cond Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Covered	Percent
Conditions	24	24	100.00
Logical	24	24	100.00
Non-Logical	0	0
Event	0	0

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[0])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T4,T7
1	0	Covered	T1,T2,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[1])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T7,T41
1	0	Covered	T1,T2,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[2])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T41,T44
1	0	Covered	T1,T2,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[3])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T41,T44
1	0	Covered	T1,T2,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[4])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T4,T41
1	0	Covered	T1,T2,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[5])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T4,T41
1	0	Covered	T1,T2,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[6])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T4,T11
1	0	Covered	T1,T2,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[7])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T41,T44
1	0	Covered	T1,T2,T4

---

Assert Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions[0].RstEnOff_A	12606006	13573	0	0
gen_assertions[0].RstEnOn_A	12606006	1132	0	0
gen_assertions[0].RstNOff_A	12606006	13573	0	0
gen_assertions[0].RstNOn_A	12606006	1132	0	0
gen_assertions[1].RstEnOff_A	50423670	12298	0	0
gen_assertions[1].RstEnOn_A	50423670	1047	0	0
gen_assertions[1].RstNOff_A	50423670	12298	0	0
gen_assertions[1].RstNOn_A	50423670	1047	0	0
gen_assertions[2].RstEnOff_A	25212584	12327	0	0
gen_assertions[2].RstEnOn_A	25212584	1021	0	0
gen_assertions[2].RstNOff_A	25212584	12327	0	0
gen_assertions[2].RstNOn_A	25212584	1021	0	0
gen_assertions[3].RstEnOff_A	25212631	12399	0	0
gen_assertions[3].RstEnOn_A	25212631	1102	0	0
gen_assertions[3].RstNOff_A	25212631	12399	0	0
gen_assertions[3].RstNOn_A	25212631	1102	0	0
gen_assertions[4].RstEnOff_A	1591472	20738	0	0
gen_assertions[4].RstEnOn_A	1591472	1141	0	0
gen_assertions[4].RstNOff_A	1591472	20738	0	0
gen_assertions[4].RstNOn_A	1591472	1141	0	0
gen_assertions[5].RstEnOff_A	12606006	13780	0	0
gen_assertions[5].RstEnOn_A	12606006	1193	0	0
gen_assertions[5].RstNOff_A	12606006	13780	0	0
gen_assertions[5].RstNOn_A	12606006	1193	0	0
gen_assertions[6].RstEnOff_A	12606006	13855	0	0
gen_assertions[6].RstEnOn_A	12606006	1276	0	0
gen_assertions[6].RstNOff_A	12606006	13855	0	0
gen_assertions[6].RstNOn_A	12606006	1276	0	0
gen_assertions[7].RstEnOff_A	12606006	13892	0	0
gen_assertions[7].RstEnOn_A	12606006	1312	0	0
gen_assertions[7].RstNOff_A	12606006	13892	0	0
gen_assertions[7].RstNOn_A	12606006	1312	0	0

gen_assertions[0].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12606006	13573	0	0
T1	2233	2	0	0
T2	200065	0	0	0
T3	12795	8	0	0
T4	4628	5	0	0
T5	1520	0	0	0
T6	5815	0	0	0
T7	1846	4	0	0
T8	4201	13	0	0
T9	44883	75	0	0
T10	29085	75	0	0
T11	0	4	0	0
T12	0	7	0	0
T13	0	5	0	0

gen_assertions[0].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12606006	1132	0	0
T3	12795	8	0	0
T4	4628	1	0	0
T5	1520	0	0	0
T6	5815	0	0	0
T7	1846	3	0	0
T8	4201	1	0	0
T9	44883	0	0	0
T10	29085	0	0	0
T11	4770	0	0	0
T12	2952	0	0	0
T13	0	1	0	0
T14	0	1	0	0
T41	0	7	0	0
T44	0	1	0	0
T58	0	8	0	0
T63	0	6	0	0

gen_assertions[0].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12606006	13573	0	0
T1	2233	2	0	0
T2	200065	0	0	0
T3	12795	8	0	0
T4	4628	5	0	0
T5	1520	0	0	0
T6	5815	0	0	0
T7	1846	4	0	0
T8	4201	13	0	0
T9	44883	75	0	0
T10	29085	75	0	0
T11	0	4	0	0
T12	0	7	0	0
T13	0	5	0	0

gen_assertions[0].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12606006	1132	0	0
T3	12795	8	0	0
T4	4628	1	0	0
T5	1520	0	0	0
T6	5815	0	0	0
T7	1846	3	0	0
T8	4201	1	0	0
T9	44883	0	0	0
T10	29085	0	0	0
T11	4770	0	0	0
T12	2952	0	0	0
T13	0	1	0	0
T14	0	1	0	0
T41	0	7	0	0
T44	0	1	0	0
T58	0	8	0	0
T63	0	6	0	0

gen_assertions[1].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50423670	12298	0	0
T1	8940	1	0	0
T2	800402	0	0	0
T3	51183	9	0	0
T4	18515	1	0	0
T5	6089	0	0	0
T6	23283	0	0	0
T7	7386	4	0	0
T8	16810	13	0	0
T9	179555	73	0	0
T10	116355	69	0	0
T11	0	4	0	0
T12	0	5	0	0
T13	0	4	0	0

gen_assertions[1].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50423670	1047	0	0
T3	51183	9	0	0
T4	18515	0	0	0
T5	6089	0	0	0
T6	23283	0	0	0
T7	7386	2	0	0
T8	16810	0	0	0
T9	179555	0	0	0
T10	116355	0	0	0
T11	19087	0	0	0
T12	11814	0	0	0
T31	0	3	0	0
T41	0	5	0	0
T44	0	2	0	0
T51	0	4	0	0
T53	0	6	0	0
T58	0	8	0	0
T59	0	12	0	0
T63	0	7	0	0

gen_assertions[1].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50423670	12298	0	0
T1	8940	1	0	0
T2	800402	0	0	0
T3	51183	9	0	0
T4	18515	1	0	0
T5	6089	0	0	0
T6	23283	0	0	0
T7	7386	4	0	0
T8	16810	13	0	0
T9	179555	73	0	0
T10	116355	69	0	0
T11	0	4	0	0
T12	0	5	0	0
T13	0	4	0	0

gen_assertions[1].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50423670	1047	0	0
T3	51183	9	0	0
T4	18515	0	0	0
T5	6089	0	0	0
T6	23283	0	0	0
T7	7386	2	0	0
T8	16810	0	0	0
T9	179555	0	0	0
T10	116355	0	0	0
T11	19087	0	0	0
T12	11814	0	0	0
T31	0	3	0	0
T41	0	5	0	0
T44	0	2	0	0
T51	0	4	0	0
T53	0	6	0	0
T58	0	8	0	0
T59	0	12	0	0
T63	0	7	0	0

gen_assertions[2].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25212584	12327	0	0
T1	4469	1	0	0
T2	400235	0	0	0
T3	25591	10	0	0
T4	9257	1	0	0
T5	3043	0	0	0
T6	11643	0	0	0
T7	3693	4	0	0
T8	8405	13	0	0
T9	89767	73	0	0
T10	58161	69	0	0
T11	0	4	0	0
T12	0	5	0	0
T13	0	4	0	0

gen_assertions[2].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25212584	1021	0	0
T3	25591	10	0	0
T4	9257	0	0	0
T5	3043	0	0	0
T6	11643	0	0	0
T7	3693	0	0	0
T8	8405	0	0	0
T9	89767	0	0	0
T10	58161	0	0	0
T11	9545	0	0	0
T12	5906	0	0	0
T33	0	9	0	0
T41	0	11	0	0
T44	0	1	0	0
T51	0	6	0	0
T53	0	4	0	0
T58	0	10	0	0
T59	0	14	0	0
T87	0	1	0	0
T88	0	14	0	0

gen_assertions[2].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25212584	12327	0	0
T1	4469	1	0	0
T2	400235	0	0	0
T3	25591	10	0	0
T4	9257	1	0	0
T5	3043	0	0	0
T6	11643	0	0	0
T7	3693	4	0	0
T8	8405	13	0	0
T9	89767	73	0	0
T10	58161	69	0	0
T11	0	4	0	0
T12	0	5	0	0
T13	0	4	0	0

gen_assertions[2].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25212584	1021	0	0
T3	25591	10	0	0
T4	9257	0	0	0
T5	3043	0	0	0
T6	11643	0	0	0
T7	3693	0	0	0
T8	8405	0	0	0
T9	89767	0	0	0
T10	58161	0	0	0
T11	9545	0	0	0
T12	5906	0	0	0
T33	0	9	0	0
T41	0	11	0	0
T44	0	1	0	0
T51	0	6	0	0
T53	0	4	0	0
T58	0	10	0	0
T59	0	14	0	0
T87	0	1	0	0
T88	0	14	0	0

gen_assertions[3].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25212631	12399	0	0
T1	4469	1	0	0
T2	400249	0	0	0
T3	25592	12	0	0
T4	9258	1	0	0
T5	3043	0	0	0
T6	11643	0	0	0
T7	3693	4	0	0
T8	8406	13	0	0
T9	89778	73	0	0
T10	58161	69	0	0
T11	0	4	0	0
T12	0	5	0	0
T13	0	4	0	0

gen_assertions[3].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25212631	1102	0	0
T3	25592	12	0	0
T4	9258	0	0	0
T5	3043	0	0	0
T6	11643	0	0	0
T7	3693	0	0	0
T8	8406	0	0	0
T9	89778	0	0	0
T10	58161	0	0	0
T11	9544	0	0	0
T12	5906	0	0	0
T33	0	10	0	0
T41	0	12	0	0
T44	0	2	0	0
T51	0	7	0	0
T53	0	7	0	0
T58	0	10	0	0
T59	0	14	0	0
T87	0	1	0	0
T88	0	12	0	0

gen_assertions[3].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25212631	12399	0	0
T1	4469	1	0	0
T2	400249	0	0	0
T3	25592	12	0	0
T4	9258	1	0	0
T5	3043	0	0	0
T6	11643	0	0	0
T7	3693	4	0	0
T8	8406	13	0	0
T9	89778	73	0	0
T10	58161	69	0	0
T11	0	4	0	0
T12	0	5	0	0
T13	0	4	0	0

gen_assertions[3].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25212631	1102	0	0
T3	25592	12	0	0
T4	9258	0	0	0
T5	3043	0	0	0
T6	11643	0	0	0
T7	3693	0	0	0
T8	8406	0	0	0
T9	89778	0	0	0
T10	58161	0	0	0
T11	9544	0	0	0
T12	5906	0	0	0
T33	0	10	0	0
T41	0	12	0	0
T44	0	2	0	0
T51	0	7	0	0
T53	0	7	0	0
T58	0	10	0	0
T59	0	14	0	0
T87	0	1	0	0
T88	0	12	0	0

gen_assertions[4].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1591472	20738	0	0
T1	278	3	0	0
T2	25136	271	0	0
T3	1598	12	0	0
T4	578	7	0	0
T5	188	1	0	0
T6	729	2	0	0
T7	230	5	0	0
T8	523	14	0	0
T9	5624	92	0	0
T10	3650	75	0	0

gen_assertions[4].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1591472	1141	0	0
T3	1598	11	0	0
T4	578	1	0	0
T5	188	0	0	0
T6	729	0	0	0
T7	230	0	0	0
T8	523	0	0	0
T9	5624	0	0	0
T10	3650	0	0	0
T11	595	0	0	0
T12	367	0	0	0
T33	0	13	0	0
T41	0	12	0	0
T44	0	2	0	0
T51	0	7	0	0
T53	0	7	0	0
T58	0	6	0	0
T59	0	7	0	0
T87	0	1	0	0

gen_assertions[4].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1591472	20738	0	0
T1	278	3	0	0
T2	25136	271	0	0
T3	1598	12	0	0
T4	578	7	0	0
T5	188	1	0	0
T6	729	2	0	0
T7	230	5	0	0
T8	523	14	0	0
T9	5624	92	0	0
T10	3650	75	0	0

gen_assertions[4].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1591472	1141	0	0
T3	1598	11	0	0
T4	578	1	0	0
T5	188	0	0	0
T6	729	0	0	0
T7	230	0	0	0
T8	523	0	0	0
T9	5624	0	0	0
T10	3650	0	0	0
T11	595	0	0	0
T12	367	0	0	0
T33	0	13	0	0
T41	0	12	0	0
T44	0	2	0	0
T51	0	7	0	0
T53	0	7	0	0
T58	0	6	0	0
T59	0	7	0	0
T87	0	1	0	0

gen_assertions[5].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12606006	13780	0	0
T1	2233	2	0	0
T2	200065	0	0	0
T3	12795	12	0	0
T4	4628	5	0	0
T5	1520	0	0	0
T6	5815	0	0	0
T7	1846	4	0	0
T8	4201	13	0	0
T9	44883	75	0	0
T10	29085	75	0	0
T11	0	4	0	0
T12	0	7	0	0
T13	0	4	0	0

gen_assertions[5].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12606006	1193	0	0
T3	12795	12	0	0
T4	4628	1	0	0
T5	1520	0	0	0
T6	5815	0	0	0
T7	1846	0	0	0
T8	4201	0	0	0
T9	44883	0	0	0
T10	29085	0	0	0
T11	4770	0	0	0
T12	2952	0	0	0
T28	0	1	0	0
T33	0	8	0	0
T41	0	14	0	0
T51	0	7	0	0
T53	0	9	0	0
T58	0	9	0	0
T59	0	13	0	0
T88	0	12	0	0

gen_assertions[5].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12606006	13780	0	0
T1	2233	2	0	0
T2	200065	0	0	0
T3	12795	12	0	0
T4	4628	5	0	0
T5	1520	0	0	0
T6	5815	0	0	0
T7	1846	4	0	0
T8	4201	13	0	0
T9	44883	75	0	0
T10	29085	75	0	0
T11	0	4	0	0
T12	0	7	0	0
T13	0	4	0	0

gen_assertions[5].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12606006	1193	0	0
T3	12795	12	0	0
T4	4628	1	0	0
T5	1520	0	0	0
T6	5815	0	0	0
T7	1846	0	0	0
T8	4201	0	0	0
T9	44883	0	0	0
T10	29085	0	0	0
T11	4770	0	0	0
T12	2952	0	0	0
T28	0	1	0	0
T33	0	8	0	0
T41	0	14	0	0
T51	0	7	0	0
T53	0	9	0	0
T58	0	9	0	0
T59	0	13	0	0
T88	0	12	0	0

gen_assertions[6].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12606006	13855	0	0
T1	2233	2	0	0
T2	200065	0	0	0
T3	12795	12	0	0
T4	4628	5	0	0
T5	1520	0	0	0
T6	5815	0	0	0
T7	1846	4	0	0
T8	4201	13	0	0
T9	44883	75	0	0
T10	29085	75	0	0
T11	0	5	0	0
T12	0	7	0	0
T13	0	5	0	0

gen_assertions[6].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12606006	1276	0	0
T3	12795	12	0	0
T4	4628	1	0	0
T5	1520	0	0	0
T6	5815	0	0	0
T7	1846	0	0	0
T8	4201	0	0	0
T9	44883	0	0	0
T10	29085	0	0	0
T11	4770	1	0	0
T12	2952	0	0	0
T13	0	1	0	0
T41	0	14	0	0
T44	0	1	0	0
T51	0	8	0	0
T53	0	11	0	0
T58	0	11	0	0
T59	0	10	0	0

gen_assertions[6].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12606006	13855	0	0
T1	2233	2	0	0
T2	200065	0	0	0
T3	12795	12	0	0
T4	4628	5	0	0
T5	1520	0	0	0
T6	5815	0	0	0
T7	1846	4	0	0
T8	4201	13	0	0
T9	44883	75	0	0
T10	29085	75	0	0
T11	0	5	0	0
T12	0	7	0	0
T13	0	5	0	0

gen_assertions[6].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12606006	1276	0	0
T3	12795	12	0	0
T4	4628	1	0	0
T5	1520	0	0	0
T6	5815	0	0	0
T7	1846	0	0	0
T8	4201	0	0	0
T9	44883	0	0	0
T10	29085	0	0	0
T11	4770	1	0	0
T12	2952	0	0	0
T13	0	1	0	0
T41	0	14	0	0
T44	0	1	0	0
T51	0	8	0	0
T53	0	11	0	0
T58	0	11	0	0
T59	0	10	0	0

gen_assertions[7].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12606006	13892	0	0
T1	2233	2	0	0
T2	200065	0	0	0
T3	12795	16	0	0
T4	4628	4	0	0
T5	1520	0	0	0
T6	5815	0	0	0
T7	1846	4	0	0
T8	4201	13	0	0
T9	44883	75	0	0
T10	29085	75	0	0
T11	0	4	0	0
T12	0	7	0	0
T13	0	4	0	0

gen_assertions[7].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12606006	1312	0	0
T3	12795	16	0	0
T4	4628	0	0	0
T5	1520	0	0	0
T6	5815	0	0	0
T7	1846	0	0	0
T8	4201	0	0	0
T9	44883	0	0	0
T10	29085	0	0	0
T11	4770	0	0	0
T12	2952	0	0	0
T33	0	12	0	0
T41	0	12	0	0
T44	0	1	0	0
T51	0	11	0	0
T53	0	12	0	0
T58	0	9	0	0
T59	0	9	0	0
T88	0	11	0	0
T89	0	7	0	0

gen_assertions[7].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12606006	13892	0	0
T1	2233	2	0	0
T2	200065	0	0	0
T3	12795	16	0	0
T4	4628	4	0	0
T5	1520	0	0	0
T6	5815	0	0	0
T7	1846	4	0	0
T8	4201	13	0	0
T9	44883	75	0	0
T10	29085	75	0	0
T11	0	4	0	0
T12	0	7	0	0
T13	0	4	0	0

gen_assertions[7].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12606006	1312	0	0
T3	12795	16	0	0
T4	4628	0	0	0
T5	1520	0	0	0
T6	5815	0	0	0
T7	1846	0	0	0
T8	4201	0	0	0
T9	44883	0	0	0
T10	29085	0	0	0
T11	4770	0	0	0
T12	2952	0	0	0
T33	0	12	0	0
T41	0	12	0	0
T44	0	1	0	0
T51	0	11	0	0
T53	0	12	0	0
T58	0	9	0	0
T59	0	9	0	0
T88	0	11	0	0
T89	0	7	0	0