Unified Coverage Report :: Module :: rstmgr_csr_assert_fpv

Module : rstmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rstmgr_csr_assert_0/rstmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rstmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rstmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	19	19	100.00	19	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	19	19	100.00	19	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	11994905	8758	0	0
alert_regwen_rd_A	11994905	5971	0	0
cpu_regwen_rd_A	11994905	6206	0	0
sw_rst_ctrl_n_0_rd_A	11994905	11420	0	0
sw_rst_ctrl_n_1_rd_A	11994905	11852	0	0
sw_rst_ctrl_n_2_rd_A	11994905	11625	0	0
sw_rst_ctrl_n_3_rd_A	11994905	11722	0	0
sw_rst_ctrl_n_4_rd_A	11994905	11648	0	0
sw_rst_ctrl_n_5_rd_A	11994905	11416	0	0
sw_rst_ctrl_n_6_rd_A	11994905	11626	0	0
sw_rst_ctrl_n_7_rd_A	11994905	11828	0	0
sw_rst_regwen_0_rd_A	11994905	6670	0	0
sw_rst_regwen_1_rd_A	11994905	6676	0	0
sw_rst_regwen_2_rd_A	11994905	6728	0	0
sw_rst_regwen_3_rd_A	11994905	6795	0	0
sw_rst_regwen_4_rd_A	11994905	6636	0	0
sw_rst_regwen_5_rd_A	11994905	6665	0	0
sw_rst_regwen_6_rd_A	11994905	6665	0	0
sw_rst_regwen_7_rd_A	11994905	7019	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11994905	8758	0	0
T64	21273	1	0	0
T65	24618	1	0	0
T67	11134	392	0	0
T68	3831	254	0	0
T69	2469	58	0	0
T70	18024	4	0	0
T77	21345	1	0	0
T78	4229	126	0	0
T83	3900	54	0	0
T92	3959	14	0	0

alert_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11994905	5971	0	0
T34	53514	0	0	0
T45	42070	0	0	0
T50	4102	0	0	0
T51	2892	0	0	0
T52	5670	0	0	0
T53	10387	0	0	0
T54	31699	0	0	0
T55	2115	0	0	0
T56	40201	54	0	0
T59	104947	143	0	0
T94	0	54	0	0
T95	0	55	0	0
T100	0	34	0	0
T111	0	32	0	0
T112	0	64	0	0
T113	0	511	0	0
T114	0	50	0	0
T115	0	37	0	0

cpu_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11994905	6206	0	0
T34	53514	0	0	0
T45	42070	0	0	0
T50	4102	0	0	0
T51	2892	0	0	0
T52	5670	0	0	0
T53	10387	0	0	0
T54	31699	0	0	0
T55	2115	0	0	0
T56	40201	38	0	0
T59	104947	126	0	0
T94	0	51	0	0
T95	0	50	0	0
T100	0	27	0	0
T111	0	18	0	0
T112	0	75	0	0
T113	0	529	0	0
T114	0	61	0	0
T115	0	42	0	0

sw_rst_ctrl_n_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11994905	11420	0	0
T1	1943	13	0	0
T2	194594	0	0	0
T3	12705	203	0	0
T4	4339	0	0	0
T5	1478	0	0	0
T6	5466	0	0	0
T7	1517	0	0	0
T8	3302	0	0	0
T9	42238	0	0	0
T10	26118	0	0	0
T28	0	7	0	0
T33	0	195	0	0
T53	0	144	0	0
T56	0	69	0	0
T59	0	252	0	0
T87	0	8	0	0
T94	0	68	0	0
T95	0	46	0	0

sw_rst_ctrl_n_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11994905	11852	0	0
T1	1943	2	0	0
T2	194594	0	0	0
T3	12705	226	0	0
T4	4339	0	0	0
T5	1478	0	0	0
T6	5466	0	0	0
T7	1517	0	0	0
T8	3302	0	0	0
T9	42238	0	0	0
T10	26118	0	0	0
T28	0	17	0	0
T33	0	123	0	0
T53	0	155	0	0
T56	0	80	0	0
T59	0	299	0	0
T87	0	2	0	0
T94	0	46	0	0
T95	0	61	0	0

sw_rst_ctrl_n_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11994905	11625	0	0
T1	1943	11	0	0
T2	194594	0	0	0
T3	12705	231	0	0
T4	4339	0	0	0
T5	1478	0	0	0
T6	5466	0	0	0
T7	1517	0	0	0
T8	3302	0	0	0
T9	42238	0	0	0
T10	26118	0	0	0
T28	0	16	0	0
T33	0	103	0	0
T53	0	147	0	0
T56	0	48	0	0
T59	0	262	0	0
T87	0	6	0	0
T94	0	46	0	0
T95	0	57	0	0

sw_rst_ctrl_n_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11994905	11722	0	0
T1	1943	9	0	0
T2	194594	0	0	0
T3	12705	230	0	0
T4	4339	0	0	0
T5	1478	0	0	0
T6	5466	0	0	0
T7	1517	0	0	0
T8	3302	0	0	0
T9	42238	0	0	0
T10	26118	0	0	0
T28	0	19	0	0
T33	0	102	0	0
T53	0	156	0	0
T56	0	58	0	0
T59	0	265	0	0
T87	0	20	0	0
T94	0	52	0	0
T95	0	47	0	0

sw_rst_ctrl_n_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11994905	11648	0	0
T1	1943	12	0	0
T2	194594	0	0	0
T3	12705	171	0	0
T4	4339	0	0	0
T5	1478	0	0	0
T6	5466	0	0	0
T7	1517	0	0	0
T8	3302	0	0	0
T9	42238	0	0	0
T10	26118	0	0	0
T28	0	11	0	0
T33	0	95	0	0
T53	0	180	0	0
T56	0	63	0	0
T59	0	309	0	0
T87	0	6	0	0
T94	0	61	0	0
T95	0	29	0	0

sw_rst_ctrl_n_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11994905	11416	0	0
T1	1943	8	0	0
T2	194594	0	0	0
T3	12705	205	0	0
T4	4339	0	0	0
T5	1478	0	0	0
T6	5466	0	0	0
T7	1517	0	0	0
T8	3302	0	0	0
T9	42238	0	0	0
T10	26118	0	0	0
T28	0	14	0	0
T33	0	127	0	0
T53	0	138	0	0
T56	0	64	0	0
T59	0	286	0	0
T87	0	17	0	0
T94	0	43	0	0
T95	0	57	0	0

sw_rst_ctrl_n_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11994905	11626	0	0
T1	1943	11	0	0
T2	194594	0	0	0
T3	12705	197	0	0
T4	4339	0	0	0
T5	1478	0	0	0
T6	5466	0	0	0
T7	1517	0	0	0
T8	3302	0	0	0
T9	42238	0	0	0
T10	26118	0	0	0
T28	0	19	0	0
T33	0	149	0	0
T53	0	162	0	0
T56	0	53	0	0
T59	0	299	0	0
T87	0	4	0	0
T94	0	54	0	0
T95	0	39	0	0

sw_rst_ctrl_n_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11994905	11828	0	0
T1	1943	3	0	0
T2	194594	0	0	0
T3	12705	193	0	0
T4	4339	0	0	0
T5	1478	0	0	0
T6	5466	0	0	0
T7	1517	0	0	0
T8	3302	0	0	0
T9	42238	0	0	0
T10	26118	0	0	0
T28	0	18	0	0
T33	0	138	0	0
T53	0	173	0	0
T56	0	72	0	0
T59	0	302	0	0
T94	0	47	0	0
T95	0	47	0	0
T116	0	156	0	0

sw_rst_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11994905	6670	0	0
T3	12705	23	0	0
T4	4339	0	0	0
T5	1478	0	0	0
T6	5466	0	0	0
T7	1517	0	0	0
T8	3302	0	0	0
T9	42238	0	0	0
T10	26118	0	0	0
T11	4529	0	0	0
T12	2395	0	0	0
T28	0	11	0	0
T33	0	32	0	0
T53	0	22	0	0
T56	0	52	0	0
T59	0	131	0	0
T87	0	1	0	0
T94	0	54	0	0
T95	0	36	0	0
T116	0	38	0	0

sw_rst_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11994905	6676	0	0
T3	12705	34	0	0
T4	4339	0	0	0
T5	1478	0	0	0
T6	5466	0	0	0
T7	1517	0	0	0
T8	3302	0	0	0
T9	42238	0	0	0
T10	26118	0	0	0
T11	4529	0	0	0
T12	2395	0	0	0
T28	0	10	0	0
T33	0	9	0	0
T53	0	26	0	0
T56	0	38	0	0
T59	0	136	0	0
T87	0	5	0	0
T94	0	56	0	0
T95	0	77	0	0
T116	0	31	0	0

sw_rst_regwen_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11994905	6728	0	0
T3	12705	26	0	0
T4	4339	0	0	0
T5	1478	0	0	0
T6	5466	0	0	0
T7	1517	0	0	0
T8	3302	0	0	0
T9	42238	0	0	0
T10	26118	0	0	0
T11	4529	0	0	0
T12	2395	0	0	0
T28	0	8	0	0
T33	0	30	0	0
T53	0	33	0	0
T56	0	48	0	0
T59	0	141	0	0
T94	0	45	0	0
T95	0	40	0	0
T100	0	39	0	0
T116	0	53	0	0

sw_rst_regwen_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11994905	6795	0	0
T3	12705	29	0	0
T4	4339	0	0	0
T5	1478	0	0	0
T6	5466	0	0	0
T7	1517	0	0	0
T8	3302	0	0	0
T9	42238	0	0	0
T10	26118	0	0	0
T11	4529	0	0	0
T12	2395	0	0	0
T28	0	9	0	0
T33	0	35	0	0
T53	0	27	0	0
T56	0	66	0	0
T59	0	164	0	0
T87	0	4	0	0
T94	0	57	0	0
T95	0	60	0	0
T116	0	33	0	0

sw_rst_regwen_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11994905	6636	0	0
T3	12705	39	0	0
T4	4339	0	0	0
T5	1478	0	0	0
T6	5466	0	0	0
T7	1517	0	0	0
T8	3302	0	0	0
T9	42238	0	0	0
T10	26118	0	0	0
T11	4529	0	0	0
T12	2395	0	0	0
T28	0	15	0	0
T33	0	14	0	0
T53	0	45	0	0
T56	0	59	0	0
T59	0	139	0	0
T94	0	76	0	0
T95	0	51	0	0
T100	0	21	0	0
T116	0	24	0	0

sw_rst_regwen_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11994905	6665	0	0
T3	12705	42	0	0
T4	4339	0	0	0
T5	1478	0	0	0
T6	5466	0	0	0
T7	1517	0	0	0
T8	3302	0	0	0
T9	42238	0	0	0
T10	26118	0	0	0
T11	4529	0	0	0
T12	2395	0	0	0
T28	0	9	0	0
T33	0	15	0	0
T53	0	39	0	0
T56	0	39	0	0
T59	0	106	0	0
T87	0	1	0	0
T94	0	65	0	0
T95	0	55	0	0
T116	0	36	0	0

sw_rst_regwen_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11994905	6665	0	0
T3	12705	28	0	0
T4	4339	0	0	0
T5	1478	0	0	0
T6	5466	0	0	0
T7	1517	0	0	0
T8	3302	0	0	0
T9	42238	0	0	0
T10	26118	0	0	0
T11	4529	0	0	0
T12	2395	0	0	0
T28	0	3	0	0
T33	0	5	0	0
T53	0	41	0	0
T56	0	92	0	0
T59	0	148	0	0
T87	0	2	0	0
T94	0	58	0	0
T95	0	53	0	0
T116	0	40	0	0

sw_rst_regwen_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11994905	7019	0	0
T3	12705	27	0	0
T4	4339	0	0	0
T5	1478	0	0	0
T6	5466	0	0	0
T7	1517	0	0	0
T8	3302	0	0	0
T9	42238	0	0	0
T10	26118	0	0	0
T11	4529	0	0	0
T12	2395	0	0	0
T28	0	5	0	0
T33	0	15	0	0
T53	0	35	0	0
T56	0	56	0	0
T59	0	123	0	0
T87	0	6	0	0
T94	0	60	0	0
T95	0	67	0	0
T116	0	44	0	0