Unified Coverage Report :: Group :: rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

Group : rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_env_0.1/rstmgr_env_cov.sv

---

Summary for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
enable_cp	2	0	2	100.00	100	1	1	2
reset_info_cp	8	0	8	100.00	100	1	1	0

Crosses for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
capture_cross	16	0	16	100.00	100	1	1	0

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9094

1

T1

36

T7

165

T10

149

auto[1]

11911

1

T1

12

T4

4

T6

4

---

Summary for Variable reset_info_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for reset_info_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
others	6388	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	7039	1			T1	19		T2	1		T3	1
reset_info_cp[2]	3220	1			T1	10		T4	1		T6	1
reset_info_cp[4]	4374	1			T1	8		T4	1		T6	1
reset_info_cp[8]	135	1			T7	1		T10	1		T12	1
reset_info_cp[16]	113	1			T1	1		T10	1		T22	1
reset_info_cp[32]	109	1			T7	2		T10	1		T21	1
reset_info_cp[64]	126	1			T7	1		T21	1		T97	1
reset_info_cp[128]	120	1			T7	3		T10	1		T22	1

---

Summary for Cross capture_cross

Samples crossed: reset_info_cp enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for capture_cross

Bins

reset_info_cp	enable_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	auto[0]	3316	1			T1	12		T7	47		T10	54
reset_info_cp[1]	auto[1]	3104	1			T1	6		T4	1		T6	1
reset_info_cp[2]	auto[0]	1065	1			T1	9		T7	26		T10	18
reset_info_cp[2]	auto[1]	2155	1			T1	1		T4	1		T6	1
reset_info_cp[4]	auto[0]	1641	1			T1	4		T7	29		T10	30
reset_info_cp[4]	auto[1]	2733	1			T1	4		T4	1		T6	1
reset_info_cp[8]	auto[0]	51	1			T7	1		T22	1		T106	1
reset_info_cp[8]	auto[1]	84	1			T10	1		T12	1		T21	3
reset_info_cp[16]	auto[0]	46	1			T1	1		T22	1		T98	1
reset_info_cp[16]	auto[1]	67	1			T10	1		T98	1		T26	1
reset_info_cp[32]	auto[0]	33	1			T7	1		T22	1		T105	1
reset_info_cp[32]	auto[1]	76	1			T7	1		T10	1		T21	1
reset_info_cp[64]	auto[0]	55	1			T99	2		T134	1		T135	1
reset_info_cp[64]	auto[1]	71	1			T7	1		T21	1		T97	1
reset_info_cp[128]	auto[0]	49	1			T7	2		T98	1		T100	1
reset_info_cp[128]	auto[1]	71	1			T7	1		T10	1		T22	1