---

Detail Report for Assertions

Assertions Uncovered:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstPorAonEnTracksRstPorAonActive_A	0	0	1660647	0	0	0
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstPorEnTracksRstPorInactive_A	0	0	54743812	0	0	0
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstPorIoDiv4EnTracksRstPorIoDiv4Active_A	0	0	13138146	0	0	0
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstPorIoEnTracksRstPorIoInactive_A	0	0	52552100	0	0	0

Assertions Success:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.AlertsKnownO_A	0	0	11539416	6806657	0	0
tb.dut.FpvSecCmRegWeOnehotCheck_A	0	0	11539416	60	0	0
tb.dut.ParameterMatch_A	0	0	504	504	0	0
tb.dut.PwrKnownO_A	0	0	11539416	6806657	0	0
tb.dut.ResetsKnownO_A	0	0	11539416	6806657	0	0
tb.dut.RstEnKnownO_A	0	0	11539416	6806657	0	0
tb.dut.TlAReadyKnownO_A	0	0	11539416	6806657	0	0
tb.dut.TlDValidKnownO_A	0	0	11539416	6806657	0	0
tb.dut.gen_d0_i2c0_assert.FpvSecCmD0I2c0FsmCheck_A	0	0	11539416	60	0	0
tb.dut.gen_d0_i2c1_assert.FpvSecCmD0I2c1FsmCheck_A	0	0	11539416	60	0	0
tb.dut.gen_d0_i2c2_assert.FpvSecCmD0I2c2FsmCheck_A	0	0	11539416	60	0	0
tb.dut.gen_d0_lc_assert.FpvSecCmD0LcFsmCheck_A	0	0	11539416	60	0	0
tb.dut.gen_d0_lc_io_assert.FpvSecCmD0LcIoFsmCheck_A	0	0	11539416	60	0	0
tb.dut.gen_d0_lc_io_div2_assert.FpvSecCmD0LcIoDiv2FsmCheck_A	0	0	11539416	60	0	0
tb.dut.gen_d0_lc_shadowed_assert.FpvSecCmD0LcShadowedFsmCheck_A	0	0	11539416	60	0	0
tb.dut.gen_d0_lc_usb_assert.FpvSecCmD0LcUsbFsmCheck_A	0	0	11539416	60	0	0
tb.dut.gen_d0_spi_device_assert.FpvSecCmD0SpiDeviceFsmCheck_A	0	0	11539416	60	0	0
tb.dut.gen_d0_spi_host0_assert.FpvSecCmD0SpiHost0FsmCheck_A	0	0	11539416	60	0	0
tb.dut.gen_d0_spi_host1_assert.FpvSecCmD0SpiHost1FsmCheck_A	0	0	11539416	60	0	0
tb.dut.gen_d0_sys_assert.FpvSecCmD0SysFsmCheck_A	0	0	11539416	60	0	0
tb.dut.gen_d0_usb_aon_assert.FpvSecCmD0UsbAonFsmCheck_A	0	0	11539416	60	0	0
tb.dut.gen_d0_usb_assert.FpvSecCmD0UsbFsmCheck_A	0	0	11539416	60	0	0
tb.dut.gen_daon_lc_aon_assert.FpvSecCmDAonLcAonFsmCheck_A	0	0	11539416	60	0	0
tb.dut.gen_daon_lc_assert.FpvSecCmDAonLcFsmCheck_A	0	0	11539416	60	0	0
tb.dut.gen_daon_lc_io_assert.FpvSecCmDAonLcIoFsmCheck_A	0	0	11539416	60	0	0
tb.dut.gen_daon_lc_io_div2_assert.FpvSecCmDAonLcIoDiv2FsmCheck_A	0	0	11539416	60	0	0
tb.dut.gen_daon_lc_shadowed_assert.FpvSecCmDAonLcShadowedFsmCheck_A	0	0	11539416	60	0	0
tb.dut.gen_daon_lc_usb_assert.FpvSecCmDAonLcUsbFsmCheck_A	0	0	11539416	60	0	0
tb.dut.gen_daon_por_assert.FpvSecCmDAonPorFsmCheck_A	0	0	11539416	60	0	0
tb.dut.gen_daon_por_io_assert.FpvSecCmDAonPorIoFsmCheck_A	0	0	11539416	60	0	0
tb.dut.gen_daon_por_io_div2_assert.FpvSecCmDAonPorIoDiv2FsmCheck_A	0	0	11539416	60	0	0
tb.dut.gen_daon_por_io_div4_assert.FpvSecCmDAonPorIoDiv4FsmCheck_A	0	0	11539416	60	0	0
tb.dut.gen_daon_por_usb_assert.FpvSecCmDAonPorUsbFsmCheck_A	0	0	11539416	60	0	0
tb.dut.gen_daon_sys_io_div4_assert.FpvSecCmDAonSysIoDiv4FsmCheck_A	0	0	11539416	60	0	0
tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_prim_mubi4_sender.OutputsKnown_A	0	0	1660647	1025180	0	0
tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_rst_por_aon.u_rst_clean_mux.gen_generic.u_impl_generic.selKnown0	0	0	9204	8700	0	0
tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_rst_por_aon.u_rst_clean_mux.gen_generic.u_impl_generic.selKnown1	0	0	3081	2577	0	0
tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_rst_por_aon.u_rst_out_mux.gen_generic.u_impl_generic.selKnown0	0	0	8841	8337	0	0
tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_rst_por_aon.u_rst_out_mux.gen_generic.u_impl_generic.selKnown1	0	0	3081	2577	0	0
tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_rst_por_aon.u_rst_root_mux.gen_generic.u_impl_generic.selKnown0	0	0	6666	6162	0	0
tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_rst_por_aon.u_rst_root_mux.gen_generic.u_impl_generic.selKnown1	0	0	3081	2577	0	0
tb.dut.gen_rst_por_aon[0].u_por_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	504	504	0	0
tb.dut.gen_rst_por_aon[0].u_por_scanmode_sync.OutputsKnown_A	0	0	11539416	6806657	0	0
tb.dut.gen_rst_por_aon[0].u_por_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	11539416	6806657	0	0
tb.dut.gen_rst_por_aon[1].gen_rst_por_domain.u_por_domain_mux.gen_generic.u_impl_generic.selKnown0	0	0	8841	8337	0	0
tb.dut.gen_rst_por_aon[1].gen_rst_por_domain.u_por_domain_mux.gen_generic.u_impl_generic.selKnown1	0	0	3081	2577	0	0
tb.dut.gen_rst_por_aon[1].gen_rst_por_domain.u_prim_mubi4_sender.OutputsKnown_A	0	0	1660647	1006599	0	0
tb.dut.gen_rst_por_aon[1].u_por_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	504	504	0	0
tb.dut.gen_rst_por_aon[1].u_por_scanmode_sync.OutputsKnown_A	0	0	11539416	6806657	0	0
tb.dut.gen_rst_por_aon[1].u_por_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	11539416	6806657	0	0
tb.dut.pwrmgr_rstmgr_sva_if.gen_assertions_per_power_domains[0].LcHandshakeOff_A	0	0	11539416	14155	0	0
tb.dut.pwrmgr_rstmgr_sva_if.gen_assertions_per_power_domains[0].LcHandshakeOn_A	0	0	11539416	130548	0	0
tb.dut.pwrmgr_rstmgr_sva_if.gen_assertions_per_power_domains[0].SysHandshakeOff_A	0	0	11539416	6847616	0	0
tb.dut.pwrmgr_rstmgr_sva_if.gen_assertions_per_power_domains[0].SysHandshakeOn_A	0	0	11539416	208885	0	0
tb.dut.pwrmgr_rstmgr_sva_if.gen_assertions_per_power_domains[1].LcHandshakeOff_A	0	0	11539416	14155	0	0
tb.dut.pwrmgr_rstmgr_sva_if.gen_assertions_per_power_domains[1].LcHandshakeOn_A	0	0	11539416	130548	0	0
tb.dut.pwrmgr_rstmgr_sva_if.gen_assertions_per_power_domains[1].SysHandshakeOff_A	0	0	11539416	6847616	0	0
tb.dut.pwrmgr_rstmgr_sva_if.gen_assertions_per_power_domains[1].SysHandshakeOn_A	0	0	11539416	208885	0	0
tb.dut.rstmgr_attrs_sva_if.AlertInfoAttr_A	0	0	504	504	0	0
tb.dut.rstmgr_attrs_sva_if.CpuInfoAttr_A	0	0	504	504	0	0
tb.dut.rstmgr_cascading_sva_if.CascadeEffAonToRstPorAboveFall_A	0	0	54743812	8841	0	0
tb.dut.rstmgr_cascading_sva_if.CascadeEffAonToRstPorAboveRise_A	0	0	54743812	8841	0	0
tb.dut.rstmgr_cascading_sva_if.CascadeEffAonToRstPorIoAboveFall_A	0	0	52552100	8841	0	0
tb.dut.rstmgr_cascading_sva_if.CascadeEffAonToRstPorIoAboveRise_A	0	0	52552100	8841	0	0
tb.dut.rstmgr_cascading_sva_if.CascadeEffAonToRstPorIoDiv2AboveFall_A	0	0	26276811	8841	0	0
tb.dut.rstmgr_cascading_sva_if.CascadeEffAonToRstPorIoDiv2AboveRise_A	0	0	26276811	8841	0	0
tb.dut.rstmgr_cascading_sva_if.CascadeEffAonToRstPorIoDiv4AboveFall_A	0	0	13138146	8841	0	0
tb.dut.rstmgr_cascading_sva_if.CascadeEffAonToRstPorIoDiv4AboveRise_A	0	0	13138146	8841	0	0
tb.dut.rstmgr_cascading_sva_if.CascadeEffAonToRstPorUcbAboveFall_A	0	0	26276817	8841	0	0
tb.dut.rstmgr_cascading_sva_if.CascadeEffAonToRstPorUcbAboveRise_A	0	0	26276817	8841	0	0
tb.dut.rstmgr_cascading_sva_if.CascadeLcToLcAboveFall_A	0	0	54743812	22996	0	0
tb.dut.rstmgr_cascading_sva_if.CascadeLcToLcAboveRise_A	0	0	54743812	22996	0	0
tb.dut.rstmgr_cascading_sva_if.CascadeLcToLcAonAboveFall_A	0	0	1660647	22996	0	0
tb.dut.rstmgr_cascading_sva_if.CascadeLcToLcAonAboveRise_A	0	0	1660647	22996	0	0
tb.dut.rstmgr_cascading_sva_if.CascadeLcToLcShadowedAboveFall_A	0	0	54743812	22996	0	0
tb.dut.rstmgr_cascading_sva_if.CascadeLcToLcShadowedAboveRise_A	0	0	54743812	22996	0	0
tb.dut.rstmgr_cascading_sva_if.CascadePorToAonAboveFall_A	0	0	1660647	6683	0	0
tb.dut.rstmgr_cascading_sva_if.CascadeSysToSysAboveFall_A	0	0	54743812	22996	0	0
tb.dut.rstmgr_cascading_sva_if.CascadeSysToSysAboveRise_A	0	0	54743812	22996	0	0
tb.dut.rstmgr_cascading_sva_if.ScanRstToAonRise_A	0	0	1660647	252	0	0
tb.dut.rstmgr_cascading_sva_if.StablePorToAonRise_A	0	0	1660647	8841	0	0
tb.dut.rstmgr_cascading_sva_if.g_power_domains[0].CascadeLcToSysAboveFall_A	0	0	11539416	22996	0	0
tb.dut.rstmgr_cascading_sva_if.g_power_domains[0].CascadeLcToSysAboveRise_A	0	0	11539416	22996	0	0
tb.dut.rstmgr_cascading_sva_if.g_power_domains[0].CascadeLocalRstToLcAboveFall_A	0	0	11539416	22996	0	0
tb.dut.rstmgr_cascading_sva_if.g_power_domains[0].CascadeLocalRstToLcAboveRise_A	0	0	11539416	22996	0	0
tb.dut.rstmgr_cascading_sva_if.g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A	0	0	13138146	22996	0	0
tb.dut.rstmgr_cascading_sva_if.g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A	0	0	13138146	22996	0	0
tb.dut.rstmgr_cascading_sva_if.g_power_domains[1].CascadeLcToSysAboveFall_A	0	0	11539416	22996	0	0
tb.dut.rstmgr_cascading_sva_if.g_power_domains[1].CascadeLcToSysAboveRise_A	0	0	11539416	22996	0	0
tb.dut.rstmgr_cascading_sva_if.g_power_domains[1].CascadeLocalRstToLcAboveFall_A	0	0	11539416	22996	0	0
tb.dut.rstmgr_cascading_sva_if.g_power_domains[1].CascadeLocalRstToLcAboveRise_A	0	0	11539416	22996	0	0
tb.dut.rstmgr_csr_assert.TlulOOBAddrErr_A	0	0	12301499	6897	0	0
tb.dut.rstmgr_csr_assert.alert_regwen_rd_A	0	0	12301499	4888	0	0
tb.dut.rstmgr_csr_assert.cpu_regwen_rd_A	0	0	12301499	5057	0	0
tb.dut.rstmgr_csr_assert.sw_rst_ctrl_n_0_rd_A	0	0	12301499	9154	0	0
tb.dut.rstmgr_csr_assert.sw_rst_ctrl_n_1_rd_A	0	0	12301499	8845	0	0
tb.dut.rstmgr_csr_assert.sw_rst_ctrl_n_2_rd_A	0	0	12301499	8840	0	0
tb.dut.rstmgr_csr_assert.sw_rst_ctrl_n_3_rd_A	0	0	12301499	9058	0	0
tb.dut.rstmgr_csr_assert.sw_rst_ctrl_n_4_rd_A	0	0	12301499	9114	0	0
tb.dut.rstmgr_csr_assert.sw_rst_ctrl_n_5_rd_A	0	0	12301499	8988	0	0
tb.dut.rstmgr_csr_assert.sw_rst_ctrl_n_6_rd_A	0	0	12301499	8974	0	0
tb.dut.rstmgr_csr_assert.sw_rst_ctrl_n_7_rd_A	0	0	12301499	8979	0	0
tb.dut.rstmgr_csr_assert.sw_rst_regwen_0_rd_A	0	0	12301499	5377	0	0
tb.dut.rstmgr_csr_assert.sw_rst_regwen_1_rd_A	0	0	12301499	5543	0	0
tb.dut.rstmgr_csr_assert.sw_rst_regwen_2_rd_A	0	0	12301499	5540	0	0
tb.dut.rstmgr_csr_assert.sw_rst_regwen_3_rd_A	0	0	12301499	5321	0	0
tb.dut.rstmgr_csr_assert.sw_rst_regwen_4_rd_A	0	0	12301499	5503	0	0
tb.dut.rstmgr_csr_assert.sw_rst_regwen_5_rd_A	0	0	12301499	5540	0	0
tb.dut.rstmgr_csr_assert.sw_rst_regwen_6_rd_A	0	0	12301499	5553	0	0
tb.dut.rstmgr_csr_assert.sw_rst_regwen_7_rd_A	0	0	12301499	5405	0	0
tb.dut.rstmgr_rst_en_track_sva_if.D0RstI2c0EnTracksRstI2c0Active_A	0	0	13138146	15395	0	0
tb.dut.rstmgr_rst_en_track_sva_if.D0RstI2c0EnTracksRstI2c0Inactive_A	0	0	13138146	24128	0	0
tb.dut.rstmgr_rst_en_track_sva_if.D0RstI2c1EnTracksRstI2c1Active_A	0	0	13138146	15455	0	0
tb.dut.rstmgr_rst_en_track_sva_if.D0RstI2c1EnTracksRstI2c1Inactive_A	0	0	13138146	24179	0	0
tb.dut.rstmgr_rst_en_track_sva_if.D0RstI2c2EnTracksRstI2c2Active_A	0	0	13138146	15485	0	0
tb.dut.rstmgr_rst_en_track_sva_if.D0RstI2c2EnTracksRstI2c2Inactive_A	0	0	13138146	24215	0	0
tb.dut.rstmgr_rst_en_track_sva_if.D0RstLcIoDiv2EnTracksRstLcIoDiv2Active_A	0	0	26276811	14226	0	0
tb.dut.rstmgr_rst_en_track_sva_if.D0RstLcIoDiv2EnTracksRstLcIoDiv2Inactive_A	0	0	26276811	22996	0	0
tb.dut.rstmgr_rst_en_track_sva_if.D0RstLcIoDiv4ShadowedEnTracksRstLcIoDiv4ShadowedActive_A	0	0	13138146	14255	0	0
tb.dut.rstmgr_rst_en_track_sva_if.D0RstLcIoDiv4ShadowedEnTracksRstLcIoDiv4ShadowedInactive_A	0	0	13138146	23046	0	0
tb.dut.rstmgr_rst_en_track_sva_if.D0RstLcIoEnTracksRstLcIoActive_A	0	0	52552100	14231	0	0
tb.dut.rstmgr_rst_en_track_sva_if.D0RstLcIoEnTracksRstLcIoInactive_A	0	0	52552100	22996	0	0
tb.dut.rstmgr_rst_en_track_sva_if.D0RstLcShadowedEnTracksRstLcShadowedActive_A	0	0	54743812	14205	0	0
tb.dut.rstmgr_rst_en_track_sva_if.D0RstLcShadowedEnTracksRstLcShadowedInactive_A	0	0	54743812	22996	0	0
tb.dut.rstmgr_rst_en_track_sva_if.D0RstLcUsbEnTracksRstLcUsbActive_A	0	0	26276817	14229	0	0
tb.dut.rstmgr_rst_en_track_sva_if.D0RstLcUsbEnTracksRstLcUsbInactive_A	0	0	26276817	22996	0	0
tb.dut.rstmgr_rst_en_track_sva_if.D0RstPorAonEnTracksRstPorAonActive_A	0	0	1660647	50	0	0
tb.dut.rstmgr_rst_en_track_sva_if.D0RstPorAonEnTracksRstPorAonInactive_A	0	0	1660647	8823	0	0
tb.dut.rstmgr_rst_en_track_sva_if.D0RstSpiDeviceEnTracksRstSpiDeviceActive_A	0	0	13138146	15133	0	0
tb.dut.rstmgr_rst_en_track_sva_if.D0RstSpiDeviceEnTracksRstSpiDeviceInactive_A	0	0	13138146	23874	0	0
tb.dut.rstmgr_rst_en_track_sva_if.D0RstSpiHost0EnTracksRstSpiHost0Active_A	0	0	52552100	15193	0	0
tb.dut.rstmgr_rst_en_track_sva_if.D0RstSpiHost0EnTracksRstSpiHost0Inactive_A	0	0	52552100	23923	0	0
tb.dut.rstmgr_rst_en_track_sva_if.D0RstSpiHost1EnTracksRstSpiHost1Active_A	0	0	26276811	15249	0	0
tb.dut.rstmgr_rst_en_track_sva_if.D0RstSpiHost1EnTracksRstSpiHost1Inactive_A	0	0	26276811	23988	0	0
tb.dut.rstmgr_rst_en_track_sva_if.D0RstSysEnTracksRstSysActive_A	0	0	54743812	14225	0	0
tb.dut.rstmgr_rst_en_track_sva_if.D0RstSysEnTracksRstSysInactive_A	0	0	54743812	22996	0	0
tb.dut.rstmgr_rst_en_track_sva_if.D0RstUsbAonEnTracksRstUsbAonActive_A	0	0	1660647	14798	0	0
tb.dut.rstmgr_rst_en_track_sva_if.D0RstUsbAonEnTracksRstUsbAonInactive_A	0	0	1660647	23121	0	0
tb.dut.rstmgr_rst_en_track_sva_if.D0RstUsbEnTracksRstUsbActive_A	0	0	26276817	15272	0	0
tb.dut.rstmgr_rst_en_track_sva_if.D0RstUsbEnTracksRstUsbInactive_A	0	0	26276817	24007	0	0
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstLcAonEnTracksRstLcAonActive_A	0	0	1660647	14180	0	0
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstLcAonEnTracksRstLcAonInactive_A	0	0	1660647	22978	0	0
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstLcIoDiv2EnTracksRstLcIoDiv2Active_A	0	0	26276811	14183	0	0
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstLcIoDiv2EnTracksRstLcIoDiv2Inactive_A	0	0	26276811	22996	0	0
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstLcIoDiv4ShadowedEnTracksRstLcIoDiv4ShadowedActive_A	0	0	13138146	14205	0	0
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstLcIoDiv4ShadowedEnTracksRstLcIoDiv4ShadowedInactive_A	0	0	13138146	23046	0	0
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstLcIoEnTracksRstLcIoActive_A	0	0	52552100	14183	0	0
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstLcIoEnTracksRstLcIoInactive_A	0	0	52552100	22996	0	0
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstLcShadowedEnTracksRstLcShadowedActive_A	0	0	54743812	14227	0	0
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstLcShadowedEnTracksRstLcShadowedInactive_A	0	0	54743812	23046	0	0
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstLcUsbEnTracksRstLcUsbActive_A	0	0	26276817	14178	0	0
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstLcUsbEnTracksRstLcUsbInactive_A	0	0	26276817	22996	0	0
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstPorAonEnTracksRstPorAonInactive_A	0	0	1660647	8841	0	0
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstPorEnTracksRstPorActive_A	0	0	54743812	27	0	0
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstPorIoDiv2EnTracksRstPorIoDiv2Active_A	0	0	26276811	27	0	0
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstPorIoDiv2EnTracksRstPorIoDiv2Inactive_A	0	0	26276811	2183	0	0
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstPorIoDiv4EnTracksRstPorIoDiv4Inactive_A	0	0	13138146	8841	0	0
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstPorIoEnTracksRstPorIoActive_A	0	0	52552100	24	0	0
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstPorUsbEnTracksRstPorUsbActive_A	0	0	26276817	22	0	0
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstPorUsbEnTracksRstPorUsbInactive_A	0	0	26276817	2183	0	0
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstSysIoDiv4EnTracksRstSysIoDiv4Active_A	0	0	13138146	14177	0	0
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstSysIoDiv4EnTracksRstSysIoDiv4Inactive_A	0	0	13138146	22996	0	0
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[0].RstEnOff_A	0	0	13138146	15031	0	0
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[0].RstEnOn_A	0	0	13138146	1068	0	0
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tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[0].RstNOn_A	0	0	13138146	1068	0	0
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[1].RstEnOff_A	0	0	52552100	13694	0	0
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[1].RstEnOn_A	0	0	52552100	1024	0	0
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[1].RstNOff_A	0	0	52552100	13694	0	0
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[1].RstNOn_A	0	0	52552100	1024	0	0
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tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[3].RstNOn_A	0	0	26276817	1040	0	0
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tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[4].RstEnOn_A	0	0	1660647	1119	0	0
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tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[4].RstNOn_A	0	0	1660647	1119	0	0
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tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[5].RstEnOn_A	0	0	13138146	1164	0	0
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tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[5].RstNOn_A	0	0	13138146	1164	0	0
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tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[6].RstEnOn_A	0	0	13138146	1223	0	0
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tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[6].RstNOn_A	0	0	13138146	1223	0	0
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[7].RstEnOff_A	0	0	13138146	15372	0	0
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[7].RstEnOn_A	0	0	13138146	1253	0	0
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tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[7].RstNOn_A	0	0	13138146	1253	0	0
tb.dut.tlul_assert_device.aKnown_A	0	0	12301499	1208173	0	0
tb.dut.tlul_assert_device.aKnown_AKnownEnable	0	0	12301499	7280306	0	0
tb.dut.tlul_assert_device.aReadyKnown_A	0	0	12301499	7280306	0	0
tb.dut.tlul_assert_device.dKnown_A	0	0	12301499	1974187	0	0
tb.dut.tlul_assert_device.dKnown_AKnownEnable	0	0	12301499	7280306	0	0
tb.dut.tlul_assert_device.dReadyKnown_A	0	0	12301499	7280306	0	0
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tb.dut.tlul_assert_device.gen_assert_final[100].noOutstandingReqsAtEndOfSim_A	0	0	619	619	0	0
tb.dut.tlul_assert_device.gen_assert_final[101].noOutstandingReqsAtEndOfSim_A	0	0	619	619	0	0
tb.dut.tlul_assert_device.gen_assert_final[102].noOutstandingReqsAtEndOfSim_A	0	0	619	619	0	0
tb.dut.tlul_assert_device.gen_assert_final[103].noOutstandingReqsAtEndOfSim_A	0	0	619	619	0	0
tb.dut.tlul_assert_device.gen_assert_final[104].noOutstandingReqsAtEndOfSim_A	0	0	619	619	0	0
tb.dut.tlul_assert_device.gen_assert_final[105].noOutstandingReqsAtEndOfSim_A	0	0	619	619	0	0
tb.dut.tlul_assert_device.gen_assert_final[106].noOutstandingReqsAtEndOfSim_A	0	0	619	619	0	0
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tb.dut.tlul_assert_device.gen_assert_final[108].noOutstandingReqsAtEndOfSim_A	0	0	619	619	0	0
tb.dut.tlul_assert_device.gen_assert_final[109].noOutstandingReqsAtEndOfSim_A	0	0	619	619	0	0
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tb.dut.tlul_assert_device.gen_assert_final[110].noOutstandingReqsAtEndOfSim_A	0	0	619	619	0	0
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tb.dut.tlul_assert_device.gen_assert_final[112].noOutstandingReqsAtEndOfSim_A	0	0	619	619	0	0
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tb.dut.tlul_assert_device.gen_assert_final[90].noOutstandingReqsAtEndOfSim_A	0	0	619	619	0	0
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tb.dut.tlul_assert_device.gen_assert_final[92].noOutstandingReqsAtEndOfSim_A	0	0	619	619	0	0
tb.dut.tlul_assert_device.gen_assert_final[93].noOutstandingReqsAtEndOfSim_A	0	0	619	619	0	0
tb.dut.tlul_assert_device.gen_assert_final[94].noOutstandingReqsAtEndOfSim_A	0	0	619	619	0	0
tb.dut.tlul_assert_device.gen_assert_final[95].noOutstandingReqsAtEndOfSim_A	0	0	619	619	0	0
tb.dut.tlul_assert_device.gen_assert_final[96].noOutstandingReqsAtEndOfSim_A	0	0	619	619	0	0
tb.dut.tlul_assert_device.gen_assert_final[97].noOutstandingReqsAtEndOfSim_A	0	0	619	619	0	0
tb.dut.tlul_assert_device.gen_assert_final[98].noOutstandingReqsAtEndOfSim_A	0	0	619	619	0	0
tb.dut.tlul_assert_device.gen_assert_final[99].noOutstandingReqsAtEndOfSim_A	0	0	619	619	0	0
tb.dut.tlul_assert_device.gen_assert_final[9].noOutstandingReqsAtEndOfSim_A	0	0	619	619	0	0
tb.dut.tlul_assert_device.gen_device.aDataKnown_M	0	0	12302118	525382	0	0
tb.dut.tlul_assert_device.gen_device.addrSizeAlignedErr_A	0	0	12301499	4647	0	0
tb.dut.tlul_assert_device.gen_device.contigMask_M	0	0	12302118	905018	0	0
tb.dut.tlul_assert_device.gen_device.dDataKnown_A	0	0	12302118	1035797	0	0
tb.dut.tlul_assert_device.gen_device.legalAOpcodeErr_A	0	0	12301499	5191	0	0
tb.dut.tlul_assert_device.gen_device.legalAParam_M	0	0	12302118	1208342	0	0
tb.dut.tlul_assert_device.gen_device.legalDParam_A	0	0	12302118	1974389	0	0
tb.dut.tlul_assert_device.gen_device.pendingReqPerSrc_M	0	0	12302118	1208342	0	0
tb.dut.tlul_assert_device.gen_device.respMustHaveReq_A	0	0	12302118	1974389	0	0
tb.dut.tlul_assert_device.gen_device.respOpcode_A	0	0	12302118	1974389	0	0
tb.dut.tlul_assert_device.gen_device.respSzEqReqSz_A	0	0	12302118	1974389	0	0
tb.dut.tlul_assert_device.gen_device.sizeGTEMaskErr_A	0	0	12301499	2775	0	0
tb.dut.tlul_assert_device.gen_device.sizeMatchesMaskErr_A	0	0	12301499	2255	0	0
tb.dut.tlul_assert_device.p_dbw.TlDbw_A	0	0	619	619	0	0
tb.dut.u_alert_info.CntStoreSlot_A	0	0	504	504	0	0
tb.dut.u_alert_info.CntWidth_A	0	0	504	504	0	0
tb.dut.u_cpu_info.CntStoreSlot_A	0	0	504	504	0	0
tb.dut.u_cpu_info.CntWidth_A	0	0	504	504	0	0
tb.dut.u_ctrl_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	504	504	0	0
tb.dut.u_ctrl_scanmode_sync.OutputsKnown_A	0	0	13138146	8026702	0	0
tb.dut.u_ctrl_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	13138146	8026702	0	0
tb.dut.u_d0_i2c0.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0	0	0	23046	22542	0	0
tb.dut.u_d0_i2c0.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1	0	0	3081	2577	0	0
tb.dut.u_d0_i2c0.u_prim_mubi4_sender.OutputsKnown_A	0	0	13138146	6707186	0	0
tb.dut.u_d0_i2c0.u_rst_mux.gen_generic.u_impl_generic.selKnown0	0	0	24126	23622	0	0
tb.dut.u_d0_i2c0.u_rst_mux.gen_generic.u_impl_generic.selKnown1	0	0	3081	2577	0	0
tb.dut.u_d0_i2c0.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	504	504	0	0
tb.dut.u_d0_i2c0.u_scanmode_sync.OutputsKnown_A	0	0	11539416	6806657	0	0
tb.dut.u_d0_i2c0.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	11539416	6806657	0	0
tb.dut.u_d0_i2c1.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0	0	0	23046	22542	0	0
tb.dut.u_d0_i2c1.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1	0	0	3081	2577	0	0
tb.dut.u_d0_i2c1.u_prim_mubi4_sender.OutputsKnown_A	0	0	13138146	6707814	0	0
tb.dut.u_d0_i2c1.u_rst_mux.gen_generic.u_impl_generic.selKnown0	0	0	24178	23674	0	0
tb.dut.u_d0_i2c1.u_rst_mux.gen_generic.u_impl_generic.selKnown1	0	0	3081	2577	0	0
tb.dut.u_d0_i2c1.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	504	504	0	0
tb.dut.u_d0_i2c1.u_scanmode_sync.OutputsKnown_A	0	0	11539416	6806657	0	0
tb.dut.u_d0_i2c1.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	11539416	6806657	0	0
tb.dut.u_d0_i2c2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0	0	0	23046	22542	0	0
tb.dut.u_d0_i2c2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1	0	0	3081	2577	0	0
tb.dut.u_d0_i2c2.u_prim_mubi4_sender.OutputsKnown_A	0	0	13138146	6714925	0	0
tb.dut.u_d0_i2c2.u_rst_mux.gen_generic.u_impl_generic.selKnown0	0	0	24213	23709	0	0
tb.dut.u_d0_i2c2.u_rst_mux.gen_generic.u_impl_generic.selKnown1	0	0	3081	2577	0	0
tb.dut.u_d0_i2c2.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	504	504	0	0
tb.dut.u_d0_i2c2.u_scanmode_sync.OutputsKnown_A	0	0	11539416	6806657	0	0
tb.dut.u_d0_i2c2.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	11539416	6806657	0	0
tb.dut.u_d0_lc.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0	0	0	23046	22542	0	0
tb.dut.u_d0_lc.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1	0	0	3081	2577	0	0
tb.dut.u_d0_lc.u_prim_mubi4_sender.OutputsKnown_A	0	0	54743812	28651110	0	0
tb.dut.u_d0_lc.u_rst_mux.gen_generic.u_impl_generic.selKnown0	0	0	22996	22492	0	0
tb.dut.u_d0_lc.u_rst_mux.gen_generic.u_impl_generic.selKnown1	0	0	3081	2577	0	0
tb.dut.u_d0_lc.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	504	504	0	0
tb.dut.u_d0_lc.u_scanmode_sync.OutputsKnown_A	0	0	11539416	6806657	0	0
tb.dut.u_d0_lc.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	11539416	6806657	0	0
tb.dut.u_d0_lc_io.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0	0	0	23046	22542	0	0
tb.dut.u_d0_lc_io.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1	0	0	3081	2577	0	0
tb.dut.u_d0_lc_io.u_prim_mubi4_sender.OutputsKnown_A	0	0	52552100	27503392	0	0
tb.dut.u_d0_lc_io.u_rst_mux.gen_generic.u_impl_generic.selKnown0	0	0	22996	22492	0	0
tb.dut.u_d0_lc_io.u_rst_mux.gen_generic.u_impl_generic.selKnown1	0	0	3081	2577	0	0
tb.dut.u_d0_lc_io.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	504	504	0	0
tb.dut.u_d0_lc_io.u_scanmode_sync.OutputsKnown_A	0	0	11539416	6806657	0	0
tb.dut.u_d0_lc_io.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	11539416	6806657	0	0
tb.dut.u_d0_lc_io_div2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0	0	0	23046	22542	0	0
tb.dut.u_d0_lc_io_div2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1	0	0	3081	2577	0	0
tb.dut.u_d0_lc_io_div2.u_prim_mubi4_sender.OutputsKnown_A	0	0	26276811	13741117	0	0
tb.dut.u_d0_lc_io_div2.u_rst_mux.gen_generic.u_impl_generic.selKnown0	0	0	22996	22492	0	0
tb.dut.u_d0_lc_io_div2.u_rst_mux.gen_generic.u_impl_generic.selKnown1	0	0	3081	2577	0	0
tb.dut.u_d0_lc_io_div2.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	504	504	0	0
tb.dut.u_d0_lc_io_div2.u_scanmode_sync.OutputsKnown_A	0	0	11539416	6806657	0	0
tb.dut.u_d0_lc_io_div2.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	11539416	6806657	0	0
tb.dut.u_d0_lc_io_div4.u_prim_mubi4_sender.OutputsKnown_A	0	0	13138146	6841126	0	0
tb.dut.u_d0_lc_io_div4.u_rst_mux.gen_generic.u_impl_generic.selKnown0	0	0	22996	22492	0	0
tb.dut.u_d0_lc_io_div4.u_rst_mux.gen_generic.u_impl_generic.selKnown1	0	0	3081	2577	0	0
tb.dut.u_d0_lc_io_div4.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	504	504	0	0
tb.dut.u_d0_lc_io_div4.u_scanmode_sync.OutputsKnown_A	0	0	11539416	6806657	0	0
tb.dut.u_d0_lc_io_div4.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	11539416	6806657	0	0
tb.dut.u_d0_lc_io_div4_shadowed.u_prim_mubi4_sender.OutputsKnown_A	0	0	13138146	6841126	0	0
tb.dut.u_d0_lc_io_div4_shadowed.u_rst_mux.gen_generic.u_impl_generic.selKnown0	0	0	22996	22492	0	0
tb.dut.u_d0_lc_io_div4_shadowed.u_rst_mux.gen_generic.u_impl_generic.selKnown1	0	0	3081	2577	0	0
tb.dut.u_d0_lc_io_div4_shadowed.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	504	504	0	0
tb.dut.u_d0_lc_io_div4_shadowed.u_scanmode_sync.OutputsKnown_A	0	0	11539416	6806657	0	0
tb.dut.u_d0_lc_io_div4_shadowed.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	11539416	6806657	0	0
tb.dut.u_d0_lc_shadowed.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0	0	0	23046	22542	0	0
tb.dut.u_d0_lc_shadowed.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1	0	0	3081	2577	0	0
tb.dut.u_d0_lc_shadowed.u_prim_mubi4_sender.OutputsKnown_A	0	0	54743812	28652526	0	0
tb.dut.u_d0_lc_shadowed.u_rst_mux.gen_generic.u_impl_generic.selKnown0	0	0	22996	22492	0	0
tb.dut.u_d0_lc_shadowed.u_rst_mux.gen_generic.u_impl_generic.selKnown1	0	0	3081	2577	0	0
tb.dut.u_d0_lc_shadowed.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	504	504	0	0
tb.dut.u_d0_lc_shadowed.u_scanmode_sync.OutputsKnown_A	0	0	11539416	6806657	0	0
tb.dut.u_d0_lc_shadowed.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	11539416	6806657	0	0
tb.dut.u_d0_lc_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0	0	0	23046	22542	0	0
tb.dut.u_d0_lc_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1	0	0	3081	2577	0	0
tb.dut.u_d0_lc_usb.u_prim_mubi4_sender.OutputsKnown_A	0	0	26276817	13740850	0	0
tb.dut.u_d0_lc_usb.u_rst_mux.gen_generic.u_impl_generic.selKnown0	0	0	22996	22492	0	0
tb.dut.u_d0_lc_usb.u_rst_mux.gen_generic.u_impl_generic.selKnown1	0	0	3081	2577	0	0
tb.dut.u_d0_lc_usb.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	504	504	0	0
tb.dut.u_d0_lc_usb.u_scanmode_sync.OutputsKnown_A	0	0	11539416	6806657	0	0
tb.dut.u_d0_lc_usb.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	11539416	6806657	0	0
tb.dut.u_d0_spi_device.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0	0	0	23046	22542	0	0
tb.dut.u_d0_spi_device.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1	0	0	3081	2577	0	0
tb.dut.u_d0_spi_device.u_prim_mubi4_sender.OutputsKnown_A	0	0	13138146	6706451	0	0
tb.dut.u_d0_spi_device.u_rst_mux.gen_generic.u_impl_generic.selKnown0	0	0	23872	23368	0	0
tb.dut.u_d0_spi_device.u_rst_mux.gen_generic.u_impl_generic.selKnown1	0	0	3081	2577	0	0
tb.dut.u_d0_spi_device.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	504	504	0	0
tb.dut.u_d0_spi_device.u_scanmode_sync.OutputsKnown_A	0	0	11539416	6806657	0	0
tb.dut.u_d0_spi_device.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	11539416	6806657	0	0
tb.dut.u_d0_spi_host0.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0	0	0	23046	22542	0	0
tb.dut.u_d0_spi_host0.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1	0	0	3081	2577	0	0
tb.dut.u_d0_spi_host0.u_prim_mubi4_sender.OutputsKnown_A	0	0	52552100	26954172	0	0
tb.dut.u_d0_spi_host0.u_rst_mux.gen_generic.u_impl_generic.selKnown0	0	0	23922	23418	0	0
tb.dut.u_d0_spi_host0.u_rst_mux.gen_generic.u_impl_generic.selKnown1	0	0	3081	2577	0	0
tb.dut.u_d0_spi_host0.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	504	504	0	0
tb.dut.u_d0_spi_host0.u_scanmode_sync.OutputsKnown_A	0	0	11539416	6806657	0	0
tb.dut.u_d0_spi_host0.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	11539416	6806657	0	0
tb.dut.u_d0_spi_host1.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0	0	0	23046	22542	0	0
tb.dut.u_d0_spi_host1.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1	0	0	3081	2577	0	0
tb.dut.u_d0_spi_host1.u_prim_mubi4_sender.OutputsKnown_A	0	0	26276811	13467055	0	0
tb.dut.u_d0_spi_host1.u_rst_mux.gen_generic.u_impl_generic.selKnown0	0	0	23986	23482	0	0
tb.dut.u_d0_spi_host1.u_rst_mux.gen_generic.u_impl_generic.selKnown1	0	0	3081	2577	0	0
tb.dut.u_d0_spi_host1.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	504	504	0	0
tb.dut.u_d0_spi_host1.u_scanmode_sync.OutputsKnown_A	0	0	11539416	6806657	0	0
tb.dut.u_d0_spi_host1.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	11539416	6806657	0	0
tb.dut.u_d0_sys.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0	0	0	23046	22542	0	0
tb.dut.u_d0_sys.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1	0	0	3081	2577	0	0
tb.dut.u_d0_sys.u_prim_mubi4_sender.OutputsKnown_A	0	0	54743812	28325055	0	0
tb.dut.u_d0_sys.u_rst_mux.gen_generic.u_impl_generic.selKnown0	0	0	22996	22492	0	0
tb.dut.u_d0_sys.u_rst_mux.gen_generic.u_impl_generic.selKnown1	0	0	3081	2577	0	0
tb.dut.u_d0_sys.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	504	504	0	0
tb.dut.u_d0_sys.u_scanmode_sync.OutputsKnown_A	0	0	11539416	6806657	0	0
tb.dut.u_d0_sys.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	11539416	6806657	0	0
tb.dut.u_d0_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0	0	0	23046	22542	0	0
tb.dut.u_d0_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1	0	0	3081	2577	0	0
tb.dut.u_d0_usb.u_prim_mubi4_sender.OutputsKnown_A	0	0	26276817	13477730	0	0
tb.dut.u_d0_usb.u_rst_mux.gen_generic.u_impl_generic.selKnown0	0	0	24005	23501	0	0
tb.dut.u_d0_usb.u_rst_mux.gen_generic.u_impl_generic.selKnown1	0	0	3081	2577	0	0
tb.dut.u_d0_usb.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	504	504	0	0
tb.dut.u_d0_usb.u_scanmode_sync.OutputsKnown_A	0	0	11539416	6806657	0	0
tb.dut.u_d0_usb.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	11539416	6806657	0	0
tb.dut.u_d0_usb_aon.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0	0	0	22928	22424	0	0
tb.dut.u_d0_usb_aon.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1	0	0	3081	2577	0	0
tb.dut.u_d0_usb_aon.u_prim_mubi4_sender.OutputsKnown_A	0	0	1660647	833581	0	0
tb.dut.u_d0_usb_aon.u_rst_mux.gen_generic.u_impl_generic.selKnown0	0	0	24065	23561	0	0
tb.dut.u_d0_usb_aon.u_rst_mux.gen_generic.u_impl_generic.selKnown1	0	0	3081	2577	0	0
tb.dut.u_d0_usb_aon.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	504	504	0	0
tb.dut.u_d0_usb_aon.u_scanmode_sync.OutputsKnown_A	0	0	11539416	6806657	0	0
tb.dut.u_d0_usb_aon.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	11539416	6806657	0	0
tb.dut.u_daon_lc.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0	0	0	23046	22542	0	0
tb.dut.u_daon_lc.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1	0	0	3081	2577	0	0
tb.dut.u_daon_lc.u_prim_mubi4_sender.OutputsKnown_A	0	0	54743812	29386755	0	0
tb.dut.u_daon_lc.u_rst_mux.gen_generic.u_impl_generic.selKnown0	0	0	22996	22492	0	0
tb.dut.u_daon_lc.u_rst_mux.gen_generic.u_impl_generic.selKnown1	0	0	3081	2577	0	0
tb.dut.u_daon_lc.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	504	504	0	0
tb.dut.u_daon_lc.u_scanmode_sync.OutputsKnown_A	0	0	11539416	6806657	0	0
tb.dut.u_daon_lc.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	11539416	6806657	0	0
tb.dut.u_daon_lc_aon.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0	0	0	22928	22424	0	0
tb.dut.u_daon_lc_aon.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1	0	0	3081	2577	0	0
tb.dut.u_daon_lc_aon.u_prim_mubi4_sender.OutputsKnown_A	0	0	1660647	872998	0	0
tb.dut.u_daon_lc_aon.u_rst_mux.gen_generic.u_impl_generic.selKnown0	0	0	22996	22492	0	0
tb.dut.u_daon_lc_aon.u_rst_mux.gen_generic.u_impl_generic.selKnown1	0	0	3081	2577	0	0
tb.dut.u_daon_lc_aon.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	504	504	0	0
tb.dut.u_daon_lc_aon.u_scanmode_sync.OutputsKnown_A	0	0	11539416	6806657	0	0
tb.dut.u_daon_lc_aon.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	11539416	6806657	0	0
tb.dut.u_daon_lc_io.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0	0	0	23046	22542	0	0
tb.dut.u_daon_lc_io.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1	0	0	3081	2577	0	0
tb.dut.u_daon_lc_io.u_prim_mubi4_sender.OutputsKnown_A	0	0	52552100	28211119	0	0
tb.dut.u_daon_lc_io.u_rst_mux.gen_generic.u_impl_generic.selKnown0	0	0	22996	22492	0	0
tb.dut.u_daon_lc_io.u_rst_mux.gen_generic.u_impl_generic.selKnown1	0	0	3081	2577	0	0
tb.dut.u_daon_lc_io.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	504	504	0	0
tb.dut.u_daon_lc_io.u_scanmode_sync.OutputsKnown_A	0	0	11539416	6806657	0	0
tb.dut.u_daon_lc_io.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	11539416	6806657	0	0
tb.dut.u_daon_lc_io_div2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0	0	0	23046	22542	0	0
tb.dut.u_daon_lc_io_div2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1	0	0	3081	2577	0	0
tb.dut.u_daon_lc_io_div2.u_prim_mubi4_sender.OutputsKnown_A	0	0	26276811	14094796	0	0
tb.dut.u_daon_lc_io_div2.u_rst_mux.gen_generic.u_impl_generic.selKnown0	0	0	22996	22492	0	0
tb.dut.u_daon_lc_io_div2.u_rst_mux.gen_generic.u_impl_generic.selKnown1	0	0	3081	2577	0	0
tb.dut.u_daon_lc_io_div2.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	504	504	0	0
tb.dut.u_daon_lc_io_div2.u_scanmode_sync.OutputsKnown_A	0	0	11539416	6806657	0	0
tb.dut.u_daon_lc_io_div2.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	11539416	6806657	0	0
tb.dut.u_daon_lc_io_div4.u_prim_mubi4_sender.OutputsKnown_A	0	0	13138146	7018082	0	0
tb.dut.u_daon_lc_io_div4.u_rst_mux.gen_generic.u_impl_generic.selKnown0	0	0	22996	22492	0	0
tb.dut.u_daon_lc_io_div4.u_rst_mux.gen_generic.u_impl_generic.selKnown1	0	0	3081	2577	0	0
tb.dut.u_daon_lc_io_div4.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	504	504	0	0
tb.dut.u_daon_lc_io_div4.u_scanmode_sync.OutputsKnown_A	0	0	11539416	6806657	0	0
tb.dut.u_daon_lc_io_div4.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	11539416	6806657	0	0
tb.dut.u_daon_lc_io_div4_shadowed.u_prim_mubi4_sender.OutputsKnown_A	0	0	13138146	7018082	0	0
tb.dut.u_daon_lc_io_div4_shadowed.u_rst_mux.gen_generic.u_impl_generic.selKnown0	0	0	22996	22492	0	0
tb.dut.u_daon_lc_io_div4_shadowed.u_rst_mux.gen_generic.u_impl_generic.selKnown1	0	0	3081	2577	0	0
tb.dut.u_daon_lc_io_div4_shadowed.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	504	504	0	0
tb.dut.u_daon_lc_io_div4_shadowed.u_scanmode_sync.OutputsKnown_A	0	0	11539416	6806657	0	0
tb.dut.u_daon_lc_io_div4_shadowed.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	11539416	6806657	0	0
tb.dut.u_daon_lc_shadowed.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0	0	0	23046	22542	0	0
tb.dut.u_daon_lc_shadowed.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1	0	0	3081	2577	0	0
tb.dut.u_daon_lc_shadowed.u_prim_mubi4_sender.OutputsKnown_A	0	0	54743812	29386600	0	0
tb.dut.u_daon_lc_shadowed.u_rst_mux.gen_generic.u_impl_generic.selKnown0	0	0	22996	22492	0	0
tb.dut.u_daon_lc_shadowed.u_rst_mux.gen_generic.u_impl_generic.selKnown1	0	0	3081	2577	0	0
tb.dut.u_daon_lc_shadowed.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	504	504	0	0
tb.dut.u_daon_lc_shadowed.u_scanmode_sync.OutputsKnown_A	0	0	11539416	6806657	0	0
tb.dut.u_daon_lc_shadowed.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	11539416	6806657	0	0
tb.dut.u_daon_lc_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0	0	0	23046	22542	0	0
tb.dut.u_daon_lc_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1	0	0	3081	2577	0	0
tb.dut.u_daon_lc_usb.u_prim_mubi4_sender.OutputsKnown_A	0	0	26276817	14094783	0	0
tb.dut.u_daon_lc_usb.u_rst_mux.gen_generic.u_impl_generic.selKnown0	0	0	22996	22492	0	0
tb.dut.u_daon_lc_usb.u_rst_mux.gen_generic.u_impl_generic.selKnown1	0	0	3081	2577	0	0
tb.dut.u_daon_lc_usb.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	504	504	0	0
tb.dut.u_daon_lc_usb.u_scanmode_sync.OutputsKnown_A	0	0	11539416	6806657	0	0
tb.dut.u_daon_lc_usb.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	11539416	6806657	0	0
tb.dut.u_daon_por.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0	0	0	23046	22542	0	0
tb.dut.u_daon_por.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1	0	0	3081	2577	0	0
tb.dut.u_daon_por.u_prim_mubi4_sender.OutputsKnown_A	0	0	54743812	33468125	0	0
tb.dut.u_daon_por.u_rst_mux.gen_generic.u_impl_generic.selKnown0	0	0	8841	8337	0	0
tb.dut.u_daon_por.u_rst_mux.gen_generic.u_impl_generic.selKnown1	0	0	3081	2577	0	0
tb.dut.u_daon_por.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	504	504	0	0
tb.dut.u_daon_por.u_scanmode_sync.OutputsKnown_A	0	0	11539416	6806657	0	0
tb.dut.u_daon_por.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	11539416	6806657	0	0
tb.dut.u_daon_por_io.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0	0	0	23046	22542	0	0
tb.dut.u_daon_por_io.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1	0	0	3081	2577	0	0
tb.dut.u_daon_por_io.u_prim_mubi4_sender.OutputsKnown_A	0	0	52552100	32128255	0	0
tb.dut.u_daon_por_io.u_rst_mux.gen_generic.u_impl_generic.selKnown0	0	0	8841	8337	0	0
tb.dut.u_daon_por_io.u_rst_mux.gen_generic.u_impl_generic.selKnown1	0	0	3081	2577	0	0
tb.dut.u_daon_por_io.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	504	504	0	0
tb.dut.u_daon_por_io.u_scanmode_sync.OutputsKnown_A	0	0	11539416	6806657	0	0
tb.dut.u_daon_por_io.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	11539416	6806657	0	0
tb.dut.u_daon_por_io_div2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0	0	0	23046	22542	0	0
tb.dut.u_daon_por_io_div2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1	0	0	3081	2577	0	0
tb.dut.u_daon_por_io_div2.u_prim_mubi4_sender.OutputsKnown_A	0	0	26276811	16060365	0	0
tb.dut.u_daon_por_io_div2.u_rst_mux.gen_generic.u_impl_generic.selKnown0	0	0	8841	8337	0	0
tb.dut.u_daon_por_io_div2.u_rst_mux.gen_generic.u_impl_generic.selKnown1	0	0	3081	2577	0	0
tb.dut.u_daon_por_io_div2.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	504	504	0	0
tb.dut.u_daon_por_io_div2.u_scanmode_sync.OutputsKnown_A	0	0	11539416	6806657	0	0
tb.dut.u_daon_por_io_div2.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	11539416	6806657	0	0
tb.dut.u_daon_por_io_div4.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0	0	0	23046	22542	0	0
tb.dut.u_daon_por_io_div4.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1	0	0	3081	2577	0	0
tb.dut.u_daon_por_io_div4.u_prim_mubi4_sender.OutputsKnown_A	0	0	13138146	8026702	0	0
tb.dut.u_daon_por_io_div4.u_rst_mux.gen_generic.u_impl_generic.selKnown0	0	0	8841	8337	0	0
tb.dut.u_daon_por_io_div4.u_rst_mux.gen_generic.u_impl_generic.selKnown1	0	0	3081	2577	0	0
tb.dut.u_daon_por_io_div4.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	504	504	0	0
tb.dut.u_daon_por_io_div4.u_scanmode_sync.OutputsKnown_A	0	0	11539416	6806657	0	0
tb.dut.u_daon_por_io_div4.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	11539416	6806657	0	0
tb.dut.u_daon_por_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0	0	0	23046	22542	0	0
tb.dut.u_daon_por_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1	0	0	3081	2577	0	0
tb.dut.u_daon_por_usb.u_prim_mubi4_sender.OutputsKnown_A	0	0	26276817	16060300	0	0
tb.dut.u_daon_por_usb.u_rst_mux.gen_generic.u_impl_generic.selKnown0	0	0	8841	8337	0	0
tb.dut.u_daon_por_usb.u_rst_mux.gen_generic.u_impl_generic.selKnown1	0	0	3081	2577	0	0
tb.dut.u_daon_por_usb.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	504	504	0	0
tb.dut.u_daon_por_usb.u_scanmode_sync.OutputsKnown_A	0	0	11539416	6806657	0	0
tb.dut.u_daon_por_usb.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	11539416	6806657	0	0
tb.dut.u_daon_sys_io_div4.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0	0	0	23046	22542	0	0
tb.dut.u_daon_sys_io_div4.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1	0	0	3081	2577	0	0
tb.dut.u_daon_sys_io_div4.u_prim_mubi4_sender.OutputsKnown_A	0	0	13138146	6939957	0	0
tb.dut.u_daon_sys_io_div4.u_rst_mux.gen_generic.u_impl_generic.selKnown0	0	0	22996	22492	0	0
tb.dut.u_daon_sys_io_div4.u_rst_mux.gen_generic.u_impl_generic.selKnown1	0	0	3081	2577	0	0
tb.dut.u_daon_sys_io_div4.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	504	504	0	0
tb.dut.u_daon_sys_io_div4.u_scanmode_sync.OutputsKnown_A	0	0	11539416	6806657	0	0
tb.dut.u_daon_sys_io_div4.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	11539416	6806657	0	0
tb.dut.u_lc_src.gen_rst_pd_n[0].u_rst_pd_mux.gen_generic.u_impl_generic.selKnown0	0	0	22996	22492	0	0
tb.dut.u_lc_src.gen_rst_pd_n[0].u_rst_pd_mux.gen_generic.u_impl_generic.selKnown1	0	0	3081	2577	0	0
tb.dut.u_lc_src.u_rst_aon_mux.gen_generic.u_impl_generic.selKnown0	0	0	22996	22492	0	0
tb.dut.u_lc_src.u_rst_aon_mux.gen_generic.u_impl_generic.selKnown1	0	0	3081	2577	0	0
tb.dut.u_reg.en2addrHit	0	0	12301499	1062311	0	0
tb.dut.u_reg.reAfterRv	0	0	12301499	1062158	0	0
tb.dut.u_reg.rePulse	0	0	12301499	570957	0	0
tb.dut.u_reg.u_chk.PayLoadWidthCheck	0	0	619	619	0	0
tb.dut.u_reg.u_reg_if.AllowedLatency_A	0	0	619	619	0	0
tb.dut.u_reg.u_reg_if.MatchedWidthAssert	0	0	619	619	0	0
tb.dut.u_reg.u_reg_if.u_err.dataWidthOnly32_A	0	0	619	619	0	0
tb.dut.u_reg.u_reg_if.u_rsp_intg_gen.DataWidthCheck_A	0	0	619	619	0	0
tb.dut.u_reg.u_reg_if.u_rsp_intg_gen.PayLoadWidthCheck	0	0	619	619	0	0
tb.dut.u_reg.u_rsp_intg_gen.DataWidthCheck_A	0	0	619	619	0	0
tb.dut.u_reg.u_rsp_intg_gen.PayLoadWidthCheck	0	0	619	619	0	0
tb.dut.u_reg.wePulse	0	0	12301499	491201	0	0
tb.dut.u_sys_src.gen_rst_pd_n[0].u_rst_pd_mux.gen_generic.u_impl_generic.selKnown0	0	0	22996	22492	0	0
tb.dut.u_sys_src.gen_rst_pd_n[0].u_rst_pd_mux.gen_generic.u_impl_generic.selKnown1	0	0	3081	2577	0	0
tb.dut.u_sys_src.u_rst_aon_mux.gen_generic.u_impl_generic.selKnown0	0	0	22996	22492	0	0
tb.dut.u_sys_src.u_rst_aon_mux.gen_generic.u_impl_generic.selKnown1	0	0	3081	2577	0	0

---

Detail Report for Cover Sequences

Cover Sequences All Matches:

COVER SEQUENCES	CATEGORY	SEVERITY	ATTEMPTS	ALL MATCHES	FIRST MATCHES	INCOMPLETE	SRC
tb.dut.tlul_assert_device.gen_device_cov.aValidNotAccepted_C	0	0	12302118	6243	6243	0
tb.dut.tlul_assert_device.gen_device_cov.a_addressChangedNotAccepted_C	0	0	12302118	3005	3005	1
tb.dut.tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C	0	0	12302118	3019	3019	1
tb.dut.tlul_assert_device.gen_device_cov.a_maskChangedNotAccepted_C	0	0	12302118	2116	2116	1
tb.dut.tlul_assert_device.gen_device_cov.a_opcodeChangedNotAccepted_C	0	0	12302118	143	143	1
tb.dut.tlul_assert_device.gen_device_cov.a_sizeChangedNotAccepted_C	0	0	12302118	1683	1683	1
tb.dut.tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C	0	0	12302118	1257	1257	1
tb.dut.tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C	0	0	12302118	2868	2868	0
tb.dut.tlul_assert_device.gen_device_cov.b2bReq_C	0	0	12302118	58944	58944	0
tb.dut.tlul_assert_device.gen_device_cov.b2bSameSource_C	0	0	12302118	542448	542448	454

Cover Sequences First Matches:

COVER SEQUENCES	CATEGORY	SEVERITY	ATTEMPTS	ALL MATCHES	FIRST MATCHES	INCOMPLETE	SRC
tb.dut.tlul_assert_device.gen_device_cov.aValidNotAccepted_C	0	0	12302118	6243	6243	0
tb.dut.tlul_assert_device.gen_device_cov.a_addressChangedNotAccepted_C	0	0	12302118	3005	3005	1
tb.dut.tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C	0	0	12302118	3019	3019	1
tb.dut.tlul_assert_device.gen_device_cov.a_maskChangedNotAccepted_C	0	0	12302118	2116	2116	1
tb.dut.tlul_assert_device.gen_device_cov.a_opcodeChangedNotAccepted_C	0	0	12302118	143	143	1
tb.dut.tlul_assert_device.gen_device_cov.a_sizeChangedNotAccepted_C	0	0	12302118	1683	1683	1
tb.dut.tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C	0	0	12302118	1257	1257	1
tb.dut.tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C	0	0	12302118	2868	2868	0
tb.dut.tlul_assert_device.gen_device_cov.b2bReq_C	0	0	12302118	58944	58944	0
tb.dut.tlul_assert_device.gen_device_cov.b2bSameSource_C	0	0	12302118	542448	542448	454