Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.43 99.40 99.24 99.87 99.83 99.46 98.77


Total test records in report: 619
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html
T541 /workspace/coverage/default/11.rstmgr_leaf_rst_shadow_attack.1225635214 Jun 25 05:38:22 PM PDT 24 Jun 25 05:38:25 PM PDT 24 244453617 ps
T542 /workspace/coverage/default/32.rstmgr_smoke.3041693831 Jun 25 05:38:55 PM PDT 24 Jun 25 05:39:00 PM PDT 24 256748768 ps
T543 /workspace/coverage/default/5.rstmgr_leaf_rst_shadow_attack.730458108 Jun 25 05:38:05 PM PDT 24 Jun 25 05:38:07 PM PDT 24 248237553 ps
T544 /workspace/coverage/default/20.rstmgr_leaf_rst_cnsty.3898458072 Jun 25 05:38:29 PM PDT 24 Jun 25 05:38:37 PM PDT 24 1233288545 ps
T54 /workspace/coverage/cover_reg_top/8.rstmgr_tl_intg_err.528346977 Jun 25 05:34:16 PM PDT 24 Jun 25 05:34:20 PM PDT 24 916236680 ps
T55 /workspace/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.2498400311 Jun 25 05:34:23 PM PDT 24 Jun 25 05:34:26 PM PDT 24 231202055 ps
T57 /workspace/coverage/cover_reg_top/0.rstmgr_tl_errors.2453198078 Jun 25 05:34:12 PM PDT 24 Jun 25 05:34:16 PM PDT 24 426541601 ps
T56 /workspace/coverage/cover_reg_top/12.rstmgr_tl_intg_err.74681631 Jun 25 05:34:25 PM PDT 24 Jun 25 05:34:30 PM PDT 24 788369656 ps
T76 /workspace/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.2490668797 Jun 25 05:34:15 PM PDT 24 Jun 25 05:34:17 PM PDT 24 105731159 ps
T109 /workspace/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.2289361326 Jun 25 05:34:32 PM PDT 24 Jun 25 05:34:35 PM PDT 24 207242362 ps
T64 /workspace/coverage/cover_reg_top/17.rstmgr_tl_intg_err.2797104016 Jun 25 05:34:29 PM PDT 24 Jun 25 05:34:32 PM PDT 24 445364740 ps
T104 /workspace/coverage/cover_reg_top/0.rstmgr_csr_aliasing.895079462 Jun 25 05:34:13 PM PDT 24 Jun 25 05:34:16 PM PDT 24 444953864 ps
T58 /workspace/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.3065072020 Jun 25 05:34:34 PM PDT 24 Jun 25 05:34:36 PM PDT 24 169365321 ps
T110 /workspace/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.2132754457 Jun 25 05:34:24 PM PDT 24 Jun 25 05:34:27 PM PDT 24 94789205 ps
T59 /workspace/coverage/cover_reg_top/5.rstmgr_tl_errors.663945515 Jun 25 05:34:18 PM PDT 24 Jun 25 05:34:22 PM PDT 24 250235752 ps
T545 /workspace/coverage/cover_reg_top/3.rstmgr_csr_aliasing.406994121 Jun 25 05:34:19 PM PDT 24 Jun 25 05:34:22 PM PDT 24 251026787 ps
T546 /workspace/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.610885279 Jun 25 05:34:16 PM PDT 24 Jun 25 05:34:22 PM PDT 24 478823111 ps
T75 /workspace/coverage/cover_reg_top/6.rstmgr_tl_errors.3795302046 Jun 25 05:34:13 PM PDT 24 Jun 25 05:34:17 PM PDT 24 395789687 ps
T111 /workspace/coverage/cover_reg_top/1.rstmgr_csr_rw.3895127297 Jun 25 05:34:19 PM PDT 24 Jun 25 05:34:22 PM PDT 24 67665084 ps
T547 /workspace/coverage/cover_reg_top/4.rstmgr_csr_rw.3998690654 Jun 25 05:34:17 PM PDT 24 Jun 25 05:34:19 PM PDT 24 77620349 ps
T79 /workspace/coverage/cover_reg_top/13.rstmgr_tl_intg_err.3184180457 Jun 25 05:34:25 PM PDT 24 Jun 25 05:34:29 PM PDT 24 475865247 ps
T548 /workspace/coverage/cover_reg_top/1.rstmgr_csr_aliasing.4020472078 Jun 25 05:34:15 PM PDT 24 Jun 25 05:34:18 PM PDT 24 207946274 ps
T549 /workspace/coverage/cover_reg_top/11.rstmgr_csr_rw.2220991778 Jun 25 05:34:23 PM PDT 24 Jun 25 05:34:25 PM PDT 24 67778617 ps
T80 /workspace/coverage/cover_reg_top/6.rstmgr_tl_intg_err.2832544930 Jun 25 05:34:22 PM PDT 24 Jun 25 05:34:24 PM PDT 24 502617237 ps
T550 /workspace/coverage/cover_reg_top/3.rstmgr_csr_rw.3368230786 Jun 25 05:34:17 PM PDT 24 Jun 25 05:34:18 PM PDT 24 75399515 ps
T86 /workspace/coverage/cover_reg_top/2.rstmgr_tl_errors.3512251421 Jun 25 05:34:15 PM PDT 24 Jun 25 05:34:19 PM PDT 24 433783372 ps
T112 /workspace/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.2040164272 Jun 25 05:34:42 PM PDT 24 Jun 25 05:34:44 PM PDT 24 77079185 ps
T96 /workspace/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.1230356801 Jun 25 05:34:28 PM PDT 24 Jun 25 05:34:30 PM PDT 24 114579369 ps
T83 /workspace/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.3257649852 Jun 25 05:34:23 PM PDT 24 Jun 25 05:34:26 PM PDT 24 196613072 ps
T551 /workspace/coverage/cover_reg_top/2.rstmgr_csr_aliasing.3772075822 Jun 25 05:34:18 PM PDT 24 Jun 25 05:34:23 PM PDT 24 355333584 ps
T93 /workspace/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.908439439 Jun 25 05:34:29 PM PDT 24 Jun 25 05:34:31 PM PDT 24 116899750 ps
T113 /workspace/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.142906021 Jun 25 05:34:16 PM PDT 24 Jun 25 05:34:18 PM PDT 24 139207992 ps
T114 /workspace/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.1267864603 Jun 25 05:34:27 PM PDT 24 Jun 25 05:34:29 PM PDT 24 128816649 ps
T552 /workspace/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.1292888236 Jun 25 05:34:13 PM PDT 24 Jun 25 05:34:19 PM PDT 24 480584439 ps
T553 /workspace/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.60076643 Jun 25 05:34:17 PM PDT 24 Jun 25 05:34:20 PM PDT 24 106240458 ps
T89 /workspace/coverage/cover_reg_top/15.rstmgr_tl_intg_err.1613026778 Jun 25 05:34:27 PM PDT 24 Jun 25 05:34:31 PM PDT 24 873945433 ps
T90 /workspace/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.1477672808 Jun 25 05:34:24 PM PDT 24 Jun 25 05:34:27 PM PDT 24 113373096 ps
T554 /workspace/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.3982710017 Jun 25 05:34:33 PM PDT 24 Jun 25 05:34:35 PM PDT 24 199414715 ps
T555 /workspace/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.2709690585 Jun 25 05:34:13 PM PDT 24 Jun 25 05:34:15 PM PDT 24 183617072 ps
T95 /workspace/coverage/cover_reg_top/11.rstmgr_tl_errors.2450755734 Jun 25 05:34:33 PM PDT 24 Jun 25 05:34:36 PM PDT 24 113623884 ps
T115 /workspace/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.2476949503 Jun 25 05:34:18 PM PDT 24 Jun 25 05:34:22 PM PDT 24 238538761 ps
T556 /workspace/coverage/cover_reg_top/4.rstmgr_csr_aliasing.3791192237 Jun 25 05:34:17 PM PDT 24 Jun 25 05:34:20 PM PDT 24 267333324 ps
T84 /workspace/coverage/cover_reg_top/9.rstmgr_tl_intg_err.933856319 Jun 25 05:34:34 PM PDT 24 Jun 25 05:34:37 PM PDT 24 422657419 ps
T557 /workspace/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.1786379364 Jun 25 05:34:25 PM PDT 24 Jun 25 05:34:28 PM PDT 24 124994765 ps
T116 /workspace/coverage/cover_reg_top/6.rstmgr_csr_rw.1554717990 Jun 25 05:34:17 PM PDT 24 Jun 25 05:34:19 PM PDT 24 66082857 ps
T558 /workspace/coverage/cover_reg_top/10.rstmgr_tl_intg_err.976454273 Jun 25 05:34:28 PM PDT 24 Jun 25 05:34:32 PM PDT 24 874028393 ps
T88 /workspace/coverage/cover_reg_top/16.rstmgr_tl_intg_err.3710325654 Jun 25 05:34:24 PM PDT 24 Jun 25 05:34:28 PM PDT 24 793169222 ps
T559 /workspace/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.2387518457 Jun 25 05:34:17 PM PDT 24 Jun 25 05:34:20 PM PDT 24 123943159 ps
T560 /workspace/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.1701970641 Jun 25 05:34:13 PM PDT 24 Jun 25 05:34:14 PM PDT 24 91569735 ps
T561 /workspace/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.509746480 Jun 25 05:34:23 PM PDT 24 Jun 25 05:34:25 PM PDT 24 83074273 ps
T562 /workspace/coverage/cover_reg_top/7.rstmgr_csr_rw.3515119255 Jun 25 05:34:15 PM PDT 24 Jun 25 05:34:17 PM PDT 24 91023748 ps
T563 /workspace/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.363318988 Jun 25 05:34:14 PM PDT 24 Jun 25 05:34:16 PM PDT 24 83535610 ps
T564 /workspace/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.4098208587 Jun 25 05:34:22 PM PDT 24 Jun 25 05:34:24 PM PDT 24 83579633 ps
T81 /workspace/coverage/cover_reg_top/1.rstmgr_tl_intg_err.27823509 Jun 25 05:34:14 PM PDT 24 Jun 25 05:34:18 PM PDT 24 880916706 ps
T565 /workspace/coverage/cover_reg_top/13.rstmgr_csr_rw.11240244 Jun 25 05:34:34 PM PDT 24 Jun 25 05:34:36 PM PDT 24 92822094 ps
T132 /workspace/coverage/cover_reg_top/4.rstmgr_tl_intg_err.236185844 Jun 25 05:34:16 PM PDT 24 Jun 25 05:34:19 PM PDT 24 442540149 ps
T87 /workspace/coverage/cover_reg_top/14.rstmgr_tl_intg_err.2854243734 Jun 25 05:34:25 PM PDT 24 Jun 25 05:34:29 PM PDT 24 425454594 ps
T77 /workspace/coverage/cover_reg_top/12.rstmgr_tl_errors.3393934325 Jun 25 05:34:27 PM PDT 24 Jun 25 05:34:30 PM PDT 24 296733277 ps
T566 /workspace/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.3850926555 Jun 25 05:34:18 PM PDT 24 Jun 25 05:34:21 PM PDT 24 203523579 ps
T567 /workspace/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.2978183156 Jun 25 05:34:25 PM PDT 24 Jun 25 05:34:28 PM PDT 24 236275004 ps
T94 /workspace/coverage/cover_reg_top/15.rstmgr_tl_errors.1720057062 Jun 25 05:34:28 PM PDT 24 Jun 25 05:34:30 PM PDT 24 101620525 ps
T78 /workspace/coverage/cover_reg_top/8.rstmgr_tl_errors.2421029455 Jun 25 05:34:19 PM PDT 24 Jun 25 05:34:23 PM PDT 24 333370362 ps
T91 /workspace/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.1291805769 Jun 25 05:34:14 PM PDT 24 Jun 25 05:34:17 PM PDT 24 171740704 ps
T568 /workspace/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.1475548701 Jun 25 05:34:18 PM PDT 24 Jun 25 05:34:21 PM PDT 24 114166523 ps
T569 /workspace/coverage/cover_reg_top/15.rstmgr_csr_rw.3002954981 Jun 25 05:34:25 PM PDT 24 Jun 25 05:34:28 PM PDT 24 54698096 ps
T570 /workspace/coverage/cover_reg_top/12.rstmgr_csr_rw.70554722 Jun 25 05:34:25 PM PDT 24 Jun 25 05:34:28 PM PDT 24 84736203 ps
T571 /workspace/coverage/cover_reg_top/3.rstmgr_tl_intg_err.400133412 Jun 25 05:34:17 PM PDT 24 Jun 25 05:34:21 PM PDT 24 802153305 ps
T572 /workspace/coverage/cover_reg_top/19.rstmgr_tl_errors.3642900979 Jun 25 05:34:33 PM PDT 24 Jun 25 05:34:36 PM PDT 24 265948307 ps
T573 /workspace/coverage/cover_reg_top/14.rstmgr_csr_rw.2450761446 Jun 25 05:34:24 PM PDT 24 Jun 25 05:34:26 PM PDT 24 64081172 ps
T574 /workspace/coverage/cover_reg_top/10.rstmgr_csr_rw.3258026455 Jun 25 05:34:22 PM PDT 24 Jun 25 05:34:24 PM PDT 24 54565588 ps
T575 /workspace/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.3642842331 Jun 25 05:34:33 PM PDT 24 Jun 25 05:34:35 PM PDT 24 129494821 ps
T576 /workspace/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.1107354696 Jun 25 05:34:17 PM PDT 24 Jun 25 05:34:19 PM PDT 24 130497383 ps
T577 /workspace/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.1434692400 Jun 25 05:34:24 PM PDT 24 Jun 25 05:34:26 PM PDT 24 124444208 ps
T133 /workspace/coverage/cover_reg_top/5.rstmgr_tl_intg_err.3511633218 Jun 25 05:34:19 PM PDT 24 Jun 25 05:34:23 PM PDT 24 848077290 ps
T578 /workspace/coverage/cover_reg_top/2.rstmgr_tl_intg_err.2542702227 Jun 25 05:34:14 PM PDT 24 Jun 25 05:34:17 PM PDT 24 470659170 ps
T579 /workspace/coverage/cover_reg_top/14.rstmgr_tl_errors.2515848261 Jun 25 05:34:27 PM PDT 24 Jun 25 05:34:30 PM PDT 24 212022845 ps
T92 /workspace/coverage/cover_reg_top/3.rstmgr_tl_errors.872873754 Jun 25 05:34:17 PM PDT 24 Jun 25 05:34:20 PM PDT 24 142988739 ps
T580 /workspace/coverage/cover_reg_top/0.rstmgr_tl_intg_err.4057117501 Jun 25 05:34:13 PM PDT 24 Jun 25 05:34:17 PM PDT 24 876034798 ps
T581 /workspace/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.1982696711 Jun 25 05:34:13 PM PDT 24 Jun 25 05:34:15 PM PDT 24 97948140 ps
T582 /workspace/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.2375676008 Jun 25 05:34:17 PM PDT 24 Jun 25 05:34:24 PM PDT 24 478734784 ps
T583 /workspace/coverage/cover_reg_top/8.rstmgr_csr_rw.3856407516 Jun 25 05:34:16 PM PDT 24 Jun 25 05:34:18 PM PDT 24 81575385 ps
T584 /workspace/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.1861056499 Jun 25 05:34:22 PM PDT 24 Jun 25 05:34:24 PM PDT 24 125276543 ps
T585 /workspace/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.3659070730 Jun 25 05:34:18 PM PDT 24 Jun 25 05:34:21 PM PDT 24 223695154 ps
T586 /workspace/coverage/cover_reg_top/18.rstmgr_tl_intg_err.3467745914 Jun 25 05:34:32 PM PDT 24 Jun 25 05:34:36 PM PDT 24 785444370 ps
T587 /workspace/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.1633310177 Jun 25 05:34:42 PM PDT 24 Jun 25 05:34:45 PM PDT 24 189027757 ps
T588 /workspace/coverage/cover_reg_top/7.rstmgr_tl_errors.1006436684 Jun 25 05:34:16 PM PDT 24 Jun 25 05:34:19 PM PDT 24 282190658 ps
T589 /workspace/coverage/cover_reg_top/9.rstmgr_tl_errors.3295604781 Jun 25 05:34:24 PM PDT 24 Jun 25 05:34:27 PM PDT 24 260704382 ps
T590 /workspace/coverage/cover_reg_top/16.rstmgr_csr_rw.1672999989 Jun 25 05:34:34 PM PDT 24 Jun 25 05:34:36 PM PDT 24 81988833 ps
T591 /workspace/coverage/cover_reg_top/18.rstmgr_csr_rw.3380449132 Jun 25 05:34:31 PM PDT 24 Jun 25 05:34:33 PM PDT 24 80273346 ps
T592 /workspace/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.2901352432 Jun 25 05:34:17 PM PDT 24 Jun 25 05:34:19 PM PDT 24 140778068 ps
T593 /workspace/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.4031104612 Jun 25 05:34:19 PM PDT 24 Jun 25 05:34:22 PM PDT 24 263198463 ps
T594 /workspace/coverage/cover_reg_top/17.rstmgr_tl_errors.2237967880 Jun 25 05:34:25 PM PDT 24 Jun 25 05:34:28 PM PDT 24 139570266 ps
T595 /workspace/coverage/cover_reg_top/1.rstmgr_tl_errors.4272000174 Jun 25 05:34:17 PM PDT 24 Jun 25 05:34:21 PM PDT 24 326402481 ps
T596 /workspace/coverage/cover_reg_top/19.rstmgr_csr_rw.4120700010 Jun 25 05:34:39 PM PDT 24 Jun 25 05:34:41 PM PDT 24 58028991 ps
T597 /workspace/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.433624490 Jun 25 05:34:18 PM PDT 24 Jun 25 05:34:21 PM PDT 24 92705817 ps
T598 /workspace/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.2818245452 Jun 25 05:34:33 PM PDT 24 Jun 25 05:34:35 PM PDT 24 132156903 ps
T599 /workspace/coverage/cover_reg_top/9.rstmgr_csr_rw.1465753831 Jun 25 05:34:28 PM PDT 24 Jun 25 05:34:30 PM PDT 24 77739239 ps
T600 /workspace/coverage/cover_reg_top/17.rstmgr_csr_rw.1747480169 Jun 25 05:34:33 PM PDT 24 Jun 25 05:34:35 PM PDT 24 77865924 ps
T601 /workspace/coverage/cover_reg_top/10.rstmgr_tl_errors.3399635282 Jun 25 05:34:25 PM PDT 24 Jun 25 05:34:28 PM PDT 24 253706268 ps
T602 /workspace/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.1168266649 Jun 25 05:34:19 PM PDT 24 Jun 25 05:34:26 PM PDT 24 488617045 ps
T603 /workspace/coverage/cover_reg_top/16.rstmgr_tl_errors.3468638895 Jun 25 05:34:24 PM PDT 24 Jun 25 05:34:28 PM PDT 24 450120626 ps
T604 /workspace/coverage/cover_reg_top/5.rstmgr_csr_rw.1586409377 Jun 25 05:34:19 PM PDT 24 Jun 25 05:34:21 PM PDT 24 69778973 ps
T85 /workspace/coverage/cover_reg_top/11.rstmgr_tl_intg_err.1852332100 Jun 25 05:34:23 PM PDT 24 Jun 25 05:34:26 PM PDT 24 513669113 ps
T605 /workspace/coverage/cover_reg_top/2.rstmgr_csr_rw.766681588 Jun 25 05:34:19 PM PDT 24 Jun 25 05:34:22 PM PDT 24 71446802 ps
T606 /workspace/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.3734950454 Jun 25 05:34:16 PM PDT 24 Jun 25 05:34:18 PM PDT 24 199732197 ps
T607 /workspace/coverage/cover_reg_top/18.rstmgr_tl_errors.312528918 Jun 25 05:34:43 PM PDT 24 Jun 25 05:34:46 PM PDT 24 110242359 ps
T82 /workspace/coverage/cover_reg_top/7.rstmgr_tl_intg_err.166329955 Jun 25 05:34:18 PM PDT 24 Jun 25 05:34:22 PM PDT 24 870962759 ps
T608 /workspace/coverage/cover_reg_top/13.rstmgr_tl_errors.2545756573 Jun 25 05:34:27 PM PDT 24 Jun 25 05:34:29 PM PDT 24 205584021 ps
T609 /workspace/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.3628340636 Jun 25 05:34:29 PM PDT 24 Jun 25 05:34:32 PM PDT 24 221819147 ps
T610 /workspace/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.2767730845 Jun 25 05:34:25 PM PDT 24 Jun 25 05:34:28 PM PDT 24 125327992 ps
T611 /workspace/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.3147593899 Jun 25 05:34:25 PM PDT 24 Jun 25 05:34:28 PM PDT 24 192569739 ps
T612 /workspace/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.273663401 Jun 25 05:34:22 PM PDT 24 Jun 25 05:34:24 PM PDT 24 82360218 ps
T613 /workspace/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.3546751756 Jun 25 05:34:28 PM PDT 24 Jun 25 05:34:31 PM PDT 24 251776791 ps
T614 /workspace/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.3505810559 Jun 25 05:34:22 PM PDT 24 Jun 25 05:34:24 PM PDT 24 136238126 ps
T615 /workspace/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.713899822 Jun 25 05:34:17 PM PDT 24 Jun 25 05:34:27 PM PDT 24 2300184173 ps
T616 /workspace/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.3876681827 Jun 25 05:34:16 PM PDT 24 Jun 25 05:34:17 PM PDT 24 90573983 ps
T617 /workspace/coverage/cover_reg_top/4.rstmgr_tl_errors.736821497 Jun 25 05:34:18 PM PDT 24 Jun 25 05:34:21 PM PDT 24 208666533 ps
T618 /workspace/coverage/cover_reg_top/19.rstmgr_tl_intg_err.3673109074 Jun 25 05:34:42 PM PDT 24 Jun 25 05:34:46 PM PDT 24 876329350 ps
T619 /workspace/coverage/cover_reg_top/0.rstmgr_csr_rw.884523728 Jun 25 05:34:08 PM PDT 24 Jun 25 05:34:12 PM PDT 24 67610941 ps

Test location /workspace/coverage/default/25.rstmgr_stress_all.13990703
Short name T7
Test name
Test status
Simulation time 5134690906 ps
CPU time 23.35 seconds
Started Jun 25 05:38:48 PM PDT 24
Finished Jun 25 05:39:12 PM PDT 24
Peak memory 208600 kb
Host smart-d3579c4f-d8f4-4c4b-a17a-515de90e0441
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13990703 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_stress_all.13990703
Directory /workspace/25.rstmgr_stress_all/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst.3795365756
Short name T38
Test name
Test status
Simulation time 446357998 ps
CPU time 2.33 seconds
Started Jun 25 05:39:17 PM PDT 24
Finished Jun 25 05:39:21 PM PDT 24
Peak memory 200068 kb
Host smart-ff043e3c-c339-4021-a9ce-03c29bff992b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3795365756 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst.3795365756
Directory /workspace/41.rstmgr_sw_rst/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_intg_err.528346977
Short name T54
Test name
Test status
Simulation time 916236680 ps
CPU time 2.96 seconds
Started Jun 25 05:34:16 PM PDT 24
Finished Jun 25 05:34:20 PM PDT 24
Peak memory 200476 kb
Host smart-1147d1db-6693-438a-b7cb-9d5b99d635c0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=528346977 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_intg_err.
528346977
Directory /workspace/8.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm.3093520226
Short name T60
Test name
Test status
Simulation time 8321977839 ps
CPU time 13.02 seconds
Started Jun 25 05:37:58 PM PDT 24
Finished Jun 25 05:38:14 PM PDT 24
Peak memory 216900 kb
Host smart-6560db98-2d75-46a9-b8a3-a0e80f0e11e4
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093520226 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm.3093520226
Directory /workspace/4.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_cnsty.3145500359
Short name T21
Test name
Test status
Simulation time 2197835602 ps
CPU time 8.14 seconds
Started Jun 25 05:38:15 PM PDT 24
Finished Jun 25 05:38:24 PM PDT 24
Peak memory 221736 kb
Host smart-27e6c273-c9e9-43c8-bf71-8e9ccc11de7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3145500359 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_cnsty.3145500359
Directory /workspace/10.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_errors.2453198078
Short name T57
Test name
Test status
Simulation time 426541601 ps
CPU time 3.09 seconds
Started Jun 25 05:34:12 PM PDT 24
Finished Jun 25 05:34:16 PM PDT 24
Peak memory 208332 kb
Host smart-48e3bfe6-dce0-40a6-a7f2-24f1ffec05a9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453198078 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_errors.2453198078
Directory /workspace/0.rstmgr_tl_errors/latest

Test location /workspace/coverage/default/4.rstmgr_stress_all.1993846392
Short name T98
Test name
Test status
Simulation time 7329837011 ps
CPU time 30.33 seconds
Started Jun 25 05:37:56 PM PDT 24
Finished Jun 25 05:38:28 PM PDT 24
Peak memory 208540 kb
Host smart-ea73bad4-4dd1-48aa-93fc-8269315906f6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993846392 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_stress_all.1993846392
Directory /workspace/4.rstmgr_stress_all/latest

Test location /workspace/coverage/default/38.rstmgr_alert_test.1892274683
Short name T34
Test name
Test status
Simulation time 80541421 ps
CPU time 0.82 seconds
Started Jun 25 05:39:08 PM PDT 24
Finished Jun 25 05:39:10 PM PDT 24
Peak memory 199868 kb
Host smart-6be59ddf-b666-4458-9692-91e4000d856a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892274683 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_alert_test.1892274683
Directory /workspace/38.rstmgr_alert_test/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm_scan_intersig_mubi.2019849001
Short name T137
Test name
Test status
Simulation time 151041000 ps
CPU time 1.25 seconds
Started Jun 25 05:37:47 PM PDT 24
Finished Jun 25 05:37:50 PM PDT 24
Peak memory 200068 kb
Host smart-1dbbaf38-7a69-467a-bebd-d6eaa13d48f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2019849001 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm_scan_intersig_mubi.2019849001
Directory /workspace/0.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst_reset_race.2211093060
Short name T162
Test name
Test status
Simulation time 154489952 ps
CPU time 1.35 seconds
Started Jun 25 05:38:50 PM PDT 24
Finished Jun 25 05:38:54 PM PDT 24
Peak memory 200340 kb
Host smart-24b39574-932f-4f72-bcfa-7b3b4461d80d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2211093060 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst_reset_race.2211093060
Directory /workspace/24.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_cnsty.2097315631
Short name T42
Test name
Test status
Simulation time 1229213052 ps
CPU time 5.97 seconds
Started Jun 25 05:38:54 PM PDT 24
Finished Jun 25 05:39:03 PM PDT 24
Peak memory 217780 kb
Host smart-13ec22e8-b404-42e2-84f0-7819b0a0d4cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2097315631 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_cnsty.2097315631
Directory /workspace/33.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_intg_err.166329955
Short name T82
Test name
Test status
Simulation time 870962759 ps
CPU time 3.11 seconds
Started Jun 25 05:34:18 PM PDT 24
Finished Jun 25 05:34:22 PM PDT 24
Peak memory 200492 kb
Host smart-36b95f07-37d0-4b6b-8d42-0819da64528b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166329955 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_intg_err.
166329955
Directory /workspace/7.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_errors.663945515
Short name T59
Test name
Test status
Simulation time 250235752 ps
CPU time 1.97 seconds
Started Jun 25 05:34:18 PM PDT 24
Finished Jun 25 05:34:22 PM PDT 24
Peak memory 211088 kb
Host smart-56e68479-739e-437b-8595-80bc10318a96
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663945515 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_errors.663945515
Directory /workspace/5.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.142906021
Short name T113
Test name
Test status
Simulation time 139207992 ps
CPU time 1.16 seconds
Started Jun 25 05:34:16 PM PDT 24
Finished Jun 25 05:34:18 PM PDT 24
Peak memory 200204 kb
Host smart-b95c27b5-e118-431b-8800-d4a62b9f4f7b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142906021 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_sam
e_csr_outstanding.142906021
Directory /workspace/0.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/default/10.rstmgr_por_stretcher.3770192367
Short name T18
Test name
Test status
Simulation time 67404408 ps
CPU time 0.76 seconds
Started Jun 25 05:38:13 PM PDT 24
Finished Jun 25 05:38:15 PM PDT 24
Peak memory 199880 kb
Host smart-6af7c7eb-7f5b-4167-b6f5-bad1975af441
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3770192367 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_por_stretcher.3770192367
Directory /workspace/10.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm.1687494188
Short name T65
Test name
Test status
Simulation time 8304813898 ps
CPU time 15.79 seconds
Started Jun 25 05:37:49 PM PDT 24
Finished Jun 25 05:38:08 PM PDT 24
Peak memory 217072 kb
Host smart-65d530db-5158-4752-83d8-6c287fe1b2c4
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687494188 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm.1687494188
Directory /workspace/0.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_cnsty.2796328691
Short name T27
Test name
Test status
Simulation time 1883205666 ps
CPU time 7.69 seconds
Started Jun 25 05:38:30 PM PDT 24
Finished Jun 25 05:38:40 PM PDT 24
Peak memory 221664 kb
Host smart-e13aacc1-a865-473f-81ed-58d7d3d337b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2796328691 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_cnsty.2796328691
Directory /workspace/17.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_intg_err.1852332100
Short name T85
Test name
Test status
Simulation time 513669113 ps
CPU time 1.97 seconds
Started Jun 25 05:34:23 PM PDT 24
Finished Jun 25 05:34:26 PM PDT 24
Peak memory 200484 kb
Host smart-f39c2d26-582e-44cf-aa8f-9ebaa771efd3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852332100 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_intg_er
r.1852332100
Directory /workspace/11.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst.2084098080
Short name T3
Test name
Test status
Simulation time 136248778 ps
CPU time 1.64 seconds
Started Jun 25 05:37:49 PM PDT 24
Finished Jun 25 05:37:53 PM PDT 24
Peak memory 208256 kb
Host smart-16a6a71d-59a4-4791-9752-7bd9455bb179
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2084098080 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst.2084098080
Directory /workspace/0.rstmgr_sw_rst/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_aliasing.895079462
Short name T104
Test name
Test status
Simulation time 444953864 ps
CPU time 2.57 seconds
Started Jun 25 05:34:13 PM PDT 24
Finished Jun 25 05:34:16 PM PDT 24
Peak memory 200412 kb
Host smart-35fe9a6f-d3b5-4c3b-a63a-5fb68a538c42
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895079462 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_aliasing.895079462
Directory /workspace/0.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.1292888236
Short name T552
Test name
Test status
Simulation time 480584439 ps
CPU time 5.83 seconds
Started Jun 25 05:34:13 PM PDT 24
Finished Jun 25 05:34:19 PM PDT 24
Peak memory 200344 kb
Host smart-c0e90ded-a10e-4738-ac4c-616eddcfa007
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292888236 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_bit_bash.1
292888236
Directory /workspace/0.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.1701970641
Short name T560
Test name
Test status
Simulation time 91569735 ps
CPU time 0.81 seconds
Started Jun 25 05:34:13 PM PDT 24
Finished Jun 25 05:34:14 PM PDT 24
Peak memory 200152 kb
Host smart-37eb5985-917c-4cee-be90-2dba9683f75b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701970641 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_hw_reset.1
701970641
Directory /workspace/0.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.2387518457
Short name T559
Test name
Test status
Simulation time 123943159 ps
CPU time 1.3 seconds
Started Jun 25 05:34:17 PM PDT 24
Finished Jun 25 05:34:20 PM PDT 24
Peak memory 208532 kb
Host smart-1f9460e9-ec79-4988-b62c-badd79362b6c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387518457 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.rstmgr_csr_mem_rw_with_rand_reset.2387518457
Directory /workspace/0.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_rw.884523728
Short name T619
Test name
Test status
Simulation time 67610941 ps
CPU time 0.88 seconds
Started Jun 25 05:34:08 PM PDT 24
Finished Jun 25 05:34:12 PM PDT 24
Peak memory 200136 kb
Host smart-a87c1ace-2ad9-4be4-b7fe-65830caa8e8d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884523728 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_rw.884523728
Directory /workspace/0.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_intg_err.4057117501
Short name T580
Test name
Test status
Simulation time 876034798 ps
CPU time 2.99 seconds
Started Jun 25 05:34:13 PM PDT 24
Finished Jun 25 05:34:17 PM PDT 24
Peak memory 200308 kb
Host smart-682db87d-57b5-4a89-8b02-7e53eb9c0043
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057117501 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_intg_err
.4057117501
Directory /workspace/0.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_aliasing.4020472078
Short name T548
Test name
Test status
Simulation time 207946274 ps
CPU time 1.72 seconds
Started Jun 25 05:34:15 PM PDT 24
Finished Jun 25 05:34:18 PM PDT 24
Peak memory 200352 kb
Host smart-34318e41-b799-4dcf-807d-fe2fd1385fb3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020472078 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_aliasing.4
020472078
Directory /workspace/1.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.1168266649
Short name T602
Test name
Test status
Simulation time 488617045 ps
CPU time 5.91 seconds
Started Jun 25 05:34:19 PM PDT 24
Finished Jun 25 05:34:26 PM PDT 24
Peak memory 200376 kb
Host smart-7b07c381-8de6-4ad7-a395-0a103eb520ff
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168266649 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_bit_bash.1
168266649
Directory /workspace/1.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.1107354696
Short name T576
Test name
Test status
Simulation time 130497383 ps
CPU time 0.97 seconds
Started Jun 25 05:34:17 PM PDT 24
Finished Jun 25 05:34:19 PM PDT 24
Peak memory 200216 kb
Host smart-965cddeb-d6ed-4559-a534-46c489da01a5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107354696 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_hw_reset.1
107354696
Directory /workspace/1.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.60076643
Short name T553
Test name
Test status
Simulation time 106240458 ps
CPU time 1.01 seconds
Started Jun 25 05:34:17 PM PDT 24
Finished Jun 25 05:34:20 PM PDT 24
Peak memory 200416 kb
Host smart-e5fe8e3f-8c17-420f-8190-82c68559f1bf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60076643 -assert nopostproc +UVM_TESTNAME=r
stmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 1.rstmgr_csr_mem_rw_with_rand_reset.60076643
Directory /workspace/1.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_rw.3895127297
Short name T111
Test name
Test status
Simulation time 67665084 ps
CPU time 0.84 seconds
Started Jun 25 05:34:19 PM PDT 24
Finished Jun 25 05:34:22 PM PDT 24
Peak memory 199980 kb
Host smart-bfc4fb4f-00e0-4940-8c31-178c5b481457
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895127297 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_rw.3895127297
Directory /workspace/1.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.2476949503
Short name T115
Test name
Test status
Simulation time 238538761 ps
CPU time 1.56 seconds
Started Jun 25 05:34:18 PM PDT 24
Finished Jun 25 05:34:22 PM PDT 24
Peak memory 200480 kb
Host smart-38c9619b-1970-44bb-8ef9-7b86d49c976e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476949503 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_sa
me_csr_outstanding.2476949503
Directory /workspace/1.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_errors.4272000174
Short name T595
Test name
Test status
Simulation time 326402481 ps
CPU time 2.48 seconds
Started Jun 25 05:34:17 PM PDT 24
Finished Jun 25 05:34:21 PM PDT 24
Peak memory 208548 kb
Host smart-c09daa7f-910f-494b-a48a-15ef4a25034e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272000174 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_errors.4272000174
Directory /workspace/1.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_intg_err.27823509
Short name T81
Test name
Test status
Simulation time 880916706 ps
CPU time 2.87 seconds
Started Jun 25 05:34:14 PM PDT 24
Finished Jun 25 05:34:18 PM PDT 24
Peak memory 200476 kb
Host smart-8ff36876-1c3a-4ce5-b089-595f391e3995
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27823509 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_intg_err.27823509
Directory /workspace/1.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.908439439
Short name T93
Test name
Test status
Simulation time 116899750 ps
CPU time 1.05 seconds
Started Jun 25 05:34:29 PM PDT 24
Finished Jun 25 05:34:31 PM PDT 24
Peak memory 200332 kb
Host smart-a4814912-abd1-4909-b542-3b71df6b673e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908439439 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 10.rstmgr_csr_mem_rw_with_rand_reset.908439439
Directory /workspace/10.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_rw.3258026455
Short name T574
Test name
Test status
Simulation time 54565588 ps
CPU time 0.77 seconds
Started Jun 25 05:34:22 PM PDT 24
Finished Jun 25 05:34:24 PM PDT 24
Peak memory 200228 kb
Host smart-f89f55a6-dfe1-415c-97d3-02d3d1a0bc5c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258026455 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_csr_rw.3258026455
Directory /workspace/10.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.3546751756
Short name T613
Test name
Test status
Simulation time 251776791 ps
CPU time 1.69 seconds
Started Jun 25 05:34:28 PM PDT 24
Finished Jun 25 05:34:31 PM PDT 24
Peak memory 200340 kb
Host smart-1b8322d9-2ee5-49a9-b128-f8304787300a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546751756 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_s
ame_csr_outstanding.3546751756
Directory /workspace/10.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_errors.3399635282
Short name T601
Test name
Test status
Simulation time 253706268 ps
CPU time 1.98 seconds
Started Jun 25 05:34:25 PM PDT 24
Finished Jun 25 05:34:28 PM PDT 24
Peak memory 208448 kb
Host smart-13eb287a-bcc1-45ea-a235-01360fac248d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399635282 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_errors.3399635282
Directory /workspace/10.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_intg_err.976454273
Short name T558
Test name
Test status
Simulation time 874028393 ps
CPU time 3.37 seconds
Started Jun 25 05:34:28 PM PDT 24
Finished Jun 25 05:34:32 PM PDT 24
Peak memory 200428 kb
Host smart-61df17bb-88af-4c17-84e2-26f3842eabf0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976454273 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_intg_err
.976454273
Directory /workspace/10.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.3147593899
Short name T611
Test name
Test status
Simulation time 192569739 ps
CPU time 1.32 seconds
Started Jun 25 05:34:25 PM PDT 24
Finished Jun 25 05:34:28 PM PDT 24
Peak memory 208484 kb
Host smart-250c9138-4149-480c-bbe9-04c6dd33c535
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3147593899 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.rstmgr_csr_mem_rw_with_rand_reset.3147593899
Directory /workspace/11.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_rw.2220991778
Short name T549
Test name
Test status
Simulation time 67778617 ps
CPU time 0.81 seconds
Started Jun 25 05:34:23 PM PDT 24
Finished Jun 25 05:34:25 PM PDT 24
Peak memory 200092 kb
Host smart-141c41d0-b44d-456d-a983-9ba725e4b7d1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220991778 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_csr_rw.2220991778
Directory /workspace/11.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.1434692400
Short name T577
Test name
Test status
Simulation time 124444208 ps
CPU time 1.09 seconds
Started Jun 25 05:34:24 PM PDT 24
Finished Jun 25 05:34:26 PM PDT 24
Peak memory 200252 kb
Host smart-fa383f76-a256-45af-9540-56b70dc34f62
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434692400 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_s
ame_csr_outstanding.1434692400
Directory /workspace/11.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_errors.2450755734
Short name T95
Test name
Test status
Simulation time 113623884 ps
CPU time 1.6 seconds
Started Jun 25 05:34:33 PM PDT 24
Finished Jun 25 05:34:36 PM PDT 24
Peak memory 211280 kb
Host smart-5046229a-1dd2-4de8-b7cd-87ab362021f9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450755734 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_errors.2450755734
Directory /workspace/11.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.1786379364
Short name T557
Test name
Test status
Simulation time 124994765 ps
CPU time 1.01 seconds
Started Jun 25 05:34:25 PM PDT 24
Finished Jun 25 05:34:28 PM PDT 24
Peak memory 200280 kb
Host smart-b4e6a022-013e-446c-9c1d-fd6ce617d88a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786379364 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 12.rstmgr_csr_mem_rw_with_rand_reset.1786379364
Directory /workspace/12.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_rw.70554722
Short name T570
Test name
Test status
Simulation time 84736203 ps
CPU time 0.81 seconds
Started Jun 25 05:34:25 PM PDT 24
Finished Jun 25 05:34:28 PM PDT 24
Peak memory 200208 kb
Host smart-4b7e6de3-91c0-4ee2-9542-01e07e67da63
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70554722 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_csr_rw.70554722
Directory /workspace/12.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.273663401
Short name T612
Test name
Test status
Simulation time 82360218 ps
CPU time 1.04 seconds
Started Jun 25 05:34:22 PM PDT 24
Finished Jun 25 05:34:24 PM PDT 24
Peak memory 199980 kb
Host smart-c54afe73-33b5-4e40-9853-587a346ac6e4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=273663401 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_sa
me_csr_outstanding.273663401
Directory /workspace/12.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_errors.3393934325
Short name T77
Test name
Test status
Simulation time 296733277 ps
CPU time 2.16 seconds
Started Jun 25 05:34:27 PM PDT 24
Finished Jun 25 05:34:30 PM PDT 24
Peak memory 208464 kb
Host smart-4fe66be6-8d88-478e-b0e6-5798a0fc64ee
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393934325 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_errors.3393934325
Directory /workspace/12.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_intg_err.74681631
Short name T56
Test name
Test status
Simulation time 788369656 ps
CPU time 3.31 seconds
Started Jun 25 05:34:25 PM PDT 24
Finished Jun 25 05:34:30 PM PDT 24
Peak memory 200416 kb
Host smart-07209c2a-d9bc-4c2f-b219-d151a4d83802
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74681631 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_intg_err.74681631
Directory /workspace/12.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.3257649852
Short name T83
Test name
Test status
Simulation time 196613072 ps
CPU time 1.38 seconds
Started Jun 25 05:34:23 PM PDT 24
Finished Jun 25 05:34:26 PM PDT 24
Peak memory 208644 kb
Host smart-2f7f90a0-fede-48e5-a28f-c88f5b755d84
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257649852 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 13.rstmgr_csr_mem_rw_with_rand_reset.3257649852
Directory /workspace/13.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_rw.11240244
Short name T565
Test name
Test status
Simulation time 92822094 ps
CPU time 1.02 seconds
Started Jun 25 05:34:34 PM PDT 24
Finished Jun 25 05:34:36 PM PDT 24
Peak memory 200196 kb
Host smart-14996d7a-2f23-40e1-b380-c696017ef55c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11240244 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_csr_rw.11240244
Directory /workspace/13.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.2978183156
Short name T567
Test name
Test status
Simulation time 236275004 ps
CPU time 1.57 seconds
Started Jun 25 05:34:25 PM PDT 24
Finished Jun 25 05:34:28 PM PDT 24
Peak memory 200388 kb
Host smart-e5f45016-0f43-4c46-bdf7-e217450b64cb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978183156 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_s
ame_csr_outstanding.2978183156
Directory /workspace/13.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_errors.2545756573
Short name T608
Test name
Test status
Simulation time 205584021 ps
CPU time 1.71 seconds
Started Jun 25 05:34:27 PM PDT 24
Finished Jun 25 05:34:29 PM PDT 24
Peak memory 216640 kb
Host smart-64bc1a72-d221-4ab4-8c41-36876120605a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545756573 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_errors.2545756573
Directory /workspace/13.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_intg_err.3184180457
Short name T79
Test name
Test status
Simulation time 475865247 ps
CPU time 2.14 seconds
Started Jun 25 05:34:25 PM PDT 24
Finished Jun 25 05:34:29 PM PDT 24
Peak memory 200476 kb
Host smart-44f65edb-668a-4276-94e0-71735b776973
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3184180457 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_intg_er
r.3184180457
Directory /workspace/13.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.1861056499
Short name T584
Test name
Test status
Simulation time 125276543 ps
CPU time 1.04 seconds
Started Jun 25 05:34:22 PM PDT 24
Finished Jun 25 05:34:24 PM PDT 24
Peak memory 200344 kb
Host smart-3ff13a34-f2a4-4400-969e-6a8ab3ec9ebb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861056499 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.rstmgr_csr_mem_rw_with_rand_reset.1861056499
Directory /workspace/14.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_rw.2450761446
Short name T573
Test name
Test status
Simulation time 64081172 ps
CPU time 0.81 seconds
Started Jun 25 05:34:24 PM PDT 24
Finished Jun 25 05:34:26 PM PDT 24
Peak memory 200212 kb
Host smart-52cff1d7-b3ca-4198-875c-d90e98435310
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450761446 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_csr_rw.2450761446
Directory /workspace/14.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.1267864603
Short name T114
Test name
Test status
Simulation time 128816649 ps
CPU time 1.34 seconds
Started Jun 25 05:34:27 PM PDT 24
Finished Jun 25 05:34:29 PM PDT 24
Peak memory 200408 kb
Host smart-787541a1-6656-4723-9562-e9b1d46227d1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267864603 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_s
ame_csr_outstanding.1267864603
Directory /workspace/14.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_errors.2515848261
Short name T579
Test name
Test status
Simulation time 212022845 ps
CPU time 1.7 seconds
Started Jun 25 05:34:27 PM PDT 24
Finished Jun 25 05:34:30 PM PDT 24
Peak memory 208532 kb
Host smart-d6c020db-285d-4fb2-86cc-a77e0c5cc7bf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515848261 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_errors.2515848261
Directory /workspace/14.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_intg_err.2854243734
Short name T87
Test name
Test status
Simulation time 425454594 ps
CPU time 1.9 seconds
Started Jun 25 05:34:25 PM PDT 24
Finished Jun 25 05:34:29 PM PDT 24
Peak memory 200444 kb
Host smart-51ed0fc4-ec81-46b2-bb09-ba613a50efda
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854243734 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_intg_er
r.2854243734
Directory /workspace/14.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.1477672808
Short name T90
Test name
Test status
Simulation time 113373096 ps
CPU time 1.12 seconds
Started Jun 25 05:34:24 PM PDT 24
Finished Jun 25 05:34:27 PM PDT 24
Peak memory 211444 kb
Host smart-7737e4b4-ecff-4b3f-9180-7ffbc545e1a7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1477672808 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.rstmgr_csr_mem_rw_with_rand_reset.1477672808
Directory /workspace/15.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_rw.3002954981
Short name T569
Test name
Test status
Simulation time 54698096 ps
CPU time 0.8 seconds
Started Jun 25 05:34:25 PM PDT 24
Finished Jun 25 05:34:28 PM PDT 24
Peak memory 200048 kb
Host smart-9af51370-0bbe-4f00-8724-3ff21178b537
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002954981 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_csr_rw.3002954981
Directory /workspace/15.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.2498400311
Short name T55
Test name
Test status
Simulation time 231202055 ps
CPU time 1.45 seconds
Started Jun 25 05:34:23 PM PDT 24
Finished Jun 25 05:34:26 PM PDT 24
Peak memory 200500 kb
Host smart-2976546d-ddb3-41dc-a2e9-1395f5cdc146
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498400311 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_s
ame_csr_outstanding.2498400311
Directory /workspace/15.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_errors.1720057062
Short name T94
Test name
Test status
Simulation time 101620525 ps
CPU time 1.52 seconds
Started Jun 25 05:34:28 PM PDT 24
Finished Jun 25 05:34:30 PM PDT 24
Peak memory 208540 kb
Host smart-4a660e87-775c-401a-b214-22f92ef1cda3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720057062 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_errors.1720057062
Directory /workspace/15.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_intg_err.1613026778
Short name T89
Test name
Test status
Simulation time 873945433 ps
CPU time 3 seconds
Started Jun 25 05:34:27 PM PDT 24
Finished Jun 25 05:34:31 PM PDT 24
Peak memory 200332 kb
Host smart-ffa94509-b6d7-4cce-a993-a10cc6044b6f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613026778 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_intg_er
r.1613026778
Directory /workspace/15.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.3065072020
Short name T58
Test name
Test status
Simulation time 169365321 ps
CPU time 1.23 seconds
Started Jun 25 05:34:34 PM PDT 24
Finished Jun 25 05:34:36 PM PDT 24
Peak memory 208544 kb
Host smart-c1fc4b1f-cc93-407f-8c0d-191599c97dc8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065072020 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 16.rstmgr_csr_mem_rw_with_rand_reset.3065072020
Directory /workspace/16.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_rw.1672999989
Short name T590
Test name
Test status
Simulation time 81988833 ps
CPU time 0.91 seconds
Started Jun 25 05:34:34 PM PDT 24
Finished Jun 25 05:34:36 PM PDT 24
Peak memory 200208 kb
Host smart-4b49ea61-15c0-4d2a-a951-6debe37791d7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672999989 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_csr_rw.1672999989
Directory /workspace/16.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.509746480
Short name T561
Test name
Test status
Simulation time 83074273 ps
CPU time 0.99 seconds
Started Jun 25 05:34:23 PM PDT 24
Finished Jun 25 05:34:25 PM PDT 24
Peak memory 200268 kb
Host smart-69f528ad-09a9-49f8-b452-c63aa21b797b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509746480 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_sa
me_csr_outstanding.509746480
Directory /workspace/16.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_errors.3468638895
Short name T603
Test name
Test status
Simulation time 450120626 ps
CPU time 3.09 seconds
Started Jun 25 05:34:24 PM PDT 24
Finished Jun 25 05:34:28 PM PDT 24
Peak memory 211916 kb
Host smart-ee779b5e-2913-4094-9d26-c103d64e60eb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468638895 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_errors.3468638895
Directory /workspace/16.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_intg_err.3710325654
Short name T88
Test name
Test status
Simulation time 793169222 ps
CPU time 2.93 seconds
Started Jun 25 05:34:24 PM PDT 24
Finished Jun 25 05:34:28 PM PDT 24
Peak memory 200424 kb
Host smart-374261cc-34fc-43c3-a41e-166dd65d4178
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710325654 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_intg_er
r.3710325654
Directory /workspace/16.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.2818245452
Short name T598
Test name
Test status
Simulation time 132156903 ps
CPU time 1.17 seconds
Started Jun 25 05:34:33 PM PDT 24
Finished Jun 25 05:34:35 PM PDT 24
Peak memory 208540 kb
Host smart-29a1a556-60cb-4e0f-b1bb-8f5c5f0cd60f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818245452 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.rstmgr_csr_mem_rw_with_rand_reset.2818245452
Directory /workspace/17.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_rw.1747480169
Short name T600
Test name
Test status
Simulation time 77865924 ps
CPU time 0.88 seconds
Started Jun 25 05:34:33 PM PDT 24
Finished Jun 25 05:34:35 PM PDT 24
Peak memory 200204 kb
Host smart-6c35fa7c-481a-4470-b0bb-9d39723f70d6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747480169 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_csr_rw.1747480169
Directory /workspace/17.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.3642842331
Short name T575
Test name
Test status
Simulation time 129494821 ps
CPU time 1.19 seconds
Started Jun 25 05:34:33 PM PDT 24
Finished Jun 25 05:34:35 PM PDT 24
Peak memory 200284 kb
Host smart-694f23a3-7cf8-4fda-858a-fa6898bbdc91
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3642842331 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_s
ame_csr_outstanding.3642842331
Directory /workspace/17.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_errors.2237967880
Short name T594
Test name
Test status
Simulation time 139570266 ps
CPU time 1.87 seconds
Started Jun 25 05:34:25 PM PDT 24
Finished Jun 25 05:34:28 PM PDT 24
Peak memory 212108 kb
Host smart-2558af6b-884b-4239-94ac-e2d7fd60bab8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237967880 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_errors.2237967880
Directory /workspace/17.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_intg_err.2797104016
Short name T64
Test name
Test status
Simulation time 445364740 ps
CPU time 1.89 seconds
Started Jun 25 05:34:29 PM PDT 24
Finished Jun 25 05:34:32 PM PDT 24
Peak memory 200480 kb
Host smart-ca46c4e2-11d3-4ad4-ad7e-50f072d131d9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797104016 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_intg_er
r.2797104016
Directory /workspace/17.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.1633310177
Short name T587
Test name
Test status
Simulation time 189027757 ps
CPU time 1.38 seconds
Started Jun 25 05:34:42 PM PDT 24
Finished Jun 25 05:34:45 PM PDT 24
Peak memory 208532 kb
Host smart-635ac065-1d12-403f-b851-851e342bfedf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633310177 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.rstmgr_csr_mem_rw_with_rand_reset.1633310177
Directory /workspace/18.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_rw.3380449132
Short name T591
Test name
Test status
Simulation time 80273346 ps
CPU time 0.85 seconds
Started Jun 25 05:34:31 PM PDT 24
Finished Jun 25 05:34:33 PM PDT 24
Peak memory 200180 kb
Host smart-4a1782e9-465e-4ab0-b05a-3d423b24a50b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380449132 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_csr_rw.3380449132
Directory /workspace/18.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.2289361326
Short name T109
Test name
Test status
Simulation time 207242362 ps
CPU time 1.5 seconds
Started Jun 25 05:34:32 PM PDT 24
Finished Jun 25 05:34:35 PM PDT 24
Peak memory 200448 kb
Host smart-f6a6ad2e-3b1a-4732-8ffb-2652c6be8d2c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289361326 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_s
ame_csr_outstanding.2289361326
Directory /workspace/18.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_errors.312528918
Short name T607
Test name
Test status
Simulation time 110242359 ps
CPU time 1.71 seconds
Started Jun 25 05:34:43 PM PDT 24
Finished Jun 25 05:34:46 PM PDT 24
Peak memory 211144 kb
Host smart-1e6084f5-8c00-445e-aa70-ce1c9263d1e5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312528918 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_errors.312528918
Directory /workspace/18.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_intg_err.3467745914
Short name T586
Test name
Test status
Simulation time 785444370 ps
CPU time 3.01 seconds
Started Jun 25 05:34:32 PM PDT 24
Finished Jun 25 05:34:36 PM PDT 24
Peak memory 200320 kb
Host smart-79fc0c07-6748-4fc7-9544-666dec39041d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467745914 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_intg_er
r.3467745914
Directory /workspace/18.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.3982710017
Short name T554
Test name
Test status
Simulation time 199414715 ps
CPU time 1.38 seconds
Started Jun 25 05:34:33 PM PDT 24
Finished Jun 25 05:34:35 PM PDT 24
Peak memory 208444 kb
Host smart-15c30b2c-6ecf-42df-897d-cc94217fd1d1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3982710017 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.rstmgr_csr_mem_rw_with_rand_reset.3982710017
Directory /workspace/19.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_rw.4120700010
Short name T596
Test name
Test status
Simulation time 58028991 ps
CPU time 0.82 seconds
Started Jun 25 05:34:39 PM PDT 24
Finished Jun 25 05:34:41 PM PDT 24
Peak memory 200328 kb
Host smart-dcde0833-87d7-4805-8b2e-cee1139cffb2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120700010 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_csr_rw.4120700010
Directory /workspace/19.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.2040164272
Short name T112
Test name
Test status
Simulation time 77079185 ps
CPU time 0.91 seconds
Started Jun 25 05:34:42 PM PDT 24
Finished Jun 25 05:34:44 PM PDT 24
Peak memory 200264 kb
Host smart-0c31ab0d-cc1d-4f90-ae55-c4435134a8ff
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040164272 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_s
ame_csr_outstanding.2040164272
Directory /workspace/19.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_errors.3642900979
Short name T572
Test name
Test status
Simulation time 265948307 ps
CPU time 1.92 seconds
Started Jun 25 05:34:33 PM PDT 24
Finished Jun 25 05:34:36 PM PDT 24
Peak memory 208596 kb
Host smart-512250a0-b08d-4420-894c-f3f9a9f5ee63
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3642900979 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_errors.3642900979
Directory /workspace/19.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_intg_err.3673109074
Short name T618
Test name
Test status
Simulation time 876329350 ps
CPU time 2.86 seconds
Started Jun 25 05:34:42 PM PDT 24
Finished Jun 25 05:34:46 PM PDT 24
Peak memory 200460 kb
Host smart-f89bed43-ce82-449a-ae45-6b129ef22036
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673109074 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_intg_er
r.3673109074
Directory /workspace/19.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_aliasing.3772075822
Short name T551
Test name
Test status
Simulation time 355333584 ps
CPU time 2.57 seconds
Started Jun 25 05:34:18 PM PDT 24
Finished Jun 25 05:34:23 PM PDT 24
Peak memory 200384 kb
Host smart-47ec1501-3c91-4797-a881-858313dd20d5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772075822 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_aliasing.3
772075822
Directory /workspace/2.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.610885279
Short name T546
Test name
Test status
Simulation time 478823111 ps
CPU time 5.83 seconds
Started Jun 25 05:34:16 PM PDT 24
Finished Jun 25 05:34:22 PM PDT 24
Peak memory 200364 kb
Host smart-49d5ed55-7c1a-4f33-b5e4-6858b1ec3a58
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=610885279 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_bit_bash.610885279
Directory /workspace/2.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.1982696711
Short name T581
Test name
Test status
Simulation time 97948140 ps
CPU time 0.85 seconds
Started Jun 25 05:34:13 PM PDT 24
Finished Jun 25 05:34:15 PM PDT 24
Peak memory 200384 kb
Host smart-0d329c6d-0cb6-4343-8775-2ecb29e8d24c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1982696711 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_hw_reset.1
982696711
Directory /workspace/2.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.1475548701
Short name T568
Test name
Test status
Simulation time 114166523 ps
CPU time 1.24 seconds
Started Jun 25 05:34:18 PM PDT 24
Finished Jun 25 05:34:21 PM PDT 24
Peak memory 208532 kb
Host smart-b8f7506b-0111-44cb-94fd-1a15546c7a55
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475548701 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.rstmgr_csr_mem_rw_with_rand_reset.1475548701
Directory /workspace/2.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_rw.766681588
Short name T605
Test name
Test status
Simulation time 71446802 ps
CPU time 0.86 seconds
Started Jun 25 05:34:19 PM PDT 24
Finished Jun 25 05:34:22 PM PDT 24
Peak memory 200208 kb
Host smart-4e03635e-3eb9-4f09-9889-f09c0788a245
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766681588 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_rw.766681588
Directory /workspace/2.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.2901352432
Short name T592
Test name
Test status
Simulation time 140778068 ps
CPU time 1.09 seconds
Started Jun 25 05:34:17 PM PDT 24
Finished Jun 25 05:34:19 PM PDT 24
Peak memory 200244 kb
Host smart-645f3f1c-c568-4866-b0ea-940e172c0f67
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901352432 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_sa
me_csr_outstanding.2901352432
Directory /workspace/2.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_errors.3512251421
Short name T86
Test name
Test status
Simulation time 433783372 ps
CPU time 2.82 seconds
Started Jun 25 05:34:15 PM PDT 24
Finished Jun 25 05:34:19 PM PDT 24
Peak memory 208548 kb
Host smart-a0fc5dd7-e4d1-4a14-96d4-b732c61618cd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512251421 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_errors.3512251421
Directory /workspace/2.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_intg_err.2542702227
Short name T578
Test name
Test status
Simulation time 470659170 ps
CPU time 2.05 seconds
Started Jun 25 05:34:14 PM PDT 24
Finished Jun 25 05:34:17 PM PDT 24
Peak memory 200516 kb
Host smart-ca7ca68b-3d0f-4fbf-a6ff-c9e1bff9499b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542702227 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_intg_err
.2542702227
Directory /workspace/2.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_aliasing.406994121
Short name T545
Test name
Test status
Simulation time 251026787 ps
CPU time 1.71 seconds
Started Jun 25 05:34:19 PM PDT 24
Finished Jun 25 05:34:22 PM PDT 24
Peak memory 200268 kb
Host smart-7f57228c-afa1-4027-8d7c-99d400fbbe19
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406994121 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_aliasing.406994121
Directory /workspace/3.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.2375676008
Short name T582
Test name
Test status
Simulation time 478734784 ps
CPU time 5.91 seconds
Started Jun 25 05:34:17 PM PDT 24
Finished Jun 25 05:34:24 PM PDT 24
Peak memory 200368 kb
Host smart-3ae76096-b068-4ab1-bd41-ae9ea03c826e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375676008 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_bit_bash.2
375676008
Directory /workspace/3.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.433624490
Short name T597
Test name
Test status
Simulation time 92705817 ps
CPU time 0.87 seconds
Started Jun 25 05:34:18 PM PDT 24
Finished Jun 25 05:34:21 PM PDT 24
Peak memory 200256 kb
Host smart-14a8f04a-3740-49db-a369-3642f68abd5f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433624490 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_hw_reset.433624490
Directory /workspace/3.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.3734950454
Short name T606
Test name
Test status
Simulation time 199732197 ps
CPU time 1.39 seconds
Started Jun 25 05:34:16 PM PDT 24
Finished Jun 25 05:34:18 PM PDT 24
Peak memory 208688 kb
Host smart-26e2c105-0fee-4f82-b816-04dcf967d2aa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3734950454 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.rstmgr_csr_mem_rw_with_rand_reset.3734950454
Directory /workspace/3.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_rw.3368230786
Short name T550
Test name
Test status
Simulation time 75399515 ps
CPU time 0.83 seconds
Started Jun 25 05:34:17 PM PDT 24
Finished Jun 25 05:34:18 PM PDT 24
Peak memory 200144 kb
Host smart-d9ec17c6-98e3-48a4-bd05-7b731cf299de
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368230786 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_rw.3368230786
Directory /workspace/3.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.4098208587
Short name T564
Test name
Test status
Simulation time 83579633 ps
CPU time 0.9 seconds
Started Jun 25 05:34:22 PM PDT 24
Finished Jun 25 05:34:24 PM PDT 24
Peak memory 200184 kb
Host smart-648dae34-7986-4327-a19e-24d42d23452b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098208587 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_sa
me_csr_outstanding.4098208587
Directory /workspace/3.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_errors.872873754
Short name T92
Test name
Test status
Simulation time 142988739 ps
CPU time 2.21 seconds
Started Jun 25 05:34:17 PM PDT 24
Finished Jun 25 05:34:20 PM PDT 24
Peak memory 208548 kb
Host smart-eda5738a-2435-4d2b-9ad0-fb9c448cfdf5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872873754 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_errors.872873754
Directory /workspace/3.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_intg_err.400133412
Short name T571
Test name
Test status
Simulation time 802153305 ps
CPU time 2.77 seconds
Started Jun 25 05:34:17 PM PDT 24
Finished Jun 25 05:34:21 PM PDT 24
Peak memory 200420 kb
Host smart-96f90816-49f5-4cf0-8d5a-95a004ffd4e5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400133412 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_intg_err.
400133412
Directory /workspace/3.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_aliasing.3791192237
Short name T556
Test name
Test status
Simulation time 267333324 ps
CPU time 1.78 seconds
Started Jun 25 05:34:17 PM PDT 24
Finished Jun 25 05:34:20 PM PDT 24
Peak memory 200368 kb
Host smart-ac71fa4a-7e9f-4701-98a9-835c98db080a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3791192237 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_aliasing.3
791192237
Directory /workspace/4.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.713899822
Short name T615
Test name
Test status
Simulation time 2300184173 ps
CPU time 9.33 seconds
Started Jun 25 05:34:17 PM PDT 24
Finished Jun 25 05:34:27 PM PDT 24
Peak memory 200412 kb
Host smart-784f115b-c3f9-41bc-aec6-b17c68e8415e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713899822 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_bit_bash.713899822
Directory /workspace/4.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.3505810559
Short name T614
Test name
Test status
Simulation time 136238126 ps
CPU time 0.97 seconds
Started Jun 25 05:34:22 PM PDT 24
Finished Jun 25 05:34:24 PM PDT 24
Peak memory 200128 kb
Host smart-a5386741-4b1c-4345-8e9b-777dd431ceb3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505810559 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_hw_reset.3
505810559
Directory /workspace/4.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.2709690585
Short name T555
Test name
Test status
Simulation time 183617072 ps
CPU time 1.2 seconds
Started Jun 25 05:34:13 PM PDT 24
Finished Jun 25 05:34:15 PM PDT 24
Peak memory 209904 kb
Host smart-42e62be7-e351-4fd6-a5a1-57b981880ffb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709690585 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.rstmgr_csr_mem_rw_with_rand_reset.2709690585
Directory /workspace/4.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_rw.3998690654
Short name T547
Test name
Test status
Simulation time 77620349 ps
CPU time 0.84 seconds
Started Jun 25 05:34:17 PM PDT 24
Finished Jun 25 05:34:19 PM PDT 24
Peak memory 200200 kb
Host smart-12ace4ac-2f88-474a-9048-64c1ef21461a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998690654 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_rw.3998690654
Directory /workspace/4.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.4031104612
Short name T593
Test name
Test status
Simulation time 263198463 ps
CPU time 1.59 seconds
Started Jun 25 05:34:19 PM PDT 24
Finished Jun 25 05:34:22 PM PDT 24
Peak memory 200300 kb
Host smart-73e4c861-728d-4424-b342-752d695d822f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031104612 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_sa
me_csr_outstanding.4031104612
Directory /workspace/4.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_errors.736821497
Short name T617
Test name
Test status
Simulation time 208666533 ps
CPU time 1.7 seconds
Started Jun 25 05:34:18 PM PDT 24
Finished Jun 25 05:34:21 PM PDT 24
Peak memory 211704 kb
Host smart-c650da44-ee71-4f5f-a252-a6fbea7a7bbe
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736821497 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_errors.736821497
Directory /workspace/4.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_intg_err.236185844
Short name T132
Test name
Test status
Simulation time 442540149 ps
CPU time 1.78 seconds
Started Jun 25 05:34:16 PM PDT 24
Finished Jun 25 05:34:19 PM PDT 24
Peak memory 200504 kb
Host smart-605c7cf2-2efd-4bc6-bd52-87aab4d669ac
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236185844 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_intg_err.
236185844
Directory /workspace/4.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.3850926555
Short name T566
Test name
Test status
Simulation time 203523579 ps
CPU time 1.47 seconds
Started Jun 25 05:34:18 PM PDT 24
Finished Jun 25 05:34:21 PM PDT 24
Peak memory 208528 kb
Host smart-c3beed31-78e0-4e87-8d6e-7f8907ef0eb5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850926555 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.rstmgr_csr_mem_rw_with_rand_reset.3850926555
Directory /workspace/5.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_rw.1586409377
Short name T604
Test name
Test status
Simulation time 69778973 ps
CPU time 0.8 seconds
Started Jun 25 05:34:19 PM PDT 24
Finished Jun 25 05:34:21 PM PDT 24
Peak memory 200216 kb
Host smart-478b9cc1-74bc-4dbe-82d3-c9117847d7de
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586409377 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_csr_rw.1586409377
Directory /workspace/5.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.2490668797
Short name T76
Test name
Test status
Simulation time 105731159 ps
CPU time 1.26 seconds
Started Jun 25 05:34:15 PM PDT 24
Finished Jun 25 05:34:17 PM PDT 24
Peak memory 200372 kb
Host smart-fda11aff-6a89-47c0-bfe2-b6ad25e2122c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490668797 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_sa
me_csr_outstanding.2490668797
Directory /workspace/5.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_intg_err.3511633218
Short name T133
Test name
Test status
Simulation time 848077290 ps
CPU time 2.71 seconds
Started Jun 25 05:34:19 PM PDT 24
Finished Jun 25 05:34:23 PM PDT 24
Peak memory 200348 kb
Host smart-9daa97fe-9ba1-4d17-8daf-d04b79dd302a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511633218 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_intg_err
.3511633218
Directory /workspace/5.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.1291805769
Short name T91
Test name
Test status
Simulation time 171740704 ps
CPU time 1.77 seconds
Started Jun 25 05:34:14 PM PDT 24
Finished Jun 25 05:34:17 PM PDT 24
Peak memory 208620 kb
Host smart-59ec24b4-a488-41d6-a20c-93cdfc54ff4b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1291805769 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.rstmgr_csr_mem_rw_with_rand_reset.1291805769
Directory /workspace/6.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_rw.1554717990
Short name T116
Test name
Test status
Simulation time 66082857 ps
CPU time 0.81 seconds
Started Jun 25 05:34:17 PM PDT 24
Finished Jun 25 05:34:19 PM PDT 24
Peak memory 200200 kb
Host smart-4bca75ca-e429-4518-b15e-d0dc3694db2f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554717990 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_csr_rw.1554717990
Directory /workspace/6.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.363318988
Short name T563
Test name
Test status
Simulation time 83535610 ps
CPU time 1.09 seconds
Started Jun 25 05:34:14 PM PDT 24
Finished Jun 25 05:34:16 PM PDT 24
Peak memory 200176 kb
Host smart-a30f8561-c0c8-4654-9fb9-c0765a4b13dd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363318988 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_sam
e_csr_outstanding.363318988
Directory /workspace/6.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_errors.3795302046
Short name T75
Test name
Test status
Simulation time 395789687 ps
CPU time 2.91 seconds
Started Jun 25 05:34:13 PM PDT 24
Finished Jun 25 05:34:17 PM PDT 24
Peak memory 212124 kb
Host smart-c6b8900f-dd2c-4c15-b91e-47b2a2c3f8ff
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795302046 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_errors.3795302046
Directory /workspace/6.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_intg_err.2832544930
Short name T80
Test name
Test status
Simulation time 502617237 ps
CPU time 1.86 seconds
Started Jun 25 05:34:22 PM PDT 24
Finished Jun 25 05:34:24 PM PDT 24
Peak memory 200336 kb
Host smart-fd8680f1-3678-47ec-ac07-df0589247d91
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832544930 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_intg_err
.2832544930
Directory /workspace/6.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.3876681827
Short name T616
Test name
Test status
Simulation time 90573983 ps
CPU time 0.89 seconds
Started Jun 25 05:34:16 PM PDT 24
Finished Jun 25 05:34:17 PM PDT 24
Peak memory 200284 kb
Host smart-2cae1825-04ac-41b9-83b0-85c4f90936f7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876681827 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.rstmgr_csr_mem_rw_with_rand_reset.3876681827
Directory /workspace/7.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_rw.3515119255
Short name T562
Test name
Test status
Simulation time 91023748 ps
CPU time 0.86 seconds
Started Jun 25 05:34:15 PM PDT 24
Finished Jun 25 05:34:17 PM PDT 24
Peak memory 200128 kb
Host smart-d38c5bbb-7b0f-477d-ba2b-5704cadb172f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515119255 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_csr_rw.3515119255
Directory /workspace/7.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.3659070730
Short name T585
Test name
Test status
Simulation time 223695154 ps
CPU time 1.58 seconds
Started Jun 25 05:34:18 PM PDT 24
Finished Jun 25 05:34:21 PM PDT 24
Peak memory 200224 kb
Host smart-61a507d2-2345-4e4e-ac42-017cc78fb89a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659070730 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_sa
me_csr_outstanding.3659070730
Directory /workspace/7.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_errors.1006436684
Short name T588
Test name
Test status
Simulation time 282190658 ps
CPU time 2.37 seconds
Started Jun 25 05:34:16 PM PDT 24
Finished Jun 25 05:34:19 PM PDT 24
Peak memory 208552 kb
Host smart-95e33bca-ad8d-4d89-9f68-69fe200348f2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006436684 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_errors.1006436684
Directory /workspace/7.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.1230356801
Short name T96
Test name
Test status
Simulation time 114579369 ps
CPU time 1.13 seconds
Started Jun 25 05:34:28 PM PDT 24
Finished Jun 25 05:34:30 PM PDT 24
Peak memory 208468 kb
Host smart-6124e4a3-67c2-4060-bf8e-28cd7601c692
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230356801 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.rstmgr_csr_mem_rw_with_rand_reset.1230356801
Directory /workspace/8.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_rw.3856407516
Short name T583
Test name
Test status
Simulation time 81575385 ps
CPU time 0.83 seconds
Started Jun 25 05:34:16 PM PDT 24
Finished Jun 25 05:34:18 PM PDT 24
Peak memory 200208 kb
Host smart-73a93d41-a55a-4cfe-a488-3230c041a2b3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3856407516 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_csr_rw.3856407516
Directory /workspace/8.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.2132754457
Short name T110
Test name
Test status
Simulation time 94789205 ps
CPU time 1.22 seconds
Started Jun 25 05:34:24 PM PDT 24
Finished Jun 25 05:34:27 PM PDT 24
Peak memory 200376 kb
Host smart-23cd2bf5-61ad-462c-b47e-2b2290efbcf2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132754457 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_sa
me_csr_outstanding.2132754457
Directory /workspace/8.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_errors.2421029455
Short name T78
Test name
Test status
Simulation time 333370362 ps
CPU time 2.41 seconds
Started Jun 25 05:34:19 PM PDT 24
Finished Jun 25 05:34:23 PM PDT 24
Peak memory 211220 kb
Host smart-ae0ce8c0-3dc9-4fed-a03b-af9c24b78b39
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421029455 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_errors.2421029455
Directory /workspace/8.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.2767730845
Short name T610
Test name
Test status
Simulation time 125327992 ps
CPU time 1.11 seconds
Started Jun 25 05:34:25 PM PDT 24
Finished Jun 25 05:34:28 PM PDT 24
Peak memory 200336 kb
Host smart-18bd67d6-d56f-4143-839c-1a72c8e33fea
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767730845 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.rstmgr_csr_mem_rw_with_rand_reset.2767730845
Directory /workspace/9.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_rw.1465753831
Short name T599
Test name
Test status
Simulation time 77739239 ps
CPU time 0.89 seconds
Started Jun 25 05:34:28 PM PDT 24
Finished Jun 25 05:34:30 PM PDT 24
Peak memory 200212 kb
Host smart-d3551baf-f025-420c-8ea2-f19ca6e78a18
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465753831 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_csr_rw.1465753831
Directory /workspace/9.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.3628340636
Short name T609
Test name
Test status
Simulation time 221819147 ps
CPU time 1.53 seconds
Started Jun 25 05:34:29 PM PDT 24
Finished Jun 25 05:34:32 PM PDT 24
Peak memory 200396 kb
Host smart-e4e7c9ec-2210-424a-af69-8cdbd83860cd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628340636 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_sa
me_csr_outstanding.3628340636
Directory /workspace/9.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_errors.3295604781
Short name T589
Test name
Test status
Simulation time 260704382 ps
CPU time 2.07 seconds
Started Jun 25 05:34:24 PM PDT 24
Finished Jun 25 05:34:27 PM PDT 24
Peak memory 208436 kb
Host smart-c9599754-5704-4b52-ba28-fe3e1e6c9ca6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3295604781 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_errors.3295604781
Directory /workspace/9.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_intg_err.933856319
Short name T84
Test name
Test status
Simulation time 422657419 ps
CPU time 1.98 seconds
Started Jun 25 05:34:34 PM PDT 24
Finished Jun 25 05:34:37 PM PDT 24
Peak memory 200424 kb
Host smart-ae1d744b-44b8-4d1f-b5e7-f58bb224b763
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=933856319 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_intg_err.
933856319
Directory /workspace/9.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.rstmgr_alert_test.2348300748
Short name T502
Test name
Test status
Simulation time 67332775 ps
CPU time 0.79 seconds
Started Jun 25 05:37:48 PM PDT 24
Finished Jun 25 05:37:50 PM PDT 24
Peak memory 199876 kb
Host smart-aae4f4fe-52ca-4c2e-b25d-3fdbda79d98a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348300748 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_alert_test.2348300748
Directory /workspace/0.rstmgr_alert_test/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_cnsty.3249769304
Short name T391
Test name
Test status
Simulation time 1892789783 ps
CPU time 7.58 seconds
Started Jun 25 05:37:50 PM PDT 24
Finished Jun 25 05:38:00 PM PDT 24
Peak memory 217532 kb
Host smart-a629f69f-d4fe-4e8a-b348-3524c1d48fc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3249769304 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_cnsty.3249769304
Directory /workspace/0.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_shadow_attack.3528628836
Short name T489
Test name
Test status
Simulation time 251070263 ps
CPU time 1.1 seconds
Started Jun 25 05:37:48 PM PDT 24
Finished Jun 25 05:37:50 PM PDT 24
Peak memory 217460 kb
Host smart-8f4b5884-c86a-4972-bb9d-be524fcb28d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3528628836 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_shadow_attack.3528628836
Directory /workspace/0.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/0.rstmgr_por_stretcher.1421435201
Short name T220
Test name
Test status
Simulation time 169361539 ps
CPU time 0.87 seconds
Started Jun 25 05:37:48 PM PDT 24
Finished Jun 25 05:37:51 PM PDT 24
Peak memory 199848 kb
Host smart-ecd1e5f1-9d39-493c-acbf-f6ef053e9bbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1421435201 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_por_stretcher.1421435201
Directory /workspace/0.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/0.rstmgr_reset.1118783838
Short name T49
Test name
Test status
Simulation time 928995862 ps
CPU time 4.65 seconds
Started Jun 25 05:37:49 PM PDT 24
Finished Jun 25 05:37:55 PM PDT 24
Peak memory 200392 kb
Host smart-819797da-5fbd-4966-90c6-770e55aa644b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1118783838 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_reset.1118783838
Directory /workspace/0.rstmgr_reset/latest

Test location /workspace/coverage/default/0.rstmgr_smoke.34143202
Short name T209
Test name
Test status
Simulation time 198230851 ps
CPU time 1.4 seconds
Started Jun 25 05:37:51 PM PDT 24
Finished Jun 25 05:37:54 PM PDT 24
Peak memory 200224 kb
Host smart-3e3efb15-c655-4c7d-bde5-7fdfd113dfde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34143202 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_smoke.34143202
Directory /workspace/0.rstmgr_smoke/latest

Test location /workspace/coverage/default/0.rstmgr_stress_all.3079670028
Short name T260
Test name
Test status
Simulation time 4341266902 ps
CPU time 20.51 seconds
Started Jun 25 05:37:49 PM PDT 24
Finished Jun 25 05:38:12 PM PDT 24
Peak memory 200380 kb
Host smart-a11d7e93-cfe2-41c3-9361-9a7ba9d0d883
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079670028 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_stress_all.3079670028
Directory /workspace/0.rstmgr_stress_all/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst_reset_race.3450548598
Short name T247
Test name
Test status
Simulation time 158162336 ps
CPU time 1.3 seconds
Started Jun 25 05:37:49 PM PDT 24
Finished Jun 25 05:37:51 PM PDT 24
Peak memory 200268 kb
Host smart-c55a9e3e-68c1-45f3-9a1b-1ea70ef5dc16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3450548598 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst_reset_race.3450548598
Directory /workspace/0.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/1.rstmgr_alert_test.15429577
Short name T496
Test name
Test status
Simulation time 78317942 ps
CPU time 0.82 seconds
Started Jun 25 05:38:00 PM PDT 24
Finished Jun 25 05:38:03 PM PDT 24
Peak memory 199860 kb
Host smart-bae9d38a-8d51-4cff-b08b-95ba719490fa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15429577 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_alert_test.15429577
Directory /workspace/1.rstmgr_alert_test/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_cnsty.39748918
Short name T364
Test name
Test status
Simulation time 1228546111 ps
CPU time 5.38 seconds
Started Jun 25 05:37:50 PM PDT 24
Finished Jun 25 05:37:58 PM PDT 24
Peak memory 216708 kb
Host smart-c8111a11-2479-4e9a-bd5f-34bc3e8307fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39748918 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_cnsty.39748918
Directory /workspace/1.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_shadow_attack.2508749754
Short name T310
Test name
Test status
Simulation time 244860833 ps
CPU time 1.1 seconds
Started Jun 25 05:37:47 PM PDT 24
Finished Jun 25 05:37:49 PM PDT 24
Peak memory 217456 kb
Host smart-79339eb0-7b63-41a2-89fd-099ccfbc60f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2508749754 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_shadow_attack.2508749754
Directory /workspace/1.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/1.rstmgr_por_stretcher.4283388068
Short name T509
Test name
Test status
Simulation time 136357873 ps
CPU time 0.85 seconds
Started Jun 25 05:37:50 PM PDT 24
Finished Jun 25 05:37:53 PM PDT 24
Peak memory 199904 kb
Host smart-2a10da5d-1d01-4eb0-87a5-785a6ec7cd2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4283388068 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_por_stretcher.4283388068
Directory /workspace/1.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/1.rstmgr_reset.1914609317
Short name T474
Test name
Test status
Simulation time 1886179845 ps
CPU time 7.08 seconds
Started Jun 25 05:37:47 PM PDT 24
Finished Jun 25 05:37:55 PM PDT 24
Peak memory 200272 kb
Host smart-4993c5d3-280c-4961-9b98-d279a7748ec1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1914609317 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_reset.1914609317
Directory /workspace/1.rstmgr_reset/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm.1107673980
Short name T66
Test name
Test status
Simulation time 9022648585 ps
CPU time 14.18 seconds
Started Jun 25 05:37:55 PM PDT 24
Finished Jun 25 05:38:11 PM PDT 24
Peak memory 217100 kb
Host smart-64c6b0cb-7678-4269-9f1e-36b2e3bde6e8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107673980 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm.1107673980
Directory /workspace/1.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm_scan_intersig_mubi.1526691265
Short name T147
Test name
Test status
Simulation time 154150413 ps
CPU time 1.22 seconds
Started Jun 25 05:37:47 PM PDT 24
Finished Jun 25 05:37:50 PM PDT 24
Peak memory 199980 kb
Host smart-5ba1a795-1293-4fca-b5aa-6d2a72118a0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1526691265 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm_scan_intersig_mubi.1526691265
Directory /workspace/1.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/1.rstmgr_smoke.3100172007
Short name T359
Test name
Test status
Simulation time 254731224 ps
CPU time 1.41 seconds
Started Jun 25 05:37:49 PM PDT 24
Finished Jun 25 05:37:53 PM PDT 24
Peak memory 200268 kb
Host smart-452e563d-44c2-495f-a12f-fcb01095b573
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3100172007 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_smoke.3100172007
Directory /workspace/1.rstmgr_smoke/latest

Test location /workspace/coverage/default/1.rstmgr_stress_all.3945456330
Short name T397
Test name
Test status
Simulation time 7305671401 ps
CPU time 24.71 seconds
Started Jun 25 05:38:00 PM PDT 24
Finished Jun 25 05:38:27 PM PDT 24
Peak memory 200420 kb
Host smart-60dd2a4e-01e7-4fb4-9610-751225d62938
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945456330 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_stress_all.3945456330
Directory /workspace/1.rstmgr_stress_all/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst.2247923697
Short name T347
Test name
Test status
Simulation time 118984948 ps
CPU time 1.51 seconds
Started Jun 25 05:37:49 PM PDT 24
Finished Jun 25 05:37:53 PM PDT 24
Peak memory 200332 kb
Host smart-304cebed-d739-467f-b0d8-3d5de0a30aab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2247923697 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst.2247923697
Directory /workspace/1.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst_reset_race.2716984041
Short name T384
Test name
Test status
Simulation time 118746574 ps
CPU time 1.07 seconds
Started Jun 25 05:37:47 PM PDT 24
Finished Jun 25 05:37:50 PM PDT 24
Peak memory 200012 kb
Host smart-397f636c-f1e2-48e6-b24e-103f225dead5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2716984041 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst_reset_race.2716984041
Directory /workspace/1.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/10.rstmgr_alert_test.1706386325
Short name T487
Test name
Test status
Simulation time 72862975 ps
CPU time 0.78 seconds
Started Jun 25 05:38:13 PM PDT 24
Finished Jun 25 05:38:15 PM PDT 24
Peak memory 199892 kb
Host smart-8895618a-046b-42f1-9aff-9d8e44f0cd2b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706386325 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_alert_test.1706386325
Directory /workspace/10.rstmgr_alert_test/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_shadow_attack.2705734242
Short name T450
Test name
Test status
Simulation time 244619275 ps
CPU time 1.08 seconds
Started Jun 25 05:38:12 PM PDT 24
Finished Jun 25 05:38:14 PM PDT 24
Peak memory 217388 kb
Host smart-f31c7e1b-9b8a-4dbe-8e48-af89f484112a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2705734242 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_shadow_attack.2705734242
Directory /workspace/10.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/10.rstmgr_reset.2655956431
Short name T144
Test name
Test status
Simulation time 1474674491 ps
CPU time 5.53 seconds
Started Jun 25 05:38:13 PM PDT 24
Finished Jun 25 05:38:20 PM PDT 24
Peak memory 200344 kb
Host smart-f8bb104f-f9b7-4bbe-b18e-2b0f7c6d9502
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2655956431 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_reset.2655956431
Directory /workspace/10.rstmgr_reset/latest

Test location /workspace/coverage/default/10.rstmgr_sec_cm_scan_intersig_mubi.3280338541
Short name T482
Test name
Test status
Simulation time 144608087 ps
CPU time 1.21 seconds
Started Jun 25 05:38:15 PM PDT 24
Finished Jun 25 05:38:18 PM PDT 24
Peak memory 200088 kb
Host smart-608feaeb-2bf3-4530-8e3b-1696d6951b35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3280338541 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sec_cm_scan_intersig_mubi.3280338541
Directory /workspace/10.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/10.rstmgr_smoke.4008492053
Short name T519
Test name
Test status
Simulation time 118563536 ps
CPU time 1.26 seconds
Started Jun 25 05:38:13 PM PDT 24
Finished Jun 25 05:38:15 PM PDT 24
Peak memory 200276 kb
Host smart-e6524d00-81f8-4f7f-8666-9d139ba84fe6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4008492053 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_smoke.4008492053
Directory /workspace/10.rstmgr_smoke/latest

Test location /workspace/coverage/default/10.rstmgr_stress_all.819626872
Short name T268
Test name
Test status
Simulation time 6059458596 ps
CPU time 26.62 seconds
Started Jun 25 05:38:13 PM PDT 24
Finished Jun 25 05:38:41 PM PDT 24
Peak memory 210424 kb
Host smart-6a7aeab5-d1aa-408d-ae9d-48749f4c35c1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=819626872 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_stress_all.819626872
Directory /workspace/10.rstmgr_stress_all/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst.3421761193
Short name T153
Test name
Test status
Simulation time 132078062 ps
CPU time 1.81 seconds
Started Jun 25 05:38:15 PM PDT 24
Finished Jun 25 05:38:18 PM PDT 24
Peak memory 200000 kb
Host smart-9f0d1a34-0aaa-42ad-b1a2-29ada9a9c260
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3421761193 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst.3421761193
Directory /workspace/10.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst_reset_race.2344217358
Short name T506
Test name
Test status
Simulation time 102571568 ps
CPU time 0.96 seconds
Started Jun 25 05:38:15 PM PDT 24
Finished Jun 25 05:38:17 PM PDT 24
Peak memory 200108 kb
Host smart-a3368b56-d50c-4e19-9db3-5a760c8dff68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2344217358 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst_reset_race.2344217358
Directory /workspace/10.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/11.rstmgr_alert_test.3420084542
Short name T499
Test name
Test status
Simulation time 74658101 ps
CPU time 0.85 seconds
Started Jun 25 05:38:15 PM PDT 24
Finished Jun 25 05:38:17 PM PDT 24
Peak memory 200120 kb
Host smart-ea493a17-6bf6-4f23-9cea-c2f6f702564c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420084542 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_alert_test.3420084542
Directory /workspace/11.rstmgr_alert_test/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_cnsty.561726132
Short name T41
Test name
Test status
Simulation time 1896920175 ps
CPU time 7.02 seconds
Started Jun 25 05:38:17 PM PDT 24
Finished Jun 25 05:38:25 PM PDT 24
Peak memory 217684 kb
Host smart-187d7e6f-59d3-4287-9d04-1a4f19c72f9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=561726132 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_cnsty.561726132
Directory /workspace/11.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_shadow_attack.1225635214
Short name T541
Test name
Test status
Simulation time 244453617 ps
CPU time 1.13 seconds
Started Jun 25 05:38:22 PM PDT 24
Finished Jun 25 05:38:25 PM PDT 24
Peak memory 217456 kb
Host smart-4b945236-d47d-4e75-81ae-db139f4fbf86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1225635214 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_shadow_attack.1225635214
Directory /workspace/11.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/11.rstmgr_por_stretcher.1529121799
Short name T14
Test name
Test status
Simulation time 213030470 ps
CPU time 0.95 seconds
Started Jun 25 05:38:14 PM PDT 24
Finished Jun 25 05:38:16 PM PDT 24
Peak memory 199820 kb
Host smart-e8bf5118-0c83-46d9-bcec-73be5a0e27ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1529121799 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_por_stretcher.1529121799
Directory /workspace/11.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/11.rstmgr_reset.3255777116
Short name T341
Test name
Test status
Simulation time 1366710449 ps
CPU time 5.3 seconds
Started Jun 25 05:38:16 PM PDT 24
Finished Jun 25 05:38:22 PM PDT 24
Peak memory 200204 kb
Host smart-10226434-623e-4c5f-a0a3-b716f7336a41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3255777116 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_reset.3255777116
Directory /workspace/11.rstmgr_reset/latest

Test location /workspace/coverage/default/11.rstmgr_sec_cm_scan_intersig_mubi.1098411178
Short name T449
Test name
Test status
Simulation time 103820820 ps
CPU time 1.03 seconds
Started Jun 25 05:38:15 PM PDT 24
Finished Jun 25 05:38:17 PM PDT 24
Peak memory 200072 kb
Host smart-4d26f82b-10f3-44ec-9490-f8cf10b0c9e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1098411178 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sec_cm_scan_intersig_mubi.1098411178
Directory /workspace/11.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/11.rstmgr_smoke.462073297
Short name T358
Test name
Test status
Simulation time 188077550 ps
CPU time 1.41 seconds
Started Jun 25 05:38:16 PM PDT 24
Finished Jun 25 05:38:19 PM PDT 24
Peak memory 200276 kb
Host smart-27d3fa91-1276-451a-86fe-08bd8635496e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=462073297 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_smoke.462073297
Directory /workspace/11.rstmgr_smoke/latest

Test location /workspace/coverage/default/11.rstmgr_stress_all.1291500657
Short name T216
Test name
Test status
Simulation time 8130837930 ps
CPU time 29.92 seconds
Started Jun 25 05:38:14 PM PDT 24
Finished Jun 25 05:38:45 PM PDT 24
Peak memory 208608 kb
Host smart-c6a7b9bc-a713-4cda-8533-fa29ae7c3391
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1291500657 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_stress_all.1291500657
Directory /workspace/11.rstmgr_stress_all/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst.327246010
Short name T210
Test name
Test status
Simulation time 118107868 ps
CPU time 1.46 seconds
Started Jun 25 05:38:15 PM PDT 24
Finished Jun 25 05:38:18 PM PDT 24
Peak memory 200084 kb
Host smart-5c650a38-c231-4171-bc20-fbc07462b738
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=327246010 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst.327246010
Directory /workspace/11.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst_reset_race.1543915869
Short name T488
Test name
Test status
Simulation time 134565848 ps
CPU time 1.04 seconds
Started Jun 25 05:38:23 PM PDT 24
Finished Jun 25 05:38:26 PM PDT 24
Peak memory 200080 kb
Host smart-a9f8304f-6d50-4989-9a0f-ee607d380733
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1543915869 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst_reset_race.1543915869
Directory /workspace/11.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/12.rstmgr_alert_test.2828865050
Short name T350
Test name
Test status
Simulation time 67328856 ps
CPU time 0.82 seconds
Started Jun 25 05:38:21 PM PDT 24
Finished Jun 25 05:38:23 PM PDT 24
Peak memory 199820 kb
Host smart-3bd8c061-55fe-4495-94ab-aaf206d81c9a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828865050 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_alert_test.2828865050
Directory /workspace/12.rstmgr_alert_test/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_cnsty.1279939682
Short name T514
Test name
Test status
Simulation time 2177663881 ps
CPU time 7.88 seconds
Started Jun 25 05:38:17 PM PDT 24
Finished Jun 25 05:38:26 PM PDT 24
Peak memory 229884 kb
Host smart-32fb67f1-b5ea-429c-9752-57dc29f17bfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1279939682 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_cnsty.1279939682
Directory /workspace/12.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_shadow_attack.801895722
Short name T71
Test name
Test status
Simulation time 244572715 ps
CPU time 1.18 seconds
Started Jun 25 05:38:23 PM PDT 24
Finished Jun 25 05:38:26 PM PDT 24
Peak memory 217448 kb
Host smart-75804a19-f999-4eb5-853f-05b1f081bf2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=801895722 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_shadow_attack.801895722
Directory /workspace/12.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/12.rstmgr_por_stretcher.3453116800
Short name T165
Test name
Test status
Simulation time 145994110 ps
CPU time 0.82 seconds
Started Jun 25 05:38:22 PM PDT 24
Finished Jun 25 05:38:25 PM PDT 24
Peak memory 199888 kb
Host smart-60848fcd-53f3-461d-8423-ea47624c2058
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3453116800 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_por_stretcher.3453116800
Directory /workspace/12.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/12.rstmgr_reset.722187332
Short name T394
Test name
Test status
Simulation time 1929251045 ps
CPU time 7.71 seconds
Started Jun 25 05:38:13 PM PDT 24
Finished Jun 25 05:38:22 PM PDT 24
Peak memory 200340 kb
Host smart-68f8ddc6-3301-4e33-875f-84ed26bdd842
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=722187332 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_reset.722187332
Directory /workspace/12.rstmgr_reset/latest

Test location /workspace/coverage/default/12.rstmgr_sec_cm_scan_intersig_mubi.3018760463
Short name T436
Test name
Test status
Simulation time 157373109 ps
CPU time 1.19 seconds
Started Jun 25 05:38:16 PM PDT 24
Finished Jun 25 05:38:19 PM PDT 24
Peak memory 200084 kb
Host smart-e0551711-a96b-4597-9833-91f834754b9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3018760463 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sec_cm_scan_intersig_mubi.3018760463
Directory /workspace/12.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/12.rstmgr_smoke.1541504414
Short name T457
Test name
Test status
Simulation time 252075259 ps
CPU time 1.49 seconds
Started Jun 25 05:38:14 PM PDT 24
Finished Jun 25 05:38:17 PM PDT 24
Peak memory 200288 kb
Host smart-f981dd8e-ca47-4a46-9f86-03eb9e831731
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1541504414 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_smoke.1541504414
Directory /workspace/12.rstmgr_smoke/latest

Test location /workspace/coverage/default/12.rstmgr_stress_all.2272862456
Short name T518
Test name
Test status
Simulation time 1888668475 ps
CPU time 8.08 seconds
Started Jun 25 05:38:14 PM PDT 24
Finished Jun 25 05:38:23 PM PDT 24
Peak memory 200252 kb
Host smart-b1987d1b-71dc-47bb-a142-d698a795a3b4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272862456 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_stress_all.2272862456
Directory /workspace/12.rstmgr_stress_all/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst.2666351567
Short name T302
Test name
Test status
Simulation time 305579507 ps
CPU time 1.96 seconds
Started Jun 25 05:38:14 PM PDT 24
Finished Jun 25 05:38:17 PM PDT 24
Peak memory 208332 kb
Host smart-7dfe8d23-4dc4-4c55-8b48-94094f6d84b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2666351567 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst.2666351567
Directory /workspace/12.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst_reset_race.530596119
Short name T460
Test name
Test status
Simulation time 125280200 ps
CPU time 1.1 seconds
Started Jun 25 05:38:13 PM PDT 24
Finished Jun 25 05:38:15 PM PDT 24
Peak memory 200000 kb
Host smart-2710fbb3-fbca-48f6-8182-140b10396438
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=530596119 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst_reset_race.530596119
Directory /workspace/12.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/13.rstmgr_alert_test.4238869530
Short name T264
Test name
Test status
Simulation time 64949516 ps
CPU time 0.75 seconds
Started Jun 25 05:38:21 PM PDT 24
Finished Jun 25 05:38:23 PM PDT 24
Peak memory 199892 kb
Host smart-361aa1dc-039c-4842-8dff-dcea345ffacf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238869530 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_alert_test.4238869530
Directory /workspace/13.rstmgr_alert_test/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_cnsty.3742133795
Short name T325
Test name
Test status
Simulation time 1225837068 ps
CPU time 6.04 seconds
Started Jun 25 05:38:22 PM PDT 24
Finished Jun 25 05:38:30 PM PDT 24
Peak memory 216716 kb
Host smart-34cd261c-1593-4d91-8a12-d6babbbd8c67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3742133795 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_cnsty.3742133795
Directory /workspace/13.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_shadow_attack.794909624
Short name T434
Test name
Test status
Simulation time 244277525 ps
CPU time 1.1 seconds
Started Jun 25 05:38:27 PM PDT 24
Finished Jun 25 05:38:29 PM PDT 24
Peak memory 217436 kb
Host smart-54f128cf-c1e6-4b2f-8351-67d3dd6bcef8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=794909624 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_shadow_attack.794909624
Directory /workspace/13.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/13.rstmgr_por_stretcher.4132440770
Short name T16
Test name
Test status
Simulation time 84108961 ps
CPU time 0.8 seconds
Started Jun 25 05:38:23 PM PDT 24
Finished Jun 25 05:38:26 PM PDT 24
Peak memory 199872 kb
Host smart-781c9951-1d93-416b-8aca-68bfe2f72d7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4132440770 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_por_stretcher.4132440770
Directory /workspace/13.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/13.rstmgr_reset.3824905206
Short name T413
Test name
Test status
Simulation time 1066660873 ps
CPU time 5.43 seconds
Started Jun 25 05:38:23 PM PDT 24
Finished Jun 25 05:38:30 PM PDT 24
Peak memory 200312 kb
Host smart-f28b9473-5ef8-4abb-bd2f-2c47da13e929
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3824905206 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_reset.3824905206
Directory /workspace/13.rstmgr_reset/latest

Test location /workspace/coverage/default/13.rstmgr_sec_cm_scan_intersig_mubi.1338689495
Short name T343
Test name
Test status
Simulation time 156992894 ps
CPU time 1.14 seconds
Started Jun 25 05:38:24 PM PDT 24
Finished Jun 25 05:38:27 PM PDT 24
Peak memory 200104 kb
Host smart-55406b11-e363-4ac4-b968-604abb3aea23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1338689495 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sec_cm_scan_intersig_mubi.1338689495
Directory /workspace/13.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/13.rstmgr_smoke.777959058
Short name T294
Test name
Test status
Simulation time 251160692 ps
CPU time 1.76 seconds
Started Jun 25 05:38:25 PM PDT 24
Finished Jun 25 05:38:28 PM PDT 24
Peak memory 200264 kb
Host smart-051d5048-8067-453b-8a16-cf095cdf7897
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=777959058 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_smoke.777959058
Directory /workspace/13.rstmgr_smoke/latest

Test location /workspace/coverage/default/13.rstmgr_stress_all.3324981524
Short name T446
Test name
Test status
Simulation time 153077644 ps
CPU time 1.09 seconds
Started Jun 25 05:38:25 PM PDT 24
Finished Jun 25 05:38:28 PM PDT 24
Peak memory 199868 kb
Host smart-83bf3b86-41d5-4228-997e-75a7a98aa99e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3324981524 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_stress_all.3324981524
Directory /workspace/13.rstmgr_stress_all/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst.3143736245
Short name T255
Test name
Test status
Simulation time 126736834 ps
CPU time 1.56 seconds
Started Jun 25 05:38:20 PM PDT 24
Finished Jun 25 05:38:23 PM PDT 24
Peak memory 200000 kb
Host smart-331e044e-beb9-4a12-9e6d-e801e71b8c26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3143736245 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst.3143736245
Directory /workspace/13.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst_reset_race.2880403087
Short name T309
Test name
Test status
Simulation time 100737161 ps
CPU time 0.99 seconds
Started Jun 25 05:38:21 PM PDT 24
Finished Jun 25 05:38:24 PM PDT 24
Peak memory 200004 kb
Host smart-737d76e6-465d-4a2a-aa3c-2276793867b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2880403087 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst_reset_race.2880403087
Directory /workspace/13.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/14.rstmgr_alert_test.3615147871
Short name T438
Test name
Test status
Simulation time 74949653 ps
CPU time 0.82 seconds
Started Jun 25 05:38:24 PM PDT 24
Finished Jun 25 05:38:27 PM PDT 24
Peak memory 199884 kb
Host smart-d7174723-62c5-4705-87fb-d3e0a02ad718
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615147871 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_alert_test.3615147871
Directory /workspace/14.rstmgr_alert_test/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_cnsty.1555957464
Short name T296
Test name
Test status
Simulation time 2170288961 ps
CPU time 8.45 seconds
Started Jun 25 05:38:23 PM PDT 24
Finished Jun 25 05:38:33 PM PDT 24
Peak memory 229880 kb
Host smart-675a4124-0870-4669-bafc-60479299eb70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1555957464 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_cnsty.1555957464
Directory /workspace/14.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_shadow_attack.951045010
Short name T439
Test name
Test status
Simulation time 245197581 ps
CPU time 1.04 seconds
Started Jun 25 05:38:25 PM PDT 24
Finished Jun 25 05:38:28 PM PDT 24
Peak memory 217448 kb
Host smart-0927241a-441a-48d9-8c0e-a7f90bba19cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=951045010 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_shadow_attack.951045010
Directory /workspace/14.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/14.rstmgr_por_stretcher.2237963773
Short name T348
Test name
Test status
Simulation time 186910899 ps
CPU time 0.9 seconds
Started Jun 25 05:38:20 PM PDT 24
Finished Jun 25 05:38:22 PM PDT 24
Peak memory 199908 kb
Host smart-9d68aebd-7ad3-4bfb-89c2-19bf2dc58e8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2237963773 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_por_stretcher.2237963773
Directory /workspace/14.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/14.rstmgr_reset.1387338461
Short name T118
Test name
Test status
Simulation time 1246073093 ps
CPU time 4.99 seconds
Started Jun 25 05:38:22 PM PDT 24
Finished Jun 25 05:38:29 PM PDT 24
Peak memory 200320 kb
Host smart-1677df40-60ad-4a88-96f9-0e1fb5255d00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1387338461 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_reset.1387338461
Directory /workspace/14.rstmgr_reset/latest

Test location /workspace/coverage/default/14.rstmgr_sec_cm_scan_intersig_mubi.3764064674
Short name T124
Test name
Test status
Simulation time 101325652 ps
CPU time 1.02 seconds
Started Jun 25 05:38:21 PM PDT 24
Finished Jun 25 05:38:24 PM PDT 24
Peak memory 200076 kb
Host smart-92fa9715-1ddd-4a36-a39f-f98d7915a12c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3764064674 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sec_cm_scan_intersig_mubi.3764064674
Directory /workspace/14.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/14.rstmgr_smoke.2770216932
Short name T265
Test name
Test status
Simulation time 204408314 ps
CPU time 1.5 seconds
Started Jun 25 05:38:22 PM PDT 24
Finished Jun 25 05:38:25 PM PDT 24
Peak memory 200256 kb
Host smart-f82ec952-e5b3-4cfa-b561-fdb554b41b4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2770216932 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_smoke.2770216932
Directory /workspace/14.rstmgr_smoke/latest

Test location /workspace/coverage/default/14.rstmgr_stress_all.3490529538
Short name T194
Test name
Test status
Simulation time 1673041949 ps
CPU time 7.71 seconds
Started Jun 25 05:38:24 PM PDT 24
Finished Jun 25 05:38:34 PM PDT 24
Peak memory 200360 kb
Host smart-ba23ce81-63b0-4153-bdb2-974371930e20
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490529538 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_stress_all.3490529538
Directory /workspace/14.rstmgr_stress_all/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst.4000927324
Short name T373
Test name
Test status
Simulation time 342815270 ps
CPU time 2.08 seconds
Started Jun 25 05:38:21 PM PDT 24
Finished Jun 25 05:38:24 PM PDT 24
Peak memory 199972 kb
Host smart-1fc974be-8bdd-418c-92fa-813a67764b62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4000927324 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst.4000927324
Directory /workspace/14.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst_reset_race.1796941114
Short name T475
Test name
Test status
Simulation time 95149813 ps
CPU time 0.9 seconds
Started Jun 25 05:38:20 PM PDT 24
Finished Jun 25 05:38:22 PM PDT 24
Peak memory 200088 kb
Host smart-c5503a62-5369-4ac1-a5ec-261830afd6fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1796941114 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst_reset_race.1796941114
Directory /workspace/14.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/15.rstmgr_alert_test.4220393037
Short name T152
Test name
Test status
Simulation time 66372257 ps
CPU time 0.77 seconds
Started Jun 25 05:38:22 PM PDT 24
Finished Jun 25 05:38:24 PM PDT 24
Peak memory 199872 kb
Host smart-3154f754-4c49-41e9-aca1-bb241494c57f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220393037 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_alert_test.4220393037
Directory /workspace/15.rstmgr_alert_test/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_cnsty.1608626986
Short name T33
Test name
Test status
Simulation time 1223202653 ps
CPU time 5.68 seconds
Started Jun 25 05:38:22 PM PDT 24
Finished Jun 25 05:38:29 PM PDT 24
Peak memory 221640 kb
Host smart-79f787d0-52c6-45ca-a310-d67fbd9ecdbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1608626986 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_cnsty.1608626986
Directory /workspace/15.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_shadow_attack.3091137341
Short name T69
Test name
Test status
Simulation time 243540377 ps
CPU time 1.1 seconds
Started Jun 25 05:38:21 PM PDT 24
Finished Jun 25 05:38:23 PM PDT 24
Peak memory 217356 kb
Host smart-b757c234-297d-4e4c-b0d7-ff747b19f8ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3091137341 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_shadow_attack.3091137341
Directory /workspace/15.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/15.rstmgr_por_stretcher.657592943
Short name T437
Test name
Test status
Simulation time 137372401 ps
CPU time 0.85 seconds
Started Jun 25 05:38:23 PM PDT 24
Finished Jun 25 05:38:26 PM PDT 24
Peak memory 199888 kb
Host smart-b8d5310b-7836-4b99-8f12-7e69e282e0e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=657592943 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_por_stretcher.657592943
Directory /workspace/15.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/15.rstmgr_reset.4002068042
Short name T12
Test name
Test status
Simulation time 717902424 ps
CPU time 4.08 seconds
Started Jun 25 05:38:22 PM PDT 24
Finished Jun 25 05:38:28 PM PDT 24
Peak memory 200340 kb
Host smart-860038ac-c349-4c7a-96a0-c89e70377e47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4002068042 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_reset.4002068042
Directory /workspace/15.rstmgr_reset/latest

Test location /workspace/coverage/default/15.rstmgr_sec_cm_scan_intersig_mubi.1453938232
Short name T458
Test name
Test status
Simulation time 107957174 ps
CPU time 1.05 seconds
Started Jun 25 05:38:22 PM PDT 24
Finished Jun 25 05:38:25 PM PDT 24
Peak memory 200064 kb
Host smart-c300513b-cae6-4bea-bf13-36770a306b26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1453938232 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sec_cm_scan_intersig_mubi.1453938232
Directory /workspace/15.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/15.rstmgr_smoke.1500480510
Short name T346
Test name
Test status
Simulation time 122153469 ps
CPU time 1.22 seconds
Started Jun 25 05:38:20 PM PDT 24
Finished Jun 25 05:38:22 PM PDT 24
Peak memory 200260 kb
Host smart-40e2f021-55e3-42c5-b390-38552f5f16cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1500480510 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_smoke.1500480510
Directory /workspace/15.rstmgr_smoke/latest

Test location /workspace/coverage/default/15.rstmgr_stress_all.931439593
Short name T106
Test name
Test status
Simulation time 6179037630 ps
CPU time 28.96 seconds
Started Jun 25 05:38:22 PM PDT 24
Finished Jun 25 05:38:53 PM PDT 24
Peak memory 209620 kb
Host smart-bb49c80a-ca00-4f2e-a571-3932c5e09d71
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931439593 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_stress_all.931439593
Directory /workspace/15.rstmgr_stress_all/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst.385320100
Short name T353
Test name
Test status
Simulation time 342541995 ps
CPU time 2.25 seconds
Started Jun 25 05:38:21 PM PDT 24
Finished Jun 25 05:38:24 PM PDT 24
Peak memory 208196 kb
Host smart-88b443dc-c8fc-4711-b569-9730a9d7b7fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=385320100 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst.385320100
Directory /workspace/15.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst_reset_race.1893922285
Short name T208
Test name
Test status
Simulation time 172571105 ps
CPU time 1.45 seconds
Started Jun 25 05:38:22 PM PDT 24
Finished Jun 25 05:38:26 PM PDT 24
Peak memory 200332 kb
Host smart-629883bf-e87b-4d90-9621-87cbc64c08ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1893922285 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst_reset_race.1893922285
Directory /workspace/15.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/16.rstmgr_alert_test.385004501
Short name T367
Test name
Test status
Simulation time 62563611 ps
CPU time 0.78 seconds
Started Jun 25 05:38:26 PM PDT 24
Finished Jun 25 05:38:28 PM PDT 24
Peak memory 199796 kb
Host smart-8a01b346-e437-40d9-a75e-d73046205648
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385004501 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_alert_test.385004501
Directory /workspace/16.rstmgr_alert_test/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_cnsty.222571411
Short name T40
Test name
Test status
Simulation time 1890962111 ps
CPU time 7.41 seconds
Started Jun 25 05:38:20 PM PDT 24
Finished Jun 25 05:38:29 PM PDT 24
Peak memory 217716 kb
Host smart-7bab90d3-39fa-4d99-ab64-86ef576411f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=222571411 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_cnsty.222571411
Directory /workspace/16.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_shadow_attack.3178616853
Short name T522
Test name
Test status
Simulation time 244000173 ps
CPU time 1.07 seconds
Started Jun 25 05:38:21 PM PDT 24
Finished Jun 25 05:38:23 PM PDT 24
Peak memory 217428 kb
Host smart-7cb34123-41b6-4eaa-87ed-d49eeeffad5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3178616853 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_shadow_attack.3178616853
Directory /workspace/16.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/16.rstmgr_por_stretcher.2952510688
Short name T536
Test name
Test status
Simulation time 195701824 ps
CPU time 0.94 seconds
Started Jun 25 05:38:24 PM PDT 24
Finished Jun 25 05:38:27 PM PDT 24
Peak memory 199888 kb
Host smart-89b1fdad-c326-4a22-b4d9-00b0d5220299
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2952510688 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_por_stretcher.2952510688
Directory /workspace/16.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/16.rstmgr_reset.3023418423
Short name T261
Test name
Test status
Simulation time 1583454265 ps
CPU time 6.53 seconds
Started Jun 25 05:38:27 PM PDT 24
Finished Jun 25 05:38:35 PM PDT 24
Peak memory 200328 kb
Host smart-12a11168-ea6d-475c-968e-6b6e2d80b322
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3023418423 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_reset.3023418423
Directory /workspace/16.rstmgr_reset/latest

Test location /workspace/coverage/default/16.rstmgr_sec_cm_scan_intersig_mubi.1557782201
Short name T270
Test name
Test status
Simulation time 113620863 ps
CPU time 1.08 seconds
Started Jun 25 05:38:23 PM PDT 24
Finished Jun 25 05:38:25 PM PDT 24
Peak memory 200084 kb
Host smart-1a05ed43-03ed-417d-b701-823cc2ee3033
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1557782201 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sec_cm_scan_intersig_mubi.1557782201
Directory /workspace/16.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/16.rstmgr_smoke.475859040
Short name T204
Test name
Test status
Simulation time 184242886 ps
CPU time 1.37 seconds
Started Jun 25 05:38:26 PM PDT 24
Finished Jun 25 05:38:29 PM PDT 24
Peak memory 200196 kb
Host smart-a3f39402-b111-439e-9ae4-b53769311aa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=475859040 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_smoke.475859040
Directory /workspace/16.rstmgr_smoke/latest

Test location /workspace/coverage/default/16.rstmgr_stress_all.1180521868
Short name T190
Test name
Test status
Simulation time 5778247505 ps
CPU time 21.05 seconds
Started Jun 25 05:38:24 PM PDT 24
Finished Jun 25 05:38:48 PM PDT 24
Peak memory 208592 kb
Host smart-c16e71b5-7072-434a-8dcc-24ac82ce99d3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180521868 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_stress_all.1180521868
Directory /workspace/16.rstmgr_stress_all/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst.2312977801
Short name T501
Test name
Test status
Simulation time 461656977 ps
CPU time 2.73 seconds
Started Jun 25 05:38:26 PM PDT 24
Finished Jun 25 05:38:30 PM PDT 24
Peak memory 200068 kb
Host smart-f716e466-dc11-4dba-b647-572193815ff6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2312977801 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst.2312977801
Directory /workspace/16.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst_reset_race.3295744799
Short name T127
Test name
Test status
Simulation time 97147340 ps
CPU time 0.93 seconds
Started Jun 25 05:38:20 PM PDT 24
Finished Jun 25 05:38:22 PM PDT 24
Peak memory 200084 kb
Host smart-a0c374a4-278c-418c-9efd-526bc676b107
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3295744799 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst_reset_race.3295744799
Directory /workspace/16.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/17.rstmgr_alert_test.806505521
Short name T217
Test name
Test status
Simulation time 75665569 ps
CPU time 0.9 seconds
Started Jun 25 05:38:32 PM PDT 24
Finished Jun 25 05:38:35 PM PDT 24
Peak memory 199768 kb
Host smart-7ef832fc-8361-4e1a-9087-6a0f45851ec3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806505521 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_alert_test.806505521
Directory /workspace/17.rstmgr_alert_test/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_shadow_attack.3944961718
Short name T239
Test name
Test status
Simulation time 244070814 ps
CPU time 1.11 seconds
Started Jun 25 05:38:28 PM PDT 24
Finished Jun 25 05:38:31 PM PDT 24
Peak memory 217432 kb
Host smart-d04fad3a-f7f6-418f-90c1-4b9b3068f927
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3944961718 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_shadow_attack.3944961718
Directory /workspace/17.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/17.rstmgr_por_stretcher.1238102092
Short name T403
Test name
Test status
Simulation time 137982424 ps
CPU time 0.84 seconds
Started Jun 25 05:38:22 PM PDT 24
Finished Jun 25 05:38:25 PM PDT 24
Peak memory 199892 kb
Host smart-6221d13c-c08d-4a3f-84c8-121529016eae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1238102092 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_por_stretcher.1238102092
Directory /workspace/17.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/17.rstmgr_reset.1969754176
Short name T440
Test name
Test status
Simulation time 648333422 ps
CPU time 3.92 seconds
Started Jun 25 05:38:28 PM PDT 24
Finished Jun 25 05:38:33 PM PDT 24
Peak memory 200384 kb
Host smart-9002a46c-7f11-4dc4-bb14-a525d636ad66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1969754176 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_reset.1969754176
Directory /workspace/17.rstmgr_reset/latest

Test location /workspace/coverage/default/17.rstmgr_sec_cm_scan_intersig_mubi.2790792986
Short name T379
Test name
Test status
Simulation time 101939429 ps
CPU time 1.08 seconds
Started Jun 25 05:38:30 PM PDT 24
Finished Jun 25 05:38:33 PM PDT 24
Peak memory 200016 kb
Host smart-2872c478-ae7f-4530-be0d-10810a78c16a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2790792986 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sec_cm_scan_intersig_mubi.2790792986
Directory /workspace/17.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/17.rstmgr_smoke.3548982207
Short name T521
Test name
Test status
Simulation time 197749251 ps
CPU time 1.41 seconds
Started Jun 25 05:38:24 PM PDT 24
Finished Jun 25 05:38:27 PM PDT 24
Peak memory 200280 kb
Host smart-1af7a87a-f5cb-4462-b5b9-a4149f8213a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3548982207 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_smoke.3548982207
Directory /workspace/17.rstmgr_smoke/latest

Test location /workspace/coverage/default/17.rstmgr_stress_all.2952658797
Short name T330
Test name
Test status
Simulation time 7283469701 ps
CPU time 26.43 seconds
Started Jun 25 05:38:28 PM PDT 24
Finished Jun 25 05:38:56 PM PDT 24
Peak memory 200388 kb
Host smart-90ede011-77e8-4c5e-bf2a-ad8bdb9ef83d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952658797 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_stress_all.2952658797
Directory /workspace/17.rstmgr_stress_all/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst.2170671269
Short name T251
Test name
Test status
Simulation time 266157945 ps
CPU time 1.82 seconds
Started Jun 25 05:38:31 PM PDT 24
Finished Jun 25 05:38:35 PM PDT 24
Peak memory 200064 kb
Host smart-f8e52478-dd53-45c9-8302-ae058e4dc3b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2170671269 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst.2170671269
Directory /workspace/17.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst_reset_race.79575142
Short name T67
Test name
Test status
Simulation time 96744818 ps
CPU time 0.96 seconds
Started Jun 25 05:38:29 PM PDT 24
Finished Jun 25 05:38:32 PM PDT 24
Peak memory 200112 kb
Host smart-a9668e45-779e-49e9-8eed-b1f755f7f91f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=79575142 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst_reset_race.79575142
Directory /workspace/17.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/18.rstmgr_alert_test.1765388509
Short name T304
Test name
Test status
Simulation time 71450241 ps
CPU time 0.77 seconds
Started Jun 25 05:38:30 PM PDT 24
Finished Jun 25 05:38:33 PM PDT 24
Peak memory 199868 kb
Host smart-69f69663-b5eb-4fc1-9a34-03029effac2c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765388509 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_alert_test.1765388509
Directory /workspace/18.rstmgr_alert_test/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_cnsty.4260009985
Short name T476
Test name
Test status
Simulation time 1220087875 ps
CPU time 5.87 seconds
Started Jun 25 05:38:27 PM PDT 24
Finished Jun 25 05:38:35 PM PDT 24
Peak memory 221584 kb
Host smart-71b9b3a2-ee6e-4faa-926e-e05f396cd549
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4260009985 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_cnsty.4260009985
Directory /workspace/18.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_shadow_attack.231856937
Short name T469
Test name
Test status
Simulation time 244567225 ps
CPU time 1.04 seconds
Started Jun 25 05:38:31 PM PDT 24
Finished Jun 25 05:38:34 PM PDT 24
Peak memory 217468 kb
Host smart-4ad97197-c587-4152-9680-4c221ade3752
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=231856937 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_shadow_attack.231856937
Directory /workspace/18.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/18.rstmgr_por_stretcher.3644177860
Short name T189
Test name
Test status
Simulation time 145524575 ps
CPU time 0.89 seconds
Started Jun 25 05:38:31 PM PDT 24
Finished Jun 25 05:38:34 PM PDT 24
Peak memory 199812 kb
Host smart-1eea9e38-95bf-4f55-9f62-fc717136c39e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3644177860 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_por_stretcher.3644177860
Directory /workspace/18.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/18.rstmgr_reset.2797294159
Short name T452
Test name
Test status
Simulation time 991988097 ps
CPU time 5.29 seconds
Started Jun 25 05:38:28 PM PDT 24
Finished Jun 25 05:38:35 PM PDT 24
Peak memory 200336 kb
Host smart-4986f2bd-4af0-454f-9160-674dd13c1e80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2797294159 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_reset.2797294159
Directory /workspace/18.rstmgr_reset/latest

Test location /workspace/coverage/default/18.rstmgr_sec_cm_scan_intersig_mubi.3150342727
Short name T4
Test name
Test status
Simulation time 189863645 ps
CPU time 1.19 seconds
Started Jun 25 05:38:33 PM PDT 24
Finished Jun 25 05:38:36 PM PDT 24
Peak memory 200076 kb
Host smart-579a6c8f-5dc2-46e0-915b-332e495339bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3150342727 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sec_cm_scan_intersig_mubi.3150342727
Directory /workspace/18.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/18.rstmgr_smoke.1453436116
Short name T431
Test name
Test status
Simulation time 252816936 ps
CPU time 1.57 seconds
Started Jun 25 05:38:28 PM PDT 24
Finished Jun 25 05:38:31 PM PDT 24
Peak memory 200196 kb
Host smart-c0dbf571-03d2-4ab9-88d1-2d66c13fcc91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1453436116 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_smoke.1453436116
Directory /workspace/18.rstmgr_smoke/latest

Test location /workspace/coverage/default/18.rstmgr_stress_all.4273417398
Short name T383
Test name
Test status
Simulation time 4638690819 ps
CPU time 20.9 seconds
Started Jun 25 05:38:31 PM PDT 24
Finished Jun 25 05:38:54 PM PDT 24
Peak memory 208604 kb
Host smart-75c1acc4-d1e3-4ffb-ac7a-0d3675f7fa59
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273417398 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_stress_all.4273417398
Directory /workspace/18.rstmgr_stress_all/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst.1594793367
Short name T540
Test name
Test status
Simulation time 144732489 ps
CPU time 1.77 seconds
Started Jun 25 05:38:31 PM PDT 24
Finished Jun 25 05:38:35 PM PDT 24
Peak memory 200080 kb
Host smart-6b7148df-96ce-430b-9b7f-4382fb49a8a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1594793367 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst.1594793367
Directory /workspace/18.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst_reset_race.4156568673
Short name T22
Test name
Test status
Simulation time 230444760 ps
CPU time 1.41 seconds
Started Jun 25 05:38:30 PM PDT 24
Finished Jun 25 05:38:34 PM PDT 24
Peak memory 200284 kb
Host smart-d513158c-3a77-480a-a99e-1249e6400a75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4156568673 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst_reset_race.4156568673
Directory /workspace/18.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/19.rstmgr_alert_test.2775608128
Short name T185
Test name
Test status
Simulation time 72909441 ps
CPU time 0.87 seconds
Started Jun 25 05:38:30 PM PDT 24
Finished Jun 25 05:38:34 PM PDT 24
Peak memory 199868 kb
Host smart-c7b85917-7b3b-4cad-9800-d2e4e85ae6f7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775608128 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_alert_test.2775608128
Directory /workspace/19.rstmgr_alert_test/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_cnsty.1194694736
Short name T409
Test name
Test status
Simulation time 1890136199 ps
CPU time 7.82 seconds
Started Jun 25 05:38:30 PM PDT 24
Finished Jun 25 05:38:40 PM PDT 24
Peak memory 217500 kb
Host smart-24377526-acb0-41e1-afed-90b8a7e85614
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1194694736 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_cnsty.1194694736
Directory /workspace/19.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_shadow_attack.11729866
Short name T24
Test name
Test status
Simulation time 244572895 ps
CPU time 1.13 seconds
Started Jun 25 05:38:33 PM PDT 24
Finished Jun 25 05:38:36 PM PDT 24
Peak memory 217424 kb
Host smart-cd8d8252-7cc0-4ac0-a9cd-f0216526f327
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=11729866 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_shadow_attack.11729866
Directory /workspace/19.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/19.rstmgr_por_stretcher.1600289811
Short name T254
Test name
Test status
Simulation time 139207125 ps
CPU time 0.82 seconds
Started Jun 25 05:38:30 PM PDT 24
Finished Jun 25 05:38:34 PM PDT 24
Peak memory 199788 kb
Host smart-408fd6e0-f1db-430c-8355-f65e3675961b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1600289811 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_por_stretcher.1600289811
Directory /workspace/19.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/19.rstmgr_reset.2971682143
Short name T287
Test name
Test status
Simulation time 1469843404 ps
CPU time 5.93 seconds
Started Jun 25 05:38:32 PM PDT 24
Finished Jun 25 05:38:40 PM PDT 24
Peak memory 200376 kb
Host smart-be7eec70-e256-4987-955e-92379448d0a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2971682143 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_reset.2971682143
Directory /workspace/19.rstmgr_reset/latest

Test location /workspace/coverage/default/19.rstmgr_sec_cm_scan_intersig_mubi.556666923
Short name T11
Test name
Test status
Simulation time 143613614 ps
CPU time 1.1 seconds
Started Jun 25 05:38:30 PM PDT 24
Finished Jun 25 05:38:34 PM PDT 24
Peak memory 200008 kb
Host smart-c725ef54-07a1-4759-ab93-7954c246c395
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=556666923 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sec_cm_scan_intersig_mubi.556666923
Directory /workspace/19.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/19.rstmgr_smoke.1033070135
Short name T421
Test name
Test status
Simulation time 190699535 ps
CPU time 1.44 seconds
Started Jun 25 05:38:32 PM PDT 24
Finished Jun 25 05:38:35 PM PDT 24
Peak memory 200276 kb
Host smart-aa37acaa-632c-48eb-be94-ec71136ed863
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1033070135 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_smoke.1033070135
Directory /workspace/19.rstmgr_smoke/latest

Test location /workspace/coverage/default/19.rstmgr_stress_all.1190695941
Short name T531
Test name
Test status
Simulation time 22267954819 ps
CPU time 77.31 seconds
Started Jun 25 05:38:30 PM PDT 24
Finished Jun 25 05:39:49 PM PDT 24
Peak memory 208580 kb
Host smart-7929f095-729d-41c8-a200-9f6166078dd9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190695941 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_stress_all.1190695941
Directory /workspace/19.rstmgr_stress_all/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst.4134013108
Short name T529
Test name
Test status
Simulation time 110577590 ps
CPU time 1.48 seconds
Started Jun 25 05:38:28 PM PDT 24
Finished Jun 25 05:38:30 PM PDT 24
Peak memory 200000 kb
Host smart-5dbeebf5-424e-4d80-bf54-54f2c12a5fe2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4134013108 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst.4134013108
Directory /workspace/19.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst_reset_race.257852683
Short name T298
Test name
Test status
Simulation time 79693824 ps
CPU time 0.83 seconds
Started Jun 25 05:38:27 PM PDT 24
Finished Jun 25 05:38:29 PM PDT 24
Peak memory 200080 kb
Host smart-7dacbc22-94d0-4e8c-9c61-eb17979436e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=257852683 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst_reset_race.257852683
Directory /workspace/19.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/2.rstmgr_alert_test.199417538
Short name T486
Test name
Test status
Simulation time 81912651 ps
CPU time 0.87 seconds
Started Jun 25 05:37:57 PM PDT 24
Finished Jun 25 05:38:00 PM PDT 24
Peak memory 199884 kb
Host smart-d58ee943-13ad-457d-84e1-145686ad361d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199417538 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_alert_test.199417538
Directory /workspace/2.rstmgr_alert_test/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_cnsty.4044042600
Short name T374
Test name
Test status
Simulation time 1216462944 ps
CPU time 5.91 seconds
Started Jun 25 05:37:54 PM PDT 24
Finished Jun 25 05:38:01 PM PDT 24
Peak memory 217712 kb
Host smart-4e863cbb-bcd1-4b56-b548-59721dba7e0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4044042600 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_cnsty.4044042600
Directory /workspace/2.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_shadow_attack.1442590646
Short name T173
Test name
Test status
Simulation time 244114087 ps
CPU time 1.16 seconds
Started Jun 25 05:37:57 PM PDT 24
Finished Jun 25 05:38:01 PM PDT 24
Peak memory 217420 kb
Host smart-7bc11c14-046b-4e47-a65c-4ee3fbad7d56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1442590646 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_shadow_attack.1442590646
Directory /workspace/2.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/2.rstmgr_por_stretcher.527893376
Short name T400
Test name
Test status
Simulation time 187448766 ps
CPU time 0.89 seconds
Started Jun 25 05:37:57 PM PDT 24
Finished Jun 25 05:38:01 PM PDT 24
Peak memory 199896 kb
Host smart-59a648c0-9ad7-49bd-8674-bdbee5aadfd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=527893376 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_por_stretcher.527893376
Directory /workspace/2.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/2.rstmgr_reset.1498506036
Short name T253
Test name
Test status
Simulation time 1678421405 ps
CPU time 6.82 seconds
Started Jun 25 05:37:59 PM PDT 24
Finished Jun 25 05:38:08 PM PDT 24
Peak memory 200184 kb
Host smart-c4c13604-4b9d-4e3a-a6de-3000d435e929
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1498506036 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_reset.1498506036
Directory /workspace/2.rstmgr_reset/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm.3662434393
Short name T62
Test name
Test status
Simulation time 16503456497 ps
CPU time 33.17 seconds
Started Jun 25 05:37:59 PM PDT 24
Finished Jun 25 05:38:35 PM PDT 24
Peak memory 218184 kb
Host smart-0ce52491-abed-4e97-aa3d-37842857d1a5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662434393 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm.3662434393
Directory /workspace/2.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm_scan_intersig_mubi.4069820671
Short name T191
Test name
Test status
Simulation time 142200767 ps
CPU time 1.15 seconds
Started Jun 25 05:37:57 PM PDT 24
Finished Jun 25 05:38:01 PM PDT 24
Peak memory 200068 kb
Host smart-b97aa157-0e61-4bda-afc8-b5a183d20004
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4069820671 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm_scan_intersig_mubi.4069820671
Directory /workspace/2.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/2.rstmgr_smoke.788198818
Short name T279
Test name
Test status
Simulation time 116784487 ps
CPU time 1.23 seconds
Started Jun 25 05:37:54 PM PDT 24
Finished Jun 25 05:37:56 PM PDT 24
Peak memory 200328 kb
Host smart-b576d99e-1d27-46dc-b97c-b44b26e88760
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=788198818 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_smoke.788198818
Directory /workspace/2.rstmgr_smoke/latest

Test location /workspace/coverage/default/2.rstmgr_stress_all.3129028115
Short name T99
Test name
Test status
Simulation time 3065308066 ps
CPU time 14.76 seconds
Started Jun 25 05:37:57 PM PDT 24
Finished Jun 25 05:38:14 PM PDT 24
Peak memory 210240 kb
Host smart-eb3515e1-2519-4b5b-a6b1-11d89de8af2d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129028115 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_stress_all.3129028115
Directory /workspace/2.rstmgr_stress_all/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst.1568240543
Short name T422
Test name
Test status
Simulation time 318657016 ps
CPU time 2.22 seconds
Started Jun 25 05:37:56 PM PDT 24
Finished Jun 25 05:37:59 PM PDT 24
Peak memory 200132 kb
Host smart-d908798d-905a-41c3-bdfd-b60bcb9068e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1568240543 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst.1568240543
Directory /workspace/2.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst_reset_race.603343074
Short name T263
Test name
Test status
Simulation time 116313993 ps
CPU time 1.05 seconds
Started Jun 25 05:37:57 PM PDT 24
Finished Jun 25 05:38:01 PM PDT 24
Peak memory 200084 kb
Host smart-663ded92-5945-4276-977c-5ce1ff356d29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=603343074 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst_reset_race.603343074
Directory /workspace/2.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/20.rstmgr_alert_test.303205859
Short name T211
Test name
Test status
Simulation time 63445461 ps
CPU time 0.79 seconds
Started Jun 25 05:38:29 PM PDT 24
Finished Jun 25 05:38:31 PM PDT 24
Peak memory 199860 kb
Host smart-1076287a-4a3d-4cd7-a883-5e9c75618ea1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303205859 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_alert_test.303205859
Directory /workspace/20.rstmgr_alert_test/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_cnsty.3898458072
Short name T544
Test name
Test status
Simulation time 1233288545 ps
CPU time 5.33 seconds
Started Jun 25 05:38:29 PM PDT 24
Finished Jun 25 05:38:37 PM PDT 24
Peak memory 221620 kb
Host smart-d2d08ebd-e0d5-4511-8b6f-2ef8c93e61af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3898458072 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_cnsty.3898458072
Directory /workspace/20.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_shadow_attack.610915217
Short name T523
Test name
Test status
Simulation time 243652138 ps
CPU time 1.07 seconds
Started Jun 25 05:38:29 PM PDT 24
Finished Jun 25 05:38:32 PM PDT 24
Peak memory 217340 kb
Host smart-27ba2bfd-1f4b-41cc-bb15-a0f21719ae15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=610915217 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_shadow_attack.610915217
Directory /workspace/20.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/20.rstmgr_por_stretcher.4111067440
Short name T532
Test name
Test status
Simulation time 99915735 ps
CPU time 0.81 seconds
Started Jun 25 05:38:28 PM PDT 24
Finished Jun 25 05:38:31 PM PDT 24
Peak memory 200116 kb
Host smart-7bfdb4b4-6b17-4702-a946-541e1882e32c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4111067440 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_por_stretcher.4111067440
Directory /workspace/20.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/20.rstmgr_reset.4158048011
Short name T134
Test name
Test status
Simulation time 1610080043 ps
CPU time 6.54 seconds
Started Jun 25 05:38:28 PM PDT 24
Finished Jun 25 05:38:36 PM PDT 24
Peak memory 200340 kb
Host smart-0d614f65-6dca-4488-b5bf-55107b9366c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4158048011 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_reset.4158048011
Directory /workspace/20.rstmgr_reset/latest

Test location /workspace/coverage/default/20.rstmgr_sec_cm_scan_intersig_mubi.3781598640
Short name T171
Test name
Test status
Simulation time 110157873 ps
CPU time 1.14 seconds
Started Jun 25 05:38:29 PM PDT 24
Finished Jun 25 05:38:31 PM PDT 24
Peak memory 200072 kb
Host smart-0c20e9b7-6da3-4bfd-a426-5a5d85bc1830
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3781598640 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sec_cm_scan_intersig_mubi.3781598640
Directory /workspace/20.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/20.rstmgr_smoke.1988454085
Short name T369
Test name
Test status
Simulation time 195114024 ps
CPU time 1.51 seconds
Started Jun 25 05:38:30 PM PDT 24
Finished Jun 25 05:38:34 PM PDT 24
Peak memory 200276 kb
Host smart-828e903d-0a2c-458c-a8fc-23262eb513b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1988454085 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_smoke.1988454085
Directory /workspace/20.rstmgr_smoke/latest

Test location /workspace/coverage/default/20.rstmgr_stress_all.1084224919
Short name T478
Test name
Test status
Simulation time 6141920301 ps
CPU time 23.65 seconds
Started Jun 25 05:38:32 PM PDT 24
Finished Jun 25 05:38:58 PM PDT 24
Peak memory 200296 kb
Host smart-ef9aeae8-b270-4f30-969b-e302c491392c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084224919 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_stress_all.1084224919
Directory /workspace/20.rstmgr_stress_all/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst.1377706943
Short name T479
Test name
Test status
Simulation time 453739335 ps
CPU time 2.32 seconds
Started Jun 25 05:38:29 PM PDT 24
Finished Jun 25 05:38:34 PM PDT 24
Peak memory 200064 kb
Host smart-5a39e709-daf9-42e4-89ca-e714228cee90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1377706943 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst.1377706943
Directory /workspace/20.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst_reset_race.3337704528
Short name T314
Test name
Test status
Simulation time 234231186 ps
CPU time 1.33 seconds
Started Jun 25 05:38:31 PM PDT 24
Finished Jun 25 05:38:35 PM PDT 24
Peak memory 199356 kb
Host smart-48e6d854-8083-4a03-9561-542177afda91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3337704528 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst_reset_race.3337704528
Directory /workspace/20.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/21.rstmgr_alert_test.1082418985
Short name T465
Test name
Test status
Simulation time 74199578 ps
CPU time 0.85 seconds
Started Jun 25 05:38:30 PM PDT 24
Finished Jun 25 05:38:33 PM PDT 24
Peak memory 199808 kb
Host smart-8f77a0d1-a724-4e7e-932a-4e07e4d16f6b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082418985 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_alert_test.1082418985
Directory /workspace/21.rstmgr_alert_test/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_cnsty.4122139078
Short name T271
Test name
Test status
Simulation time 1216413177 ps
CPU time 5.55 seconds
Started Jun 25 05:38:31 PM PDT 24
Finished Jun 25 05:38:39 PM PDT 24
Peak memory 216748 kb
Host smart-a4085d1f-9b2c-47a7-ac66-549509328530
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4122139078 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_cnsty.4122139078
Directory /workspace/21.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_shadow_attack.2988860152
Short name T195
Test name
Test status
Simulation time 244030865 ps
CPU time 1.12 seconds
Started Jun 25 05:38:31 PM PDT 24
Finished Jun 25 05:38:35 PM PDT 24
Peak memory 217460 kb
Host smart-504642d0-5c5f-4640-b8cb-73a7191bbc06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2988860152 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_shadow_attack.2988860152
Directory /workspace/21.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/21.rstmgr_por_stretcher.2824484411
Short name T170
Test name
Test status
Simulation time 198872106 ps
CPU time 0.94 seconds
Started Jun 25 05:38:32 PM PDT 24
Finished Jun 25 05:38:35 PM PDT 24
Peak memory 199900 kb
Host smart-d8f15945-1465-4ce7-83a7-f5c0db83c5ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2824484411 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_por_stretcher.2824484411
Directory /workspace/21.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/21.rstmgr_reset.2434808143
Short name T117
Test name
Test status
Simulation time 1449241834 ps
CPU time 6.17 seconds
Started Jun 25 05:38:32 PM PDT 24
Finished Jun 25 05:38:40 PM PDT 24
Peak memory 200340 kb
Host smart-2df9185d-8c2e-4d5f-9af9-e1ebaf303bb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2434808143 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_reset.2434808143
Directory /workspace/21.rstmgr_reset/latest

Test location /workspace/coverage/default/21.rstmgr_sec_cm_scan_intersig_mubi.3020802475
Short name T164
Test name
Test status
Simulation time 146624687 ps
CPU time 1.11 seconds
Started Jun 25 05:38:31 PM PDT 24
Finished Jun 25 05:38:34 PM PDT 24
Peak memory 200092 kb
Host smart-d1a3ba50-1f31-4795-9e05-6c5cd0ca2d8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3020802475 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sec_cm_scan_intersig_mubi.3020802475
Directory /workspace/21.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/21.rstmgr_smoke.3414925835
Short name T176
Test name
Test status
Simulation time 124066317 ps
CPU time 1.27 seconds
Started Jun 25 05:38:27 PM PDT 24
Finished Jun 25 05:38:29 PM PDT 24
Peak memory 200252 kb
Host smart-a5b19247-c051-437b-ac6a-5e7d96703656
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3414925835 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_smoke.3414925835
Directory /workspace/21.rstmgr_smoke/latest

Test location /workspace/coverage/default/21.rstmgr_stress_all.1885587718
Short name T97
Test name
Test status
Simulation time 1991081453 ps
CPU time 9.6 seconds
Started Jun 25 05:38:30 PM PDT 24
Finished Jun 25 05:38:42 PM PDT 24
Peak memory 208468 kb
Host smart-829cca25-014e-4f44-8c01-7463b09b6e36
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885587718 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_stress_all.1885587718
Directory /workspace/21.rstmgr_stress_all/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst.2473282665
Short name T206
Test name
Test status
Simulation time 139494906 ps
CPU time 1.94 seconds
Started Jun 25 05:38:28 PM PDT 24
Finished Jun 25 05:38:32 PM PDT 24
Peak memory 200080 kb
Host smart-bb6c1c3e-a696-4e71-9ace-2a63236f12e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2473282665 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst.2473282665
Directory /workspace/21.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst_reset_race.547009585
Short name T307
Test name
Test status
Simulation time 72908896 ps
CPU time 0.86 seconds
Started Jun 25 05:38:29 PM PDT 24
Finished Jun 25 05:38:32 PM PDT 24
Peak memory 200028 kb
Host smart-f7d7a0da-f45c-4e92-8f55-d407f1259fea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=547009585 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst_reset_race.547009585
Directory /workspace/21.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/22.rstmgr_alert_test.1432025762
Short name T404
Test name
Test status
Simulation time 56116911 ps
CPU time 0.8 seconds
Started Jun 25 05:38:39 PM PDT 24
Finished Jun 25 05:38:41 PM PDT 24
Peak memory 199844 kb
Host smart-44a89dfd-4f5d-464b-b2a7-e29b02223e9e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432025762 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_alert_test.1432025762
Directory /workspace/22.rstmgr_alert_test/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_cnsty.373265457
Short name T297
Test name
Test status
Simulation time 1222798255 ps
CPU time 6.56 seconds
Started Jun 25 05:38:50 PM PDT 24
Finished Jun 25 05:38:59 PM PDT 24
Peak memory 217548 kb
Host smart-2a839ef9-9df2-4eb4-8ebe-210ab85baeb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=373265457 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_cnsty.373265457
Directory /workspace/22.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_shadow_attack.913804692
Short name T378
Test name
Test status
Simulation time 244330034 ps
CPU time 1.2 seconds
Started Jun 25 05:38:47 PM PDT 24
Finished Jun 25 05:38:49 PM PDT 24
Peak memory 217452 kb
Host smart-a3a43dc2-35c0-4b3b-a55c-b95dd34c5e1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=913804692 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_shadow_attack.913804692
Directory /workspace/22.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/22.rstmgr_por_stretcher.309156559
Short name T494
Test name
Test status
Simulation time 91070755 ps
CPU time 0.75 seconds
Started Jun 25 05:38:52 PM PDT 24
Finished Jun 25 05:38:56 PM PDT 24
Peak memory 199896 kb
Host smart-65da748a-522c-41e6-aaf1-b355b9b58731
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=309156559 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_por_stretcher.309156559
Directory /workspace/22.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/22.rstmgr_reset.4288390297
Short name T293
Test name
Test status
Simulation time 1636708011 ps
CPU time 6.3 seconds
Started Jun 25 05:38:49 PM PDT 24
Finished Jun 25 05:38:56 PM PDT 24
Peak memory 200272 kb
Host smart-51b742e2-bab8-478c-94df-a0ce13a3d623
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4288390297 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_reset.4288390297
Directory /workspace/22.rstmgr_reset/latest

Test location /workspace/coverage/default/22.rstmgr_sec_cm_scan_intersig_mubi.292363296
Short name T412
Test name
Test status
Simulation time 173069545 ps
CPU time 1.18 seconds
Started Jun 25 05:38:46 PM PDT 24
Finished Jun 25 05:38:48 PM PDT 24
Peak memory 200092 kb
Host smart-b44c2509-97f1-40df-a031-d37cf5f3d2bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=292363296 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sec_cm_scan_intersig_mubi.292363296
Directory /workspace/22.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/22.rstmgr_smoke.2101800989
Short name T156
Test name
Test status
Simulation time 120366057 ps
CPU time 1.2 seconds
Started Jun 25 05:38:39 PM PDT 24
Finished Jun 25 05:38:42 PM PDT 24
Peak memory 200276 kb
Host smart-6ba55e85-4910-4089-a9db-aad5933e69a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2101800989 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_smoke.2101800989
Directory /workspace/22.rstmgr_smoke/latest

Test location /workspace/coverage/default/22.rstmgr_stress_all.808464581
Short name T168
Test name
Test status
Simulation time 7709084035 ps
CPU time 27.65 seconds
Started Jun 25 05:38:39 PM PDT 24
Finished Jun 25 05:39:08 PM PDT 24
Peak memory 209432 kb
Host smart-2bbbfbd0-29f8-424c-ab41-2ca13b343bbf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808464581 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_stress_all.808464581
Directory /workspace/22.rstmgr_stress_all/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst.2559927791
Short name T245
Test name
Test status
Simulation time 144402891 ps
CPU time 1.89 seconds
Started Jun 25 05:38:50 PM PDT 24
Finished Jun 25 05:38:53 PM PDT 24
Peak memory 208200 kb
Host smart-2f872e0f-a1d2-4ba6-805c-180fed92e24e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2559927791 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst.2559927791
Directory /workspace/22.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst_reset_race.4069144296
Short name T329
Test name
Test status
Simulation time 92994566 ps
CPU time 0.92 seconds
Started Jun 25 05:38:38 PM PDT 24
Finished Jun 25 05:38:40 PM PDT 24
Peak memory 200100 kb
Host smart-cad655f5-21fd-4993-94f6-af0f57bf5eaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4069144296 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst_reset_race.4069144296
Directory /workspace/22.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/23.rstmgr_alert_test.1201929158
Short name T47
Test name
Test status
Simulation time 90027727 ps
CPU time 0.86 seconds
Started Jun 25 05:38:52 PM PDT 24
Finished Jun 25 05:38:56 PM PDT 24
Peak memory 199868 kb
Host smart-5a0aefe4-5655-4350-a501-edeee5027fde
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201929158 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_alert_test.1201929158
Directory /workspace/23.rstmgr_alert_test/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_cnsty.1195527457
Short name T32
Test name
Test status
Simulation time 2360541775 ps
CPU time 9.38 seconds
Started Jun 25 05:38:40 PM PDT 24
Finished Jun 25 05:38:50 PM PDT 24
Peak memory 217848 kb
Host smart-71b814f5-f2c3-4817-bc91-28725f6eb807
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1195527457 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_cnsty.1195527457
Directory /workspace/23.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_shadow_attack.3208377009
Short name T13
Test name
Test status
Simulation time 243741672 ps
CPU time 1.09 seconds
Started Jun 25 05:38:38 PM PDT 24
Finished Jun 25 05:38:41 PM PDT 24
Peak memory 217452 kb
Host smart-7ffcb299-9514-48f3-badb-583c27b2aab1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3208377009 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_shadow_attack.3208377009
Directory /workspace/23.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/23.rstmgr_por_stretcher.1499888068
Short name T484
Test name
Test status
Simulation time 132372986 ps
CPU time 0.85 seconds
Started Jun 25 05:38:38 PM PDT 24
Finished Jun 25 05:38:40 PM PDT 24
Peak memory 199904 kb
Host smart-a50cb98f-5f9d-4ad6-9b93-47b161b658a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1499888068 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_por_stretcher.1499888068
Directory /workspace/23.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/23.rstmgr_reset.2560241877
Short name T418
Test name
Test status
Simulation time 1357009944 ps
CPU time 5.3 seconds
Started Jun 25 05:38:48 PM PDT 24
Finished Jun 25 05:38:55 PM PDT 24
Peak memory 200108 kb
Host smart-0d55fb53-e54a-489d-9984-e1839f10c587
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2560241877 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_reset.2560241877
Directory /workspace/23.rstmgr_reset/latest

Test location /workspace/coverage/default/23.rstmgr_sec_cm_scan_intersig_mubi.205330289
Short name T381
Test name
Test status
Simulation time 177613121 ps
CPU time 1.17 seconds
Started Jun 25 05:38:50 PM PDT 24
Finished Jun 25 05:38:54 PM PDT 24
Peak memory 200004 kb
Host smart-c462ecb9-1b44-4354-886f-c6fd3c70919b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=205330289 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sec_cm_scan_intersig_mubi.205330289
Directory /workspace/23.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/23.rstmgr_smoke.576290964
Short name T357
Test name
Test status
Simulation time 121109289 ps
CPU time 1.23 seconds
Started Jun 25 05:38:38 PM PDT 24
Finished Jun 25 05:38:40 PM PDT 24
Peak memory 200272 kb
Host smart-1f8c7c38-9e54-48e1-a567-3eda0d24813e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=576290964 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_smoke.576290964
Directory /workspace/23.rstmgr_smoke/latest

Test location /workspace/coverage/default/23.rstmgr_stress_all.2297764172
Short name T281
Test name
Test status
Simulation time 1839748064 ps
CPU time 8.71 seconds
Started Jun 25 05:38:37 PM PDT 24
Finished Jun 25 05:38:47 PM PDT 24
Peak memory 208564 kb
Host smart-b713fbcc-8a5e-4938-b168-7b7bf61b7bc7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297764172 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_stress_all.2297764172
Directory /workspace/23.rstmgr_stress_all/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst.1952980486
Short name T334
Test name
Test status
Simulation time 136487475 ps
CPU time 1.71 seconds
Started Jun 25 05:38:38 PM PDT 24
Finished Jun 25 05:38:41 PM PDT 24
Peak memory 200076 kb
Host smart-ac7f1600-2611-4355-9b88-0912000b8983
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1952980486 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst.1952980486
Directory /workspace/23.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst_reset_race.2298882452
Short name T425
Test name
Test status
Simulation time 190027706 ps
CPU time 1.21 seconds
Started Jun 25 05:38:37 PM PDT 24
Finished Jun 25 05:38:39 PM PDT 24
Peak memory 200100 kb
Host smart-d2dd5cf6-1207-4c9b-b21b-e45811fcbebc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2298882452 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst_reset_race.2298882452
Directory /workspace/23.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/24.rstmgr_alert_test.2884411967
Short name T224
Test name
Test status
Simulation time 66615608 ps
CPU time 0.89 seconds
Started Jun 25 05:38:49 PM PDT 24
Finished Jun 25 05:38:51 PM PDT 24
Peak memory 199888 kb
Host smart-c2f7c2d2-3fcd-45c5-972a-7cf235366aa8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884411967 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_alert_test.2884411967
Directory /workspace/24.rstmgr_alert_test/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_cnsty.1100781753
Short name T498
Test name
Test status
Simulation time 1227200271 ps
CPU time 5.93 seconds
Started Jun 25 05:38:51 PM PDT 24
Finished Jun 25 05:39:00 PM PDT 24
Peak memory 221628 kb
Host smart-5db5aa4c-39ed-4cd8-a07f-f9a1c4363c7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1100781753 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_cnsty.1100781753
Directory /workspace/24.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_shadow_attack.1171425108
Short name T284
Test name
Test status
Simulation time 244399542 ps
CPU time 1.05 seconds
Started Jun 25 05:38:41 PM PDT 24
Finished Jun 25 05:38:43 PM PDT 24
Peak memory 217500 kb
Host smart-35b62468-ff7b-48ab-9800-c3b16b13b297
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1171425108 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_shadow_attack.1171425108
Directory /workspace/24.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/24.rstmgr_por_stretcher.2816180055
Short name T151
Test name
Test status
Simulation time 121736068 ps
CPU time 0.84 seconds
Started Jun 25 05:38:52 PM PDT 24
Finished Jun 25 05:38:56 PM PDT 24
Peak memory 199888 kb
Host smart-c6cede23-881e-46ba-b959-8833cc682d90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2816180055 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_por_stretcher.2816180055
Directory /workspace/24.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/24.rstmgr_reset.1541730992
Short name T336
Test name
Test status
Simulation time 1661458048 ps
CPU time 6.25 seconds
Started Jun 25 05:38:38 PM PDT 24
Finished Jun 25 05:38:46 PM PDT 24
Peak memory 200304 kb
Host smart-57a8aa05-88e2-44c3-8ac1-b6127d705c89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1541730992 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_reset.1541730992
Directory /workspace/24.rstmgr_reset/latest

Test location /workspace/coverage/default/24.rstmgr_sec_cm_scan_intersig_mubi.3382747285
Short name T497
Test name
Test status
Simulation time 100953996 ps
CPU time 1.02 seconds
Started Jun 25 05:38:37 PM PDT 24
Finished Jun 25 05:38:39 PM PDT 24
Peak memory 200072 kb
Host smart-f439aa4c-17bc-4847-92c1-4012cf9b6384
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3382747285 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sec_cm_scan_intersig_mubi.3382747285
Directory /workspace/24.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/24.rstmgr_smoke.4115304570
Short name T230
Test name
Test status
Simulation time 229617399 ps
CPU time 1.65 seconds
Started Jun 25 05:38:50 PM PDT 24
Finished Jun 25 05:38:54 PM PDT 24
Peak memory 200264 kb
Host smart-20b07893-b630-44a9-a886-af7b89721e9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4115304570 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_smoke.4115304570
Directory /workspace/24.rstmgr_smoke/latest

Test location /workspace/coverage/default/24.rstmgr_stress_all.1155674652
Short name T432
Test name
Test status
Simulation time 6924168728 ps
CPU time 24.83 seconds
Started Jun 25 05:38:40 PM PDT 24
Finished Jun 25 05:39:06 PM PDT 24
Peak memory 200412 kb
Host smart-fa09c6ad-ef2d-4022-9375-f25ebf307a72
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155674652 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_stress_all.1155674652
Directory /workspace/24.rstmgr_stress_all/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst.677093689
Short name T274
Test name
Test status
Simulation time 404524949 ps
CPU time 2.33 seconds
Started Jun 25 05:38:39 PM PDT 24
Finished Jun 25 05:38:42 PM PDT 24
Peak memory 200024 kb
Host smart-3801f8ac-70c7-4b67-b107-c9cac37c6aa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=677093689 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst.677093689
Directory /workspace/24.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/25.rstmgr_alert_test.732006030
Short name T291
Test name
Test status
Simulation time 62860488 ps
CPU time 0.78 seconds
Started Jun 25 05:38:47 PM PDT 24
Finished Jun 25 05:38:48 PM PDT 24
Peak memory 199888 kb
Host smart-7c663ef4-d3fb-442b-aee9-19c883ee06e8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732006030 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_alert_test.732006030
Directory /workspace/25.rstmgr_alert_test/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_cnsty.99229915
Short name T388
Test name
Test status
Simulation time 2349012405 ps
CPU time 9.38 seconds
Started Jun 25 05:38:48 PM PDT 24
Finished Jun 25 05:38:58 PM PDT 24
Peak memory 221752 kb
Host smart-d1bfd7ff-ad02-4e25-9353-277c6b2185f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=99229915 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_cnsty.99229915
Directory /workspace/25.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_shadow_attack.3941512282
Short name T410
Test name
Test status
Simulation time 244320823 ps
CPU time 1.17 seconds
Started Jun 25 05:38:40 PM PDT 24
Finished Jun 25 05:38:42 PM PDT 24
Peak memory 217696 kb
Host smart-014ac89f-affa-4933-974a-da5ddba88c37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3941512282 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_shadow_attack.3941512282
Directory /workspace/25.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/25.rstmgr_por_stretcher.515438924
Short name T214
Test name
Test status
Simulation time 199398425 ps
CPU time 0.94 seconds
Started Jun 25 05:38:37 PM PDT 24
Finished Jun 25 05:38:39 PM PDT 24
Peak memory 199888 kb
Host smart-55354916-3323-4625-a721-1bfb4de70e01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=515438924 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_por_stretcher.515438924
Directory /workspace/25.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/25.rstmgr_reset.2889501446
Short name T312
Test name
Test status
Simulation time 1739089433 ps
CPU time 6.84 seconds
Started Jun 25 05:38:49 PM PDT 24
Finished Jun 25 05:38:57 PM PDT 24
Peak memory 200332 kb
Host smart-960270f1-a4c3-407a-849c-cd0fa2401004
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2889501446 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_reset.2889501446
Directory /workspace/25.rstmgr_reset/latest

Test location /workspace/coverage/default/25.rstmgr_sec_cm_scan_intersig_mubi.1204167569
Short name T306
Test name
Test status
Simulation time 144199045 ps
CPU time 1.11 seconds
Started Jun 25 05:38:41 PM PDT 24
Finished Jun 25 05:38:43 PM PDT 24
Peak memory 200088 kb
Host smart-804c728e-c447-4be2-ac0c-d80be6c5dd5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1204167569 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sec_cm_scan_intersig_mubi.1204167569
Directory /workspace/25.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/25.rstmgr_smoke.1553441284
Short name T360
Test name
Test status
Simulation time 112788524 ps
CPU time 1.2 seconds
Started Jun 25 05:38:52 PM PDT 24
Finished Jun 25 05:38:57 PM PDT 24
Peak memory 199912 kb
Host smart-ac466d7c-b690-44c0-80b2-ed851d9cfab0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1553441284 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_smoke.1553441284
Directory /workspace/25.rstmgr_smoke/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst.1092474612
Short name T331
Test name
Test status
Simulation time 316070474 ps
CPU time 1.92 seconds
Started Jun 25 05:38:48 PM PDT 24
Finished Jun 25 05:38:51 PM PDT 24
Peak memory 200084 kb
Host smart-76972a6f-2726-47b6-aa22-250d1cb368c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1092474612 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst.1092474612
Directory /workspace/25.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst_reset_race.2410010529
Short name T441
Test name
Test status
Simulation time 230065827 ps
CPU time 1.31 seconds
Started Jun 25 05:38:51 PM PDT 24
Finished Jun 25 05:38:56 PM PDT 24
Peak memory 200072 kb
Host smart-8f28d44d-f437-4efe-9a48-aeb635e2c951
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2410010529 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst_reset_race.2410010529
Directory /workspace/25.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/26.rstmgr_alert_test.2038830445
Short name T477
Test name
Test status
Simulation time 67410032 ps
CPU time 0.75 seconds
Started Jun 25 05:38:49 PM PDT 24
Finished Jun 25 05:38:51 PM PDT 24
Peak memory 199876 kb
Host smart-7198e0c1-199c-4b82-98b9-9728d16c7d0a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038830445 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_alert_test.2038830445
Directory /workspace/26.rstmgr_alert_test/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_cnsty.155733125
Short name T455
Test name
Test status
Simulation time 2357629900 ps
CPU time 8.62 seconds
Started Jun 25 05:38:55 PM PDT 24
Finished Jun 25 05:39:07 PM PDT 24
Peak memory 217356 kb
Host smart-7905b56b-821c-4325-821d-6142a1d96aca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=155733125 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_cnsty.155733125
Directory /workspace/26.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_shadow_attack.2796325168
Short name T180
Test name
Test status
Simulation time 244414740 ps
CPU time 1.13 seconds
Started Jun 25 05:38:54 PM PDT 24
Finished Jun 25 05:38:58 PM PDT 24
Peak memory 217444 kb
Host smart-0561220a-1f97-4149-9932-058ebd71650a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2796325168 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_shadow_attack.2796325168
Directory /workspace/26.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/26.rstmgr_por_stretcher.2880864883
Short name T249
Test name
Test status
Simulation time 90246912 ps
CPU time 0.78 seconds
Started Jun 25 05:38:52 PM PDT 24
Finished Jun 25 05:38:56 PM PDT 24
Peak memory 199528 kb
Host smart-634d6f7c-995d-47ab-8456-04c19571c71a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2880864883 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_por_stretcher.2880864883
Directory /workspace/26.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/26.rstmgr_reset.4237020757
Short name T108
Test name
Test status
Simulation time 904541011 ps
CPU time 4.57 seconds
Started Jun 25 05:38:50 PM PDT 24
Finished Jun 25 05:38:58 PM PDT 24
Peak memory 200328 kb
Host smart-824a6ad1-73e2-433a-84fa-b665b82feb9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4237020757 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_reset.4237020757
Directory /workspace/26.rstmgr_reset/latest

Test location /workspace/coverage/default/26.rstmgr_sec_cm_scan_intersig_mubi.21501508
Short name T6
Test name
Test status
Simulation time 149281918 ps
CPU time 1.13 seconds
Started Jun 25 05:38:49 PM PDT 24
Finished Jun 25 05:38:51 PM PDT 24
Peak memory 200084 kb
Host smart-82ee8ceb-42fd-4568-8107-346882712791
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21501508 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sec_cm_scan_intersig_mubi.21501508
Directory /workspace/26.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/26.rstmgr_smoke.3974379158
Short name T351
Test name
Test status
Simulation time 227948738 ps
CPU time 1.53 seconds
Started Jun 25 05:38:39 PM PDT 24
Finished Jun 25 05:38:42 PM PDT 24
Peak memory 200200 kb
Host smart-36c3c271-4292-4288-a32c-72f96d65a2cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3974379158 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_smoke.3974379158
Directory /workspace/26.rstmgr_smoke/latest

Test location /workspace/coverage/default/26.rstmgr_stress_all.3574458118
Short name T107
Test name
Test status
Simulation time 1816913419 ps
CPU time 7.28 seconds
Started Jun 25 05:38:51 PM PDT 24
Finished Jun 25 05:39:01 PM PDT 24
Peak memory 200332 kb
Host smart-99ab1e20-3e55-447e-a46d-fbaf4ad84e97
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3574458118 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_stress_all.3574458118
Directory /workspace/26.rstmgr_stress_all/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst.2371254607
Short name T101
Test name
Test status
Simulation time 114576456 ps
CPU time 1.54 seconds
Started Jun 25 05:38:51 PM PDT 24
Finished Jun 25 05:38:55 PM PDT 24
Peak memory 200128 kb
Host smart-a138d03a-d2be-4c6e-9275-2ab62a02af00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2371254607 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst.2371254607
Directory /workspace/26.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst_reset_race.1437038037
Short name T256
Test name
Test status
Simulation time 85284538 ps
CPU time 0.84 seconds
Started Jun 25 05:38:50 PM PDT 24
Finished Jun 25 05:38:54 PM PDT 24
Peak memory 200072 kb
Host smart-2b608656-0a50-486d-a08f-d95df54d684e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1437038037 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst_reset_race.1437038037
Directory /workspace/26.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/27.rstmgr_alert_test.1557890540
Short name T504
Test name
Test status
Simulation time 72987604 ps
CPU time 0.84 seconds
Started Jun 25 05:38:49 PM PDT 24
Finished Jun 25 05:38:51 PM PDT 24
Peak memory 199880 kb
Host smart-b7247b36-ec46-464e-8a07-09ed6012d7b4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557890540 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_alert_test.1557890540
Directory /workspace/27.rstmgr_alert_test/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_cnsty.3172460747
Short name T219
Test name
Test status
Simulation time 1218507648 ps
CPU time 5.68 seconds
Started Jun 25 05:38:48 PM PDT 24
Finished Jun 25 05:38:55 PM PDT 24
Peak memory 217700 kb
Host smart-f88e8c94-44cc-4d64-8e76-3aadf47374b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3172460747 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_cnsty.3172460747
Directory /workspace/27.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_shadow_attack.2734929033
Short name T371
Test name
Test status
Simulation time 244916445 ps
CPU time 1.1 seconds
Started Jun 25 05:38:51 PM PDT 24
Finished Jun 25 05:38:56 PM PDT 24
Peak memory 217448 kb
Host smart-4d8a673c-118b-4a96-bbe1-976d3e4e0110
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2734929033 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_shadow_attack.2734929033
Directory /workspace/27.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/27.rstmgr_por_stretcher.3091098874
Short name T408
Test name
Test status
Simulation time 135572631 ps
CPU time 0.87 seconds
Started Jun 25 05:38:51 PM PDT 24
Finished Jun 25 05:38:54 PM PDT 24
Peak memory 199888 kb
Host smart-3bfaaa61-f265-47f3-ad3c-bb33f62ca1cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3091098874 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_por_stretcher.3091098874
Directory /workspace/27.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/27.rstmgr_reset.3192875274
Short name T420
Test name
Test status
Simulation time 1419217638 ps
CPU time 5.86 seconds
Started Jun 25 05:38:51 PM PDT 24
Finished Jun 25 05:39:00 PM PDT 24
Peak memory 200344 kb
Host smart-d0d457e7-fb7e-49f8-8d40-2e1545340e9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3192875274 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_reset.3192875274
Directory /workspace/27.rstmgr_reset/latest

Test location /workspace/coverage/default/27.rstmgr_sec_cm_scan_intersig_mubi.1982738101
Short name T36
Test name
Test status
Simulation time 169114931 ps
CPU time 1.16 seconds
Started Jun 25 05:38:54 PM PDT 24
Finished Jun 25 05:38:58 PM PDT 24
Peak memory 200064 kb
Host smart-ccb68746-59b7-43db-9989-c4d4702b7b38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1982738101 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sec_cm_scan_intersig_mubi.1982738101
Directory /workspace/27.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/27.rstmgr_smoke.3600081501
Short name T454
Test name
Test status
Simulation time 201284132 ps
CPU time 1.46 seconds
Started Jun 25 05:38:51 PM PDT 24
Finished Jun 25 05:38:56 PM PDT 24
Peak memory 200260 kb
Host smart-65a44a67-d61c-460e-baf0-10ca0fd03b77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3600081501 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_smoke.3600081501
Directory /workspace/27.rstmgr_smoke/latest

Test location /workspace/coverage/default/27.rstmgr_stress_all.3327078702
Short name T102
Test name
Test status
Simulation time 2031086911 ps
CPU time 6.68 seconds
Started Jun 25 05:38:51 PM PDT 24
Finished Jun 25 05:39:01 PM PDT 24
Peak memory 208472 kb
Host smart-97e1172b-049f-483e-865e-331bcbd439b3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3327078702 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_stress_all.3327078702
Directory /workspace/27.rstmgr_stress_all/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst.3826974570
Short name T442
Test name
Test status
Simulation time 123996109 ps
CPU time 1.62 seconds
Started Jun 25 05:38:51 PM PDT 24
Finished Jun 25 05:38:56 PM PDT 24
Peak memory 208324 kb
Host smart-658aae2a-f5b2-47b3-b6c2-c9d91db72ed8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3826974570 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst.3826974570
Directory /workspace/27.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst_reset_race.2051702579
Short name T534
Test name
Test status
Simulation time 207495971 ps
CPU time 1.21 seconds
Started Jun 25 05:38:56 PM PDT 24
Finished Jun 25 05:39:01 PM PDT 24
Peak memory 200076 kb
Host smart-e91dc2a2-f92d-4a52-b25c-7c850ae2d055
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2051702579 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst_reset_race.2051702579
Directory /workspace/27.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/28.rstmgr_alert_test.1469035502
Short name T300
Test name
Test status
Simulation time 74199030 ps
CPU time 0.81 seconds
Started Jun 25 05:38:51 PM PDT 24
Finished Jun 25 05:38:54 PM PDT 24
Peak memory 199864 kb
Host smart-637965e0-2558-423b-a5a0-96b4caffc660
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469035502 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_alert_test.1469035502
Directory /workspace/28.rstmgr_alert_test/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_cnsty.1576889868
Short name T533
Test name
Test status
Simulation time 1226782819 ps
CPU time 5.73 seconds
Started Jun 25 05:38:49 PM PDT 24
Finished Jun 25 05:38:55 PM PDT 24
Peak memory 221352 kb
Host smart-7c5253a3-442e-4286-89b5-014d83c8fed2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1576889868 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_cnsty.1576889868
Directory /workspace/28.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_shadow_attack.2875886312
Short name T179
Test name
Test status
Simulation time 244789519 ps
CPU time 1.07 seconds
Started Jun 25 05:38:52 PM PDT 24
Finished Jun 25 05:38:56 PM PDT 24
Peak memory 217432 kb
Host smart-ebac0428-3573-48e5-ac37-bd1745f33cbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2875886312 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_shadow_attack.2875886312
Directory /workspace/28.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/28.rstmgr_por_stretcher.2719630401
Short name T355
Test name
Test status
Simulation time 137536840 ps
CPU time 0.83 seconds
Started Jun 25 05:38:47 PM PDT 24
Finished Jun 25 05:38:49 PM PDT 24
Peak memory 199888 kb
Host smart-e8c015f1-4cb2-45a7-ad1d-8c13466cfc0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2719630401 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_por_stretcher.2719630401
Directory /workspace/28.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/28.rstmgr_reset.2013176722
Short name T424
Test name
Test status
Simulation time 815828520 ps
CPU time 3.97 seconds
Started Jun 25 05:38:51 PM PDT 24
Finished Jun 25 05:38:58 PM PDT 24
Peak memory 200332 kb
Host smart-f7d33582-b532-41c4-ac63-2d4e6a9cf593
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2013176722 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_reset.2013176722
Directory /workspace/28.rstmgr_reset/latest

Test location /workspace/coverage/default/28.rstmgr_sec_cm_scan_intersig_mubi.1023482082
Short name T345
Test name
Test status
Simulation time 174454138 ps
CPU time 1.26 seconds
Started Jun 25 05:38:49 PM PDT 24
Finished Jun 25 05:38:51 PM PDT 24
Peak memory 200076 kb
Host smart-0b12a52a-339d-4c3d-ae54-1f07c501b311
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1023482082 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sec_cm_scan_intersig_mubi.1023482082
Directory /workspace/28.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/28.rstmgr_smoke.1162951534
Short name T196
Test name
Test status
Simulation time 259530744 ps
CPU time 1.58 seconds
Started Jun 25 05:38:50 PM PDT 24
Finished Jun 25 05:38:54 PM PDT 24
Peak memory 200212 kb
Host smart-22f95d8e-d821-4093-928e-508dc21f70df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1162951534 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_smoke.1162951534
Directory /workspace/28.rstmgr_smoke/latest

Test location /workspace/coverage/default/28.rstmgr_stress_all.1198526415
Short name T259
Test name
Test status
Simulation time 888698085 ps
CPU time 4.31 seconds
Started Jun 25 05:38:52 PM PDT 24
Finished Jun 25 05:39:00 PM PDT 24
Peak memory 209620 kb
Host smart-6ce63fc3-d547-49f4-a0c0-dfd2d8d8d8a4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198526415 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_stress_all.1198526415
Directory /workspace/28.rstmgr_stress_all/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst.462526552
Short name T444
Test name
Test status
Simulation time 131579308 ps
CPU time 1.75 seconds
Started Jun 25 05:38:51 PM PDT 24
Finished Jun 25 05:38:55 PM PDT 24
Peak memory 208272 kb
Host smart-4c0b8e52-bb0e-4c1c-97a6-2160736eb900
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=462526552 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst.462526552
Directory /workspace/28.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst_reset_race.201509124
Short name T414
Test name
Test status
Simulation time 121232173 ps
CPU time 1.03 seconds
Started Jun 25 05:38:52 PM PDT 24
Finished Jun 25 05:38:56 PM PDT 24
Peak memory 200068 kb
Host smart-dc9db7ea-ae57-4330-b51f-7f65f0c2f870
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=201509124 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst_reset_race.201509124
Directory /workspace/28.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/29.rstmgr_alert_test.467090166
Short name T250
Test name
Test status
Simulation time 70747325 ps
CPU time 0.77 seconds
Started Jun 25 05:38:50 PM PDT 24
Finished Jun 25 05:38:54 PM PDT 24
Peak memory 199800 kb
Host smart-8e38d37d-9999-47cc-8fde-08d626b365fe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=467090166 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_alert_test.467090166
Directory /workspace/29.rstmgr_alert_test/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_cnsty.2446566981
Short name T46
Test name
Test status
Simulation time 1224452000 ps
CPU time 5.51 seconds
Started Jun 25 05:38:51 PM PDT 24
Finished Jun 25 05:38:59 PM PDT 24
Peak memory 217728 kb
Host smart-a84f35d8-4e75-4831-9f21-73539442798a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2446566981 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_cnsty.2446566981
Directory /workspace/29.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_shadow_attack.2717815009
Short name T37
Test name
Test status
Simulation time 244357022 ps
CPU time 1.13 seconds
Started Jun 25 05:38:57 PM PDT 24
Finished Jun 25 05:39:01 PM PDT 24
Peak memory 217444 kb
Host smart-a4781c87-7f9e-4b44-8008-95ae427d081b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2717815009 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_shadow_attack.2717815009
Directory /workspace/29.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/29.rstmgr_por_stretcher.1691842960
Short name T528
Test name
Test status
Simulation time 75788580 ps
CPU time 0.75 seconds
Started Jun 25 05:38:50 PM PDT 24
Finished Jun 25 05:38:53 PM PDT 24
Peak memory 199832 kb
Host smart-2860a8de-0d27-4c08-954a-fda7379e24db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1691842960 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_por_stretcher.1691842960
Directory /workspace/29.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/29.rstmgr_reset.672527641
Short name T120
Test name
Test status
Simulation time 1944968271 ps
CPU time 7.12 seconds
Started Jun 25 05:38:52 PM PDT 24
Finished Jun 25 05:39:03 PM PDT 24
Peak memory 200344 kb
Host smart-33bbb9b5-f6fe-4b31-a59a-4d134d340a51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=672527641 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_reset.672527641
Directory /workspace/29.rstmgr_reset/latest

Test location /workspace/coverage/default/29.rstmgr_sec_cm_scan_intersig_mubi.1406473709
Short name T150
Test name
Test status
Simulation time 106611049 ps
CPU time 1.07 seconds
Started Jun 25 05:38:50 PM PDT 24
Finished Jun 25 05:38:54 PM PDT 24
Peak memory 200028 kb
Host smart-5226659d-b791-42b5-9acb-b0c4ffaab4e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1406473709 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sec_cm_scan_intersig_mubi.1406473709
Directory /workspace/29.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/29.rstmgr_smoke.3730213335
Short name T174
Test name
Test status
Simulation time 117077560 ps
CPU time 1.22 seconds
Started Jun 25 05:38:52 PM PDT 24
Finished Jun 25 05:38:57 PM PDT 24
Peak memory 200320 kb
Host smart-ddc79ba9-7843-4224-a1b9-020cfa73f2ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3730213335 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_smoke.3730213335
Directory /workspace/29.rstmgr_smoke/latest

Test location /workspace/coverage/default/29.rstmgr_stress_all.910084536
Short name T426
Test name
Test status
Simulation time 5553565590 ps
CPU time 25.67 seconds
Started Jun 25 05:38:51 PM PDT 24
Finished Jun 25 05:39:20 PM PDT 24
Peak memory 200392 kb
Host smart-7dcaa12a-c23d-4bd6-99d3-54b2b5c02ac8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910084536 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_stress_all.910084536
Directory /workspace/29.rstmgr_stress_all/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst.3798531784
Short name T242
Test name
Test status
Simulation time 112447248 ps
CPU time 1.4 seconds
Started Jun 25 05:38:50 PM PDT 24
Finished Jun 25 05:38:53 PM PDT 24
Peak memory 200008 kb
Host smart-b4866d0a-9446-44db-b6d0-567e709e1339
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3798531784 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst.3798531784
Directory /workspace/29.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst_reset_race.573851935
Short name T323
Test name
Test status
Simulation time 201125459 ps
CPU time 1.24 seconds
Started Jun 25 05:38:47 PM PDT 24
Finished Jun 25 05:38:49 PM PDT 24
Peak memory 200068 kb
Host smart-af13527c-192e-441c-80f0-a3c7303c0dee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=573851935 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst_reset_race.573851935
Directory /workspace/29.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/3.rstmgr_alert_test.616413811
Short name T292
Test name
Test status
Simulation time 84984922 ps
CPU time 0.9 seconds
Started Jun 25 05:37:55 PM PDT 24
Finished Jun 25 05:37:58 PM PDT 24
Peak memory 199864 kb
Host smart-3c858d8f-c63c-4e61-b94f-093966be78af
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616413811 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_alert_test.616413811
Directory /workspace/3.rstmgr_alert_test/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_cnsty.2889728681
Short name T39
Test name
Test status
Simulation time 1892504133 ps
CPU time 8.4 seconds
Started Jun 25 05:37:57 PM PDT 24
Finished Jun 25 05:38:08 PM PDT 24
Peak memory 217644 kb
Host smart-0f29e50e-98ee-4724-8162-eeb080b11501
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2889728681 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_cnsty.2889728681
Directory /workspace/3.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_shadow_attack.406074748
Short name T154
Test name
Test status
Simulation time 245071274 ps
CPU time 1.09 seconds
Started Jun 25 05:37:56 PM PDT 24
Finished Jun 25 05:38:00 PM PDT 24
Peak memory 217452 kb
Host smart-d390b949-9130-4ac9-b5cd-b718936f7d06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=406074748 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_shadow_attack.406074748
Directory /workspace/3.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/3.rstmgr_por_stretcher.3790930818
Short name T187
Test name
Test status
Simulation time 91238103 ps
CPU time 0.8 seconds
Started Jun 25 05:37:57 PM PDT 24
Finished Jun 25 05:38:00 PM PDT 24
Peak memory 199892 kb
Host smart-4029852d-cc9c-405e-bfb2-b93386cf81c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3790930818 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_por_stretcher.3790930818
Directory /workspace/3.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/3.rstmgr_reset.25747695
Short name T192
Test name
Test status
Simulation time 693288769 ps
CPU time 3.76 seconds
Started Jun 25 05:37:56 PM PDT 24
Finished Jun 25 05:38:02 PM PDT 24
Peak memory 200368 kb
Host smart-e6cbebb0-2aca-437f-be91-0f395afee549
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=25747695 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_reset.25747695
Directory /workspace/3.rstmgr_reset/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm.2166918081
Short name T61
Test name
Test status
Simulation time 8337762131 ps
CPU time 13.39 seconds
Started Jun 25 05:37:56 PM PDT 24
Finished Jun 25 05:38:11 PM PDT 24
Peak memory 217544 kb
Host smart-251be8eb-9ed3-43c0-b87b-a11d2ad99304
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166918081 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm.2166918081
Directory /workspace/3.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm_scan_intersig_mubi.1557114295
Short name T290
Test name
Test status
Simulation time 98776173 ps
CPU time 1.04 seconds
Started Jun 25 05:37:57 PM PDT 24
Finished Jun 25 05:38:00 PM PDT 24
Peak memory 200028 kb
Host smart-d6a3807a-7507-4221-8d58-4fed87b52d63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1557114295 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm_scan_intersig_mubi.1557114295
Directory /workspace/3.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/3.rstmgr_smoke.3756753138
Short name T401
Test name
Test status
Simulation time 236870315 ps
CPU time 1.58 seconds
Started Jun 25 05:37:56 PM PDT 24
Finished Jun 25 05:37:59 PM PDT 24
Peak memory 200244 kb
Host smart-4faf7d1b-3136-4d19-be83-0400278f66d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3756753138 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_smoke.3756753138
Directory /workspace/3.rstmgr_smoke/latest

Test location /workspace/coverage/default/3.rstmgr_stress_all.714039056
Short name T10
Test name
Test status
Simulation time 5433205798 ps
CPU time 23.02 seconds
Started Jun 25 05:37:56 PM PDT 24
Finished Jun 25 05:38:22 PM PDT 24
Peak memory 210152 kb
Host smart-f0fd1fd3-36c4-4e87-a96a-3ead7b7d097e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714039056 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_stress_all.714039056
Directory /workspace/3.rstmgr_stress_all/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst.2753690165
Short name T390
Test name
Test status
Simulation time 123743856 ps
CPU time 1.52 seconds
Started Jun 25 05:37:57 PM PDT 24
Finished Jun 25 05:38:01 PM PDT 24
Peak memory 200040 kb
Host smart-da981a95-ba3a-415e-a6c3-3322fb365bcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2753690165 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst.2753690165
Directory /workspace/3.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst_reset_race.654128344
Short name T328
Test name
Test status
Simulation time 118244666 ps
CPU time 1.14 seconds
Started Jun 25 05:37:57 PM PDT 24
Finished Jun 25 05:38:01 PM PDT 24
Peak memory 200100 kb
Host smart-e7fc11bb-e19e-474b-8649-31655c4b4324
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=654128344 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst_reset_race.654128344
Directory /workspace/3.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/30.rstmgr_alert_test.1416191292
Short name T159
Test name
Test status
Simulation time 81992540 ps
CPU time 0.81 seconds
Started Jun 25 05:38:49 PM PDT 24
Finished Jun 25 05:38:50 PM PDT 24
Peak memory 199848 kb
Host smart-cef47aac-d9a5-45bb-9375-3b4e89839850
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416191292 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_alert_test.1416191292
Directory /workspace/30.rstmgr_alert_test/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_cnsty.2479729804
Short name T175
Test name
Test status
Simulation time 1224827559 ps
CPU time 5.5 seconds
Started Jun 25 05:38:51 PM PDT 24
Finished Jun 25 05:39:00 PM PDT 24
Peak memory 221744 kb
Host smart-addff28c-c64f-41fc-bcac-aa2d3daba06c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2479729804 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_cnsty.2479729804
Directory /workspace/30.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_shadow_attack.3143899192
Short name T288
Test name
Test status
Simulation time 244581196 ps
CPU time 1.04 seconds
Started Jun 25 05:38:46 PM PDT 24
Finished Jun 25 05:38:48 PM PDT 24
Peak memory 217436 kb
Host smart-bb728e81-7918-4c9b-9c8e-3fb342534253
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3143899192 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_shadow_attack.3143899192
Directory /workspace/30.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/30.rstmgr_por_stretcher.3613755552
Short name T172
Test name
Test status
Simulation time 247399924 ps
CPU time 1.1 seconds
Started Jun 25 05:38:51 PM PDT 24
Finished Jun 25 05:38:55 PM PDT 24
Peak memory 199892 kb
Host smart-dbb244e7-c67c-4e57-acb9-aeaae42c8654
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3613755552 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_por_stretcher.3613755552
Directory /workspace/30.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/30.rstmgr_reset.794427682
Short name T337
Test name
Test status
Simulation time 1691168024 ps
CPU time 7.16 seconds
Started Jun 25 05:38:57 PM PDT 24
Finished Jun 25 05:39:07 PM PDT 24
Peak memory 200368 kb
Host smart-fe711f56-d4e0-4c4e-a86a-9d3286d09519
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=794427682 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_reset.794427682
Directory /workspace/30.rstmgr_reset/latest

Test location /workspace/coverage/default/30.rstmgr_sec_cm_scan_intersig_mubi.2100335979
Short name T23
Test name
Test status
Simulation time 105695109 ps
CPU time 1.02 seconds
Started Jun 25 05:38:54 PM PDT 24
Finished Jun 25 05:38:58 PM PDT 24
Peak memory 200064 kb
Host smart-1dc31094-f49c-4e44-b3ce-0f8734fbf520
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2100335979 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sec_cm_scan_intersig_mubi.2100335979
Directory /workspace/30.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/30.rstmgr_smoke.3316701586
Short name T511
Test name
Test status
Simulation time 189957932 ps
CPU time 1.55 seconds
Started Jun 25 05:38:51 PM PDT 24
Finished Jun 25 05:38:55 PM PDT 24
Peak memory 200272 kb
Host smart-e65c8364-15f2-4cb2-8172-3c8c4b1d63ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3316701586 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_smoke.3316701586
Directory /workspace/30.rstmgr_smoke/latest

Test location /workspace/coverage/default/30.rstmgr_stress_all.3551767249
Short name T72
Test name
Test status
Simulation time 11018699043 ps
CPU time 39.86 seconds
Started Jun 25 05:38:52 PM PDT 24
Finished Jun 25 05:39:36 PM PDT 24
Peak memory 208588 kb
Host smart-40c32eb8-647d-4764-8687-32804802460e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3551767249 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_stress_all.3551767249
Directory /workspace/30.rstmgr_stress_all/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst.4101517173
Short name T398
Test name
Test status
Simulation time 305615644 ps
CPU time 2.19 seconds
Started Jun 25 05:38:52 PM PDT 24
Finished Jun 25 05:38:58 PM PDT 24
Peak memory 208256 kb
Host smart-4031291d-0fc3-46fc-88ed-56622dd54070
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4101517173 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst.4101517173
Directory /workspace/30.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst_reset_race.4034257305
Short name T491
Test name
Test status
Simulation time 96578087 ps
CPU time 0.97 seconds
Started Jun 25 05:38:52 PM PDT 24
Finished Jun 25 05:38:57 PM PDT 24
Peak memory 200076 kb
Host smart-d33229a2-5e39-4abd-bd66-8017635168b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4034257305 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst_reset_race.4034257305
Directory /workspace/30.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/31.rstmgr_alert_test.831757838
Short name T344
Test name
Test status
Simulation time 82118687 ps
CPU time 0.87 seconds
Started Jun 25 05:38:58 PM PDT 24
Finished Jun 25 05:39:02 PM PDT 24
Peak memory 200124 kb
Host smart-42acd86f-f3de-42f9-b7d1-144839ef4041
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831757838 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_alert_test.831757838
Directory /workspace/31.rstmgr_alert_test/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_cnsty.3921334592
Short name T31
Test name
Test status
Simulation time 1227372674 ps
CPU time 5.75 seconds
Started Jun 25 05:38:55 PM PDT 24
Finished Jun 25 05:39:04 PM PDT 24
Peak memory 221668 kb
Host smart-a00b5c93-cdd0-4bea-ab3b-2a5dd3cc4f36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3921334592 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_cnsty.3921334592
Directory /workspace/31.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_shadow_attack.386850483
Short name T50
Test name
Test status
Simulation time 244413549 ps
CPU time 1.17 seconds
Started Jun 25 05:38:52 PM PDT 24
Finished Jun 25 05:38:56 PM PDT 24
Peak memory 217424 kb
Host smart-d0fd35e1-61bd-4cd2-8fc4-78bb28626c1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=386850483 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_shadow_attack.386850483
Directory /workspace/31.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/31.rstmgr_por_stretcher.14518635
Short name T320
Test name
Test status
Simulation time 145615906 ps
CPU time 0.83 seconds
Started Jun 25 05:38:57 PM PDT 24
Finished Jun 25 05:39:00 PM PDT 24
Peak memory 199884 kb
Host smart-0f8c7cfa-4556-4d51-8b2d-481a5f0a6330
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14518635 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_por_stretcher.14518635
Directory /workspace/31.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/31.rstmgr_reset.2061018997
Short name T340
Test name
Test status
Simulation time 2087329654 ps
CPU time 8.08 seconds
Started Jun 25 05:38:55 PM PDT 24
Finished Jun 25 05:39:06 PM PDT 24
Peak memory 200328 kb
Host smart-8b523d15-2c19-4328-8e28-730366c32348
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2061018997 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_reset.2061018997
Directory /workspace/31.rstmgr_reset/latest

Test location /workspace/coverage/default/31.rstmgr_sec_cm_scan_intersig_mubi.3683622906
Short name T365
Test name
Test status
Simulation time 154651404 ps
CPU time 1.12 seconds
Started Jun 25 05:38:57 PM PDT 24
Finished Jun 25 05:39:00 PM PDT 24
Peak memory 200012 kb
Host smart-d769a196-35e2-479c-be04-944c11088575
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3683622906 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sec_cm_scan_intersig_mubi.3683622906
Directory /workspace/31.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/31.rstmgr_smoke.3470039672
Short name T186
Test name
Test status
Simulation time 115578770 ps
CPU time 1.16 seconds
Started Jun 25 05:38:48 PM PDT 24
Finished Jun 25 05:38:50 PM PDT 24
Peak memory 200264 kb
Host smart-a067516c-48a7-43bb-8d12-7f1b349ad6c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3470039672 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_smoke.3470039672
Directory /workspace/31.rstmgr_smoke/latest

Test location /workspace/coverage/default/31.rstmgr_stress_all.3098276818
Short name T392
Test name
Test status
Simulation time 4237642778 ps
CPU time 19.79 seconds
Started Jun 25 05:38:55 PM PDT 24
Finished Jun 25 05:39:18 PM PDT 24
Peak memory 208612 kb
Host smart-d6d3d8c5-2e0b-4f08-b78f-45001aa76f68
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098276818 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_stress_all.3098276818
Directory /workspace/31.rstmgr_stress_all/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst.2138585518
Short name T53
Test name
Test status
Simulation time 326159049 ps
CPU time 2.43 seconds
Started Jun 25 05:38:53 PM PDT 24
Finished Jun 25 05:38:59 PM PDT 24
Peak memory 199996 kb
Host smart-6e1a2f21-682c-4197-ae8a-97acf8372773
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2138585518 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst.2138585518
Directory /workspace/31.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst_reset_race.888684754
Short name T135
Test name
Test status
Simulation time 128247299 ps
CPU time 1.23 seconds
Started Jun 25 05:38:59 PM PDT 24
Finished Jun 25 05:39:02 PM PDT 24
Peak memory 200004 kb
Host smart-1c1a2370-302f-46a2-8ade-e871775cde77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=888684754 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst_reset_race.888684754
Directory /workspace/31.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/32.rstmgr_alert_test.3937926929
Short name T236
Test name
Test status
Simulation time 64689318 ps
CPU time 0.74 seconds
Started Jun 25 05:38:55 PM PDT 24
Finished Jun 25 05:38:58 PM PDT 24
Peak memory 199860 kb
Host smart-e7abd455-9fd1-486a-89b3-cb767a8e69e2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937926929 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_alert_test.3937926929
Directory /workspace/32.rstmgr_alert_test/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_cnsty.710567824
Short name T28
Test name
Test status
Simulation time 1895456713 ps
CPU time 7.39 seconds
Started Jun 25 05:39:00 PM PDT 24
Finished Jun 25 05:39:09 PM PDT 24
Peak memory 221604 kb
Host smart-f58d76eb-bfaa-4610-917f-914707d8a47f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=710567824 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_cnsty.710567824
Directory /workspace/32.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_shadow_attack.1160637817
Short name T278
Test name
Test status
Simulation time 244655544 ps
CPU time 1.07 seconds
Started Jun 25 05:38:55 PM PDT 24
Finished Jun 25 05:38:59 PM PDT 24
Peak memory 217436 kb
Host smart-ad895ed1-bebe-4013-9515-fd05e6afbc88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1160637817 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_shadow_attack.1160637817
Directory /workspace/32.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/32.rstmgr_por_stretcher.1542199274
Short name T19
Test name
Test status
Simulation time 161448328 ps
CPU time 0.91 seconds
Started Jun 25 05:38:56 PM PDT 24
Finished Jun 25 05:39:00 PM PDT 24
Peak memory 199892 kb
Host smart-cdcd559d-4f06-40b6-9e55-1b08d8df1ff7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1542199274 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_por_stretcher.1542199274
Directory /workspace/32.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/32.rstmgr_reset.2449386393
Short name T385
Test name
Test status
Simulation time 1953581107 ps
CPU time 7.27 seconds
Started Jun 25 05:38:54 PM PDT 24
Finished Jun 25 05:39:05 PM PDT 24
Peak memory 200356 kb
Host smart-13d13f6c-6fde-41f3-910c-07b0e9ca6455
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2449386393 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_reset.2449386393
Directory /workspace/32.rstmgr_reset/latest

Test location /workspace/coverage/default/32.rstmgr_sec_cm_scan_intersig_mubi.1325291743
Short name T138
Test name
Test status
Simulation time 192068074 ps
CPU time 1.3 seconds
Started Jun 25 05:38:59 PM PDT 24
Finished Jun 25 05:39:02 PM PDT 24
Peak memory 200076 kb
Host smart-326298bf-61f5-4bcf-afdc-20cf6ba246d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1325291743 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sec_cm_scan_intersig_mubi.1325291743
Directory /workspace/32.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/32.rstmgr_smoke.3041693831
Short name T542
Test name
Test status
Simulation time 256748768 ps
CPU time 1.61 seconds
Started Jun 25 05:38:55 PM PDT 24
Finished Jun 25 05:39:00 PM PDT 24
Peak memory 200264 kb
Host smart-1a996347-fbd9-4dec-aa41-113d8e803b6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3041693831 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_smoke.3041693831
Directory /workspace/32.rstmgr_smoke/latest

Test location /workspace/coverage/default/32.rstmgr_stress_all.1883684816
Short name T368
Test name
Test status
Simulation time 10725196967 ps
CPU time 38.62 seconds
Started Jun 25 05:38:54 PM PDT 24
Finished Jun 25 05:39:36 PM PDT 24
Peak memory 208604 kb
Host smart-b98c027c-bf75-4510-bf9a-d62ff69246c9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883684816 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_stress_all.1883684816
Directory /workspace/32.rstmgr_stress_all/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst.1977046327
Short name T51
Test name
Test status
Simulation time 456958137 ps
CPU time 2.87 seconds
Started Jun 25 05:38:57 PM PDT 24
Finished Jun 25 05:39:03 PM PDT 24
Peak memory 200104 kb
Host smart-e2071593-6db7-4fd7-9864-43a80be90355
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1977046327 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst.1977046327
Directory /workspace/32.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst_reset_race.2418721108
Short name T237
Test name
Test status
Simulation time 171858727 ps
CPU time 1.35 seconds
Started Jun 25 05:38:54 PM PDT 24
Finished Jun 25 05:38:59 PM PDT 24
Peak memory 200312 kb
Host smart-b8f4ed21-1ccd-4bff-8e9b-e96a0074b70e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2418721108 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst_reset_race.2418721108
Directory /workspace/32.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/33.rstmgr_alert_test.537396473
Short name T415
Test name
Test status
Simulation time 84207628 ps
CPU time 0.86 seconds
Started Jun 25 05:38:56 PM PDT 24
Finished Jun 25 05:39:00 PM PDT 24
Peak memory 199868 kb
Host smart-ac59fd28-0b52-46f8-b406-fed5b594c712
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537396473 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_alert_test.537396473
Directory /workspace/33.rstmgr_alert_test/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_shadow_attack.2700222947
Short name T317
Test name
Test status
Simulation time 243747899 ps
CPU time 1.07 seconds
Started Jun 25 05:38:59 PM PDT 24
Finished Jun 25 05:39:02 PM PDT 24
Peak memory 217380 kb
Host smart-c07bf9f0-15f1-4cd9-8398-a7f22a9427c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2700222947 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_shadow_attack.2700222947
Directory /workspace/33.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/33.rstmgr_por_stretcher.1566601057
Short name T326
Test name
Test status
Simulation time 151121719 ps
CPU time 0.93 seconds
Started Jun 25 05:39:00 PM PDT 24
Finished Jun 25 05:39:03 PM PDT 24
Peak memory 199904 kb
Host smart-5576eb92-b1c6-4f47-ab29-80fa04b27ab0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1566601057 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_por_stretcher.1566601057
Directory /workspace/33.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/33.rstmgr_reset.3953515361
Short name T375
Test name
Test status
Simulation time 1800382798 ps
CPU time 6.97 seconds
Started Jun 25 05:38:55 PM PDT 24
Finished Jun 25 05:39:06 PM PDT 24
Peak memory 200252 kb
Host smart-64ee7895-7a8d-4ce4-a957-7442513b831d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3953515361 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_reset.3953515361
Directory /workspace/33.rstmgr_reset/latest

Test location /workspace/coverage/default/33.rstmgr_sec_cm_scan_intersig_mubi.2224975711
Short name T280
Test name
Test status
Simulation time 163901518 ps
CPU time 1.18 seconds
Started Jun 25 05:38:58 PM PDT 24
Finished Jun 25 05:39:02 PM PDT 24
Peak memory 200316 kb
Host smart-5272534f-26b6-478a-a515-89a2a3cabaac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2224975711 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sec_cm_scan_intersig_mubi.2224975711
Directory /workspace/33.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/33.rstmgr_smoke.3714223478
Short name T447
Test name
Test status
Simulation time 200492440 ps
CPU time 1.48 seconds
Started Jun 25 05:38:57 PM PDT 24
Finished Jun 25 05:39:01 PM PDT 24
Peak memory 200200 kb
Host smart-8f48a950-8884-4036-8a88-287f02344134
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3714223478 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_smoke.3714223478
Directory /workspace/33.rstmgr_smoke/latest

Test location /workspace/coverage/default/33.rstmgr_stress_all.3692473517
Short name T285
Test name
Test status
Simulation time 414734078 ps
CPU time 2.25 seconds
Started Jun 25 05:38:56 PM PDT 24
Finished Jun 25 05:39:01 PM PDT 24
Peak memory 200184 kb
Host smart-3d740913-5e66-4b68-8368-8ab6e8ff82af
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692473517 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_stress_all.3692473517
Directory /workspace/33.rstmgr_stress_all/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst.2842057028
Short name T526
Test name
Test status
Simulation time 342316919 ps
CPU time 2.06 seconds
Started Jun 25 05:38:53 PM PDT 24
Finished Jun 25 05:38:59 PM PDT 24
Peak memory 200092 kb
Host smart-43afce30-03a9-4334-a299-b1a428e48aed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2842057028 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst.2842057028
Directory /workspace/33.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst_reset_race.2821375776
Short name T73
Test name
Test status
Simulation time 169913975 ps
CPU time 1.13 seconds
Started Jun 25 05:38:54 PM PDT 24
Finished Jun 25 05:38:58 PM PDT 24
Peak memory 200108 kb
Host smart-fb1aa28d-bb68-45ae-8949-ed86e6a7e47c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2821375776 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst_reset_race.2821375776
Directory /workspace/33.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/34.rstmgr_alert_test.3878166523
Short name T257
Test name
Test status
Simulation time 74984030 ps
CPU time 0.77 seconds
Started Jun 25 05:38:59 PM PDT 24
Finished Jun 25 05:39:02 PM PDT 24
Peak memory 199792 kb
Host smart-18f180e2-e587-4399-bd5f-58ebe2c5b44e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878166523 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_alert_test.3878166523
Directory /workspace/34.rstmgr_alert_test/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_cnsty.2591215157
Short name T252
Test name
Test status
Simulation time 1886788866 ps
CPU time 7.36 seconds
Started Jun 25 05:39:00 PM PDT 24
Finished Jun 25 05:39:09 PM PDT 24
Peak memory 217704 kb
Host smart-7495557e-cb5e-4513-831b-fc2b62b5eaec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2591215157 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_cnsty.2591215157
Directory /workspace/34.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_shadow_attack.1810719774
Short name T481
Test name
Test status
Simulation time 245025925 ps
CPU time 1.14 seconds
Started Jun 25 05:38:59 PM PDT 24
Finished Jun 25 05:39:03 PM PDT 24
Peak memory 217436 kb
Host smart-2039eae1-b53b-47a6-8c27-4d08ba1920cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1810719774 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_shadow_attack.1810719774
Directory /workspace/34.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/34.rstmgr_por_stretcher.2629689836
Short name T470
Test name
Test status
Simulation time 114150059 ps
CPU time 0.89 seconds
Started Jun 25 05:39:00 PM PDT 24
Finished Jun 25 05:39:03 PM PDT 24
Peak memory 199904 kb
Host smart-f92024f8-8628-4042-b5ec-1a0c3184b5af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2629689836 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_por_stretcher.2629689836
Directory /workspace/34.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/34.rstmgr_reset.2194265277
Short name T103
Test name
Test status
Simulation time 953379670 ps
CPU time 4.7 seconds
Started Jun 25 05:38:53 PM PDT 24
Finished Jun 25 05:39:01 PM PDT 24
Peak memory 200340 kb
Host smart-fabc8477-e729-4c90-9914-f89a41ad4ac8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2194265277 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_reset.2194265277
Directory /workspace/34.rstmgr_reset/latest

Test location /workspace/coverage/default/34.rstmgr_sec_cm_scan_intersig_mubi.691464925
Short name T181
Test name
Test status
Simulation time 103458057 ps
CPU time 1.01 seconds
Started Jun 25 05:38:57 PM PDT 24
Finished Jun 25 05:39:00 PM PDT 24
Peak memory 200076 kb
Host smart-f806c5c7-7773-4c1f-a93e-1c47b0e0ae25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=691464925 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sec_cm_scan_intersig_mubi.691464925
Directory /workspace/34.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/34.rstmgr_smoke.3805520601
Short name T299
Test name
Test status
Simulation time 118442670 ps
CPU time 1.15 seconds
Started Jun 25 05:39:00 PM PDT 24
Finished Jun 25 05:39:03 PM PDT 24
Peak memory 200196 kb
Host smart-34160b55-5075-41ca-9e1a-6e289b8ab84c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3805520601 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_smoke.3805520601
Directory /workspace/34.rstmgr_smoke/latest

Test location /workspace/coverage/default/34.rstmgr_stress_all.2098768242
Short name T286
Test name
Test status
Simulation time 4681195644 ps
CPU time 16.8 seconds
Started Jun 25 05:38:55 PM PDT 24
Finished Jun 25 05:39:15 PM PDT 24
Peak memory 200388 kb
Host smart-8854f62d-2e5d-4624-8d14-424417ed13aa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098768242 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_stress_all.2098768242
Directory /workspace/34.rstmgr_stress_all/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst.4002516292
Short name T507
Test name
Test status
Simulation time 117146952 ps
CPU time 1.52 seconds
Started Jun 25 05:38:53 PM PDT 24
Finished Jun 25 05:38:58 PM PDT 24
Peak memory 200052 kb
Host smart-6ab6705a-c98f-430e-8b56-738ea8931a02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4002516292 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst.4002516292
Directory /workspace/34.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst_reset_race.3888072209
Short name T100
Test name
Test status
Simulation time 110653309 ps
CPU time 1 seconds
Started Jun 25 05:38:57 PM PDT 24
Finished Jun 25 05:39:01 PM PDT 24
Peak memory 200076 kb
Host smart-2d5625b4-fe52-49ea-ac27-3850e2751a75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3888072209 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst_reset_race.3888072209
Directory /workspace/34.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/35.rstmgr_alert_test.4281817840
Short name T516
Test name
Test status
Simulation time 83290961 ps
CPU time 0.81 seconds
Started Jun 25 05:38:59 PM PDT 24
Finished Jun 25 05:39:02 PM PDT 24
Peak memory 199884 kb
Host smart-515904c3-9300-4ec0-a2b5-79f4c6b6e657
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4281817840 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_alert_test.4281817840
Directory /workspace/35.rstmgr_alert_test/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_cnsty.2218244040
Short name T43
Test name
Test status
Simulation time 1228082912 ps
CPU time 6.12 seconds
Started Jun 25 05:38:58 PM PDT 24
Finished Jun 25 05:39:06 PM PDT 24
Peak memory 217872 kb
Host smart-bf69d3c9-0499-435e-bdb0-faafde3c2b69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2218244040 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_cnsty.2218244040
Directory /workspace/35.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_shadow_attack.393672856
Short name T505
Test name
Test status
Simulation time 243869222 ps
CPU time 1.08 seconds
Started Jun 25 05:38:53 PM PDT 24
Finished Jun 25 05:38:58 PM PDT 24
Peak memory 217484 kb
Host smart-672b284d-6b77-4d00-a44b-c93f8f66c45a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=393672856 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_shadow_attack.393672856
Directory /workspace/35.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/35.rstmgr_por_stretcher.885383255
Short name T15
Test name
Test status
Simulation time 90897785 ps
CPU time 0.8 seconds
Started Jun 25 05:38:59 PM PDT 24
Finished Jun 25 05:39:02 PM PDT 24
Peak memory 199888 kb
Host smart-02a323aa-30b3-483d-82ce-ba109662ed94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=885383255 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_por_stretcher.885383255
Directory /workspace/35.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/35.rstmgr_reset.14509794
Short name T1
Test name
Test status
Simulation time 848128174 ps
CPU time 4.34 seconds
Started Jun 25 05:38:54 PM PDT 24
Finished Jun 25 05:39:02 PM PDT 24
Peak memory 200376 kb
Host smart-b957fa8a-fd6c-49f7-b65d-3a7d5916e2c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14509794 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_reset.14509794
Directory /workspace/35.rstmgr_reset/latest

Test location /workspace/coverage/default/35.rstmgr_sec_cm_scan_intersig_mubi.105532891
Short name T166
Test name
Test status
Simulation time 139195217 ps
CPU time 1.06 seconds
Started Jun 25 05:39:00 PM PDT 24
Finished Jun 25 05:39:03 PM PDT 24
Peak memory 200016 kb
Host smart-8f0a146d-a4ce-40c5-b838-a350b4212437
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105532891 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sec_cm_scan_intersig_mubi.105532891
Directory /workspace/35.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/35.rstmgr_smoke.2187375673
Short name T448
Test name
Test status
Simulation time 113204766 ps
CPU time 1.14 seconds
Started Jun 25 05:38:54 PM PDT 24
Finished Jun 25 05:38:58 PM PDT 24
Peak memory 200264 kb
Host smart-27e78dcb-e7f4-4876-be52-a49ee61e90cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2187375673 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_smoke.2187375673
Directory /workspace/35.rstmgr_smoke/latest

Test location /workspace/coverage/default/35.rstmgr_stress_all.2510673305
Short name T377
Test name
Test status
Simulation time 13156727441 ps
CPU time 49.39 seconds
Started Jun 25 05:38:53 PM PDT 24
Finished Jun 25 05:39:46 PM PDT 24
Peak memory 208580 kb
Host smart-4f56e6f5-ecc7-4c90-8670-fce735dc95a2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2510673305 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_stress_all.2510673305
Directory /workspace/35.rstmgr_stress_all/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst.1824654092
Short name T395
Test name
Test status
Simulation time 467535149 ps
CPU time 2.63 seconds
Started Jun 25 05:38:59 PM PDT 24
Finished Jun 25 05:39:04 PM PDT 24
Peak memory 208356 kb
Host smart-7d0cc5eb-70b1-463b-99da-26dc9ac542bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1824654092 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst.1824654092
Directory /workspace/35.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst_reset_race.60220078
Short name T462
Test name
Test status
Simulation time 208817028 ps
CPU time 1.4 seconds
Started Jun 25 05:38:58 PM PDT 24
Finished Jun 25 05:39:02 PM PDT 24
Peak memory 200008 kb
Host smart-68635cc8-5cc3-4498-9959-fb5cdedb8631
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60220078 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst_reset_race.60220078
Directory /workspace/35.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/36.rstmgr_alert_test.2002784668
Short name T411
Test name
Test status
Simulation time 167202053 ps
CPU time 0.94 seconds
Started Jun 25 05:39:05 PM PDT 24
Finished Jun 25 05:39:08 PM PDT 24
Peak memory 199884 kb
Host smart-c994830a-67b5-4847-ad2d-6736b32be430
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002784668 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_alert_test.2002784668
Directory /workspace/36.rstmgr_alert_test/latest

Test location /workspace/coverage/default/36.rstmgr_leaf_rst_cnsty.2013462087
Short name T207
Test name
Test status
Simulation time 1228914114 ps
CPU time 5.7 seconds
Started Jun 25 05:39:11 PM PDT 24
Finished Jun 25 05:39:17 PM PDT 24
Peak memory 221620 kb
Host smart-6ec74d2a-f32e-4d8d-98f2-13f4c5416dda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2013462087 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_cnsty.2013462087
Directory /workspace/36.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/36.rstmgr_leaf_rst_shadow_attack.1177360358
Short name T139
Test name
Test status
Simulation time 244666869 ps
CPU time 1.17 seconds
Started Jun 25 05:39:06 PM PDT 24
Finished Jun 25 05:39:10 PM PDT 24
Peak memory 217436 kb
Host smart-4c7f98a8-7c6d-4820-a449-a2ea3081c614
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1177360358 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_shadow_attack.1177360358
Directory /workspace/36.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/36.rstmgr_por_stretcher.2037834483
Short name T406
Test name
Test status
Simulation time 109658503 ps
CPU time 0.83 seconds
Started Jun 25 05:39:05 PM PDT 24
Finished Jun 25 05:39:08 PM PDT 24
Peak memory 199888 kb
Host smart-82b62ceb-1881-4d09-9784-f7d6ace8906c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2037834483 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_por_stretcher.2037834483
Directory /workspace/36.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/36.rstmgr_reset.251590411
Short name T157
Test name
Test status
Simulation time 1700755455 ps
CPU time 6.55 seconds
Started Jun 25 05:39:07 PM PDT 24
Finished Jun 25 05:39:16 PM PDT 24
Peak memory 200264 kb
Host smart-da9bce32-3917-4f07-879e-fc5032bf53b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=251590411 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_reset.251590411
Directory /workspace/36.rstmgr_reset/latest

Test location /workspace/coverage/default/36.rstmgr_sec_cm_scan_intersig_mubi.1659173798
Short name T305
Test name
Test status
Simulation time 155041699 ps
CPU time 1.07 seconds
Started Jun 25 05:39:05 PM PDT 24
Finished Jun 25 05:39:09 PM PDT 24
Peak memory 200084 kb
Host smart-d677e28f-5c3c-4d25-a995-92e93794849b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1659173798 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sec_cm_scan_intersig_mubi.1659173798
Directory /workspace/36.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/36.rstmgr_smoke.3527279989
Short name T52
Test name
Test status
Simulation time 122326689 ps
CPU time 1.24 seconds
Started Jun 25 05:39:05 PM PDT 24
Finished Jun 25 05:39:09 PM PDT 24
Peak memory 200308 kb
Host smart-5ff71040-9dfa-4fd6-a0c9-53bd93360ce7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3527279989 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_smoke.3527279989
Directory /workspace/36.rstmgr_smoke/latest

Test location /workspace/coverage/default/36.rstmgr_stress_all.1016166551
Short name T262
Test name
Test status
Simulation time 7847061517 ps
CPU time 38.13 seconds
Started Jun 25 05:39:05 PM PDT 24
Finished Jun 25 05:39:46 PM PDT 24
Peak memory 208592 kb
Host smart-4f88d695-06e2-4bb7-94ff-bdf968b438b2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016166551 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_stress_all.1016166551
Directory /workspace/36.rstmgr_stress_all/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst.1187419429
Short name T243
Test name
Test status
Simulation time 112870751 ps
CPU time 1.47 seconds
Started Jun 25 05:39:04 PM PDT 24
Finished Jun 25 05:39:07 PM PDT 24
Peak memory 200084 kb
Host smart-82946dee-3c94-438f-a4e6-b83d29429055
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1187419429 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst.1187419429
Directory /workspace/36.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst_reset_race.1752898537
Short name T203
Test name
Test status
Simulation time 218828332 ps
CPU time 1.44 seconds
Started Jun 25 05:39:05 PM PDT 24
Finished Jun 25 05:39:08 PM PDT 24
Peak memory 200100 kb
Host smart-84df2d6d-6ed0-4b8c-9a0b-7afdce1c9bad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1752898537 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst_reset_race.1752898537
Directory /workspace/36.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/37.rstmgr_alert_test.1535030623
Short name T517
Test name
Test status
Simulation time 79039904 ps
CPU time 0.85 seconds
Started Jun 25 05:39:05 PM PDT 24
Finished Jun 25 05:39:07 PM PDT 24
Peak memory 199816 kb
Host smart-b387d678-6ab1-46b2-96fc-115209ec34bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535030623 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_alert_test.1535030623
Directory /workspace/37.rstmgr_alert_test/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_cnsty.2336714491
Short name T417
Test name
Test status
Simulation time 2169008003 ps
CPU time 8.78 seconds
Started Jun 25 05:39:03 PM PDT 24
Finished Jun 25 05:39:13 PM PDT 24
Peak memory 216908 kb
Host smart-cd3505ff-2a46-4d2e-b988-5e4cd68d38fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2336714491 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_cnsty.2336714491
Directory /workspace/37.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_shadow_attack.4034847806
Short name T319
Test name
Test status
Simulation time 244664512 ps
CPU time 1.15 seconds
Started Jun 25 05:39:05 PM PDT 24
Finished Jun 25 05:39:08 PM PDT 24
Peak memory 217352 kb
Host smart-cb518ce3-b71e-4a73-a411-168fe7cce22b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4034847806 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_shadow_attack.4034847806
Directory /workspace/37.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/37.rstmgr_por_stretcher.1076012319
Short name T155
Test name
Test status
Simulation time 148573376 ps
CPU time 0.93 seconds
Started Jun 25 05:39:04 PM PDT 24
Finished Jun 25 05:39:07 PM PDT 24
Peak memory 199892 kb
Host smart-8c3b64e2-c4b3-431a-8f36-384048018511
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1076012319 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_por_stretcher.1076012319
Directory /workspace/37.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/37.rstmgr_reset.331042305
Short name T472
Test name
Test status
Simulation time 988083387 ps
CPU time 5.59 seconds
Started Jun 25 05:39:05 PM PDT 24
Finished Jun 25 05:39:13 PM PDT 24
Peak memory 200332 kb
Host smart-12a1c419-f419-4fa6-bb30-7475383303b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=331042305 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_reset.331042305
Directory /workspace/37.rstmgr_reset/latest

Test location /workspace/coverage/default/37.rstmgr_sec_cm_scan_intersig_mubi.659921779
Short name T527
Test name
Test status
Simulation time 103988696 ps
CPU time 0.98 seconds
Started Jun 25 05:39:03 PM PDT 24
Finished Jun 25 05:39:06 PM PDT 24
Peak memory 200060 kb
Host smart-6f115d57-40de-40e3-b79e-25f1d2cae776
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=659921779 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sec_cm_scan_intersig_mubi.659921779
Directory /workspace/37.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/37.rstmgr_smoke.2254656106
Short name T433
Test name
Test status
Simulation time 195121287 ps
CPU time 1.49 seconds
Started Jun 25 05:39:04 PM PDT 24
Finished Jun 25 05:39:07 PM PDT 24
Peak memory 200268 kb
Host smart-f4b6ac7a-09a7-482a-9f4e-a7b46213a09f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2254656106 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_smoke.2254656106
Directory /workspace/37.rstmgr_smoke/latest

Test location /workspace/coverage/default/37.rstmgr_stress_all.2378010808
Short name T539
Test name
Test status
Simulation time 2973636162 ps
CPU time 13.24 seconds
Started Jun 25 05:39:05 PM PDT 24
Finished Jun 25 05:39:20 PM PDT 24
Peak memory 210388 kb
Host smart-5c9232f2-9695-4858-9d32-efe44a95b9ce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378010808 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_stress_all.2378010808
Directory /workspace/37.rstmgr_stress_all/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst.3308948367
Short name T463
Test name
Test status
Simulation time 450619462 ps
CPU time 2.62 seconds
Started Jun 25 05:39:03 PM PDT 24
Finished Jun 25 05:39:07 PM PDT 24
Peak memory 200056 kb
Host smart-a86b7052-889c-45e0-a112-585802873234
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3308948367 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst.3308948367
Directory /workspace/37.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst_reset_race.1712892375
Short name T178
Test name
Test status
Simulation time 254197536 ps
CPU time 1.48 seconds
Started Jun 25 05:39:05 PM PDT 24
Finished Jun 25 05:39:09 PM PDT 24
Peak memory 200112 kb
Host smart-7468081b-b7ce-4fb8-a858-d52a443eab40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1712892375 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst_reset_race.1712892375
Directory /workspace/37.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_cnsty.470561837
Short name T240
Test name
Test status
Simulation time 1899704228 ps
CPU time 7.77 seconds
Started Jun 25 05:39:04 PM PDT 24
Finished Jun 25 05:39:14 PM PDT 24
Peak memory 217500 kb
Host smart-cdf4b40c-c51f-469a-8bd5-9a1cfa55f5e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=470561837 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_cnsty.470561837
Directory /workspace/38.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_shadow_attack.1454477282
Short name T125
Test name
Test status
Simulation time 244789493 ps
CPU time 1.08 seconds
Started Jun 25 05:39:03 PM PDT 24
Finished Jun 25 05:39:06 PM PDT 24
Peak memory 217448 kb
Host smart-fa139aee-15a1-435d-a952-fcfc013fb63b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1454477282 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_shadow_attack.1454477282
Directory /workspace/38.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/38.rstmgr_por_stretcher.2925007772
Short name T467
Test name
Test status
Simulation time 93040617 ps
CPU time 0.74 seconds
Started Jun 25 05:39:06 PM PDT 24
Finished Jun 25 05:39:09 PM PDT 24
Peak memory 199824 kb
Host smart-195dbe38-adc4-4c55-aab7-230d88c68fea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2925007772 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_por_stretcher.2925007772
Directory /workspace/38.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/38.rstmgr_reset.556858038
Short name T471
Test name
Test status
Simulation time 1479176859 ps
CPU time 5.62 seconds
Started Jun 25 05:39:08 PM PDT 24
Finished Jun 25 05:39:15 PM PDT 24
Peak memory 200264 kb
Host smart-d839e634-c292-4e9c-84a5-ca9299537d49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=556858038 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_reset.556858038
Directory /workspace/38.rstmgr_reset/latest

Test location /workspace/coverage/default/38.rstmgr_sec_cm_scan_intersig_mubi.421498919
Short name T380
Test name
Test status
Simulation time 157534142 ps
CPU time 1.22 seconds
Started Jun 25 05:39:04 PM PDT 24
Finished Jun 25 05:39:06 PM PDT 24
Peak memory 199984 kb
Host smart-4a721135-aa45-459e-a6ff-fc4d168ef328
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=421498919 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sec_cm_scan_intersig_mubi.421498919
Directory /workspace/38.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/38.rstmgr_smoke.3048956488
Short name T473
Test name
Test status
Simulation time 207539765 ps
CPU time 1.46 seconds
Started Jun 25 05:39:06 PM PDT 24
Finished Jun 25 05:39:10 PM PDT 24
Peak memory 200268 kb
Host smart-848f09cb-7dd5-4a27-9589-d4b796109d07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3048956488 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_smoke.3048956488
Directory /workspace/38.rstmgr_smoke/latest

Test location /workspace/coverage/default/38.rstmgr_stress_all.3834087783
Short name T313
Test name
Test status
Simulation time 8878776379 ps
CPU time 32.16 seconds
Started Jun 25 05:39:04 PM PDT 24
Finished Jun 25 05:39:37 PM PDT 24
Peak memory 208600 kb
Host smart-85cf1862-6e74-47fd-8df3-9d7bb599371f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834087783 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_stress_all.3834087783
Directory /workspace/38.rstmgr_stress_all/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst.4115012988
Short name T405
Test name
Test status
Simulation time 341277789 ps
CPU time 2.47 seconds
Started Jun 25 05:39:11 PM PDT 24
Finished Jun 25 05:39:14 PM PDT 24
Peak memory 200068 kb
Host smart-7a30de28-5e2a-4f91-a269-8b84bfdff775
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4115012988 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst.4115012988
Directory /workspace/38.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst_reset_race.3265215269
Short name T146
Test name
Test status
Simulation time 74368414 ps
CPU time 0.86 seconds
Started Jun 25 05:39:06 PM PDT 24
Finished Jun 25 05:39:09 PM PDT 24
Peak memory 200080 kb
Host smart-d3163dde-a199-4d40-82a7-f16c20a5b12e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3265215269 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst_reset_race.3265215269
Directory /workspace/38.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/39.rstmgr_alert_test.1252078028
Short name T205
Test name
Test status
Simulation time 57495366 ps
CPU time 0.73 seconds
Started Jun 25 05:39:06 PM PDT 24
Finished Jun 25 05:39:09 PM PDT 24
Peak memory 199796 kb
Host smart-4c48cd91-4920-4889-be66-ab7ace0080c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252078028 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_alert_test.1252078028
Directory /workspace/39.rstmgr_alert_test/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_cnsty.2886988447
Short name T483
Test name
Test status
Simulation time 1232663982 ps
CPU time 5.68 seconds
Started Jun 25 05:39:05 PM PDT 24
Finished Jun 25 05:39:13 PM PDT 24
Peak memory 217020 kb
Host smart-a07e48ed-97b6-4256-b897-88c4ec860dcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2886988447 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_cnsty.2886988447
Directory /workspace/39.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_shadow_attack.1670153150
Short name T277
Test name
Test status
Simulation time 243284741 ps
CPU time 1.11 seconds
Started Jun 25 05:39:03 PM PDT 24
Finished Jun 25 05:39:06 PM PDT 24
Peak memory 217456 kb
Host smart-d7f8a290-e0e9-4c63-a30b-53a642e99879
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1670153150 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_shadow_attack.1670153150
Directory /workspace/39.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/39.rstmgr_por_stretcher.4027315349
Short name T537
Test name
Test status
Simulation time 182282592 ps
CPU time 0.89 seconds
Started Jun 25 05:39:03 PM PDT 24
Finished Jun 25 05:39:06 PM PDT 24
Peak memory 199840 kb
Host smart-33186dd6-247d-48fb-aeeb-80268bbe06d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4027315349 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_por_stretcher.4027315349
Directory /workspace/39.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/39.rstmgr_reset.3547021818
Short name T535
Test name
Test status
Simulation time 2054427025 ps
CPU time 7.78 seconds
Started Jun 25 05:39:03 PM PDT 24
Finished Jun 25 05:39:12 PM PDT 24
Peak memory 200328 kb
Host smart-b5597add-b732-487f-8310-f8566cdff0eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3547021818 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_reset.3547021818
Directory /workspace/39.rstmgr_reset/latest

Test location /workspace/coverage/default/39.rstmgr_sec_cm_scan_intersig_mubi.2713202518
Short name T393
Test name
Test status
Simulation time 147108903 ps
CPU time 1.11 seconds
Started Jun 25 05:39:06 PM PDT 24
Finished Jun 25 05:39:09 PM PDT 24
Peak memory 200008 kb
Host smart-85aa4d9f-55f8-4bdc-9e51-bb249869ab99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2713202518 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sec_cm_scan_intersig_mubi.2713202518
Directory /workspace/39.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/39.rstmgr_smoke.2408940271
Short name T335
Test name
Test status
Simulation time 203536955 ps
CPU time 1.49 seconds
Started Jun 25 05:39:07 PM PDT 24
Finished Jun 25 05:39:10 PM PDT 24
Peak memory 200272 kb
Host smart-d2b07ff3-820a-4460-a56d-c8903a40a0ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2408940271 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_smoke.2408940271
Directory /workspace/39.rstmgr_smoke/latest

Test location /workspace/coverage/default/39.rstmgr_stress_all.2876153705
Short name T123
Test name
Test status
Simulation time 3566269807 ps
CPU time 14.75 seconds
Started Jun 25 05:39:04 PM PDT 24
Finished Jun 25 05:39:21 PM PDT 24
Peak memory 200404 kb
Host smart-32553a58-d67b-492e-be4a-cb9d92c13267
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876153705 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_stress_all.2876153705
Directory /workspace/39.rstmgr_stress_all/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst.2498911587
Short name T419
Test name
Test status
Simulation time 456825012 ps
CPU time 2.51 seconds
Started Jun 25 05:39:02 PM PDT 24
Finished Jun 25 05:39:06 PM PDT 24
Peak memory 200096 kb
Host smart-70516435-3e43-4148-b6c0-7e87a035e2f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2498911587 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst.2498911587
Directory /workspace/39.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst_reset_race.3565598521
Short name T466
Test name
Test status
Simulation time 91663023 ps
CPU time 0.94 seconds
Started Jun 25 05:39:05 PM PDT 24
Finished Jun 25 05:39:08 PM PDT 24
Peak memory 200084 kb
Host smart-448e5cac-7d37-4f89-ac4c-937a5f4d16bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3565598521 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst_reset_race.3565598521
Directory /workspace/39.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/4.rstmgr_alert_test.2206669958
Short name T361
Test name
Test status
Simulation time 66980526 ps
CPU time 0.78 seconds
Started Jun 25 05:38:00 PM PDT 24
Finished Jun 25 05:38:03 PM PDT 24
Peak memory 199892 kb
Host smart-e5a5b1d5-6c53-4744-ba6d-69bca496e080
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2206669958 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_alert_test.2206669958
Directory /workspace/4.rstmgr_alert_test/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_cnsty.1700336192
Short name T500
Test name
Test status
Simulation time 2179455685 ps
CPU time 8.7 seconds
Started Jun 25 05:37:58 PM PDT 24
Finished Jun 25 05:38:09 PM PDT 24
Peak memory 218028 kb
Host smart-55a1a032-f8f3-4bd8-a2ec-67ad0ad16412
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1700336192 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_cnsty.1700336192
Directory /workspace/4.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_shadow_attack.369672129
Short name T140
Test name
Test status
Simulation time 243953025 ps
CPU time 1.08 seconds
Started Jun 25 05:37:59 PM PDT 24
Finished Jun 25 05:38:03 PM PDT 24
Peak memory 217472 kb
Host smart-2b4a03b8-6d8c-4aaf-bae4-b8bd12af0f38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=369672129 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_shadow_attack.369672129
Directory /workspace/4.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/4.rstmgr_por_stretcher.3087729764
Short name T17
Test name
Test status
Simulation time 223406046 ps
CPU time 1.02 seconds
Started Jun 25 05:37:58 PM PDT 24
Finished Jun 25 05:38:02 PM PDT 24
Peak memory 199744 kb
Host smart-37b86b9c-0fb3-4902-a4df-e48efc9c7d33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3087729764 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_por_stretcher.3087729764
Directory /workspace/4.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/4.rstmgr_reset.1828077537
Short name T197
Test name
Test status
Simulation time 1097623558 ps
CPU time 5.02 seconds
Started Jun 25 05:37:54 PM PDT 24
Finished Jun 25 05:38:00 PM PDT 24
Peak memory 200320 kb
Host smart-9ec9ac56-7b78-44f5-a08e-fcb179674a34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1828077537 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_reset.1828077537
Directory /workspace/4.rstmgr_reset/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm_scan_intersig_mubi.93413205
Short name T223
Test name
Test status
Simulation time 177153983 ps
CPU time 1.2 seconds
Started Jun 25 05:37:59 PM PDT 24
Finished Jun 25 05:38:03 PM PDT 24
Peak memory 200324 kb
Host smart-201efb56-71bd-4170-911b-be426feea106
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93413205 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm_scan_intersig_mubi.93413205
Directory /workspace/4.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/4.rstmgr_smoke.2835925972
Short name T289
Test name
Test status
Simulation time 200371251 ps
CPU time 1.38 seconds
Started Jun 25 05:37:55 PM PDT 24
Finished Jun 25 05:37:58 PM PDT 24
Peak memory 200200 kb
Host smart-19f2e392-6c96-4e90-a4cc-61b2f4b88307
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2835925972 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_smoke.2835925972
Directory /workspace/4.rstmgr_smoke/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst.1531541326
Short name T430
Test name
Test status
Simulation time 385203630 ps
CPU time 2.54 seconds
Started Jun 25 05:37:56 PM PDT 24
Finished Jun 25 05:38:00 PM PDT 24
Peak memory 200072 kb
Host smart-91bb71d2-a1c7-454c-9e3d-6cd4d2ed010d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1531541326 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst.1531541326
Directory /workspace/4.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst_reset_race.4268458388
Short name T70
Test name
Test status
Simulation time 138122841 ps
CPU time 1.18 seconds
Started Jun 25 05:37:59 PM PDT 24
Finished Jun 25 05:38:03 PM PDT 24
Peak memory 199924 kb
Host smart-192332bf-9631-4446-850d-d488064b1d56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4268458388 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst_reset_race.4268458388
Directory /workspace/4.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/40.rstmgr_alert_test.4184710613
Short name T244
Test name
Test status
Simulation time 77781085 ps
CPU time 0.82 seconds
Started Jun 25 05:39:16 PM PDT 24
Finished Jun 25 05:39:19 PM PDT 24
Peak memory 199868 kb
Host smart-582e6c09-ca9a-4440-8d78-e6fec8da2c96
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184710613 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_alert_test.4184710613
Directory /workspace/40.rstmgr_alert_test/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_cnsty.4208560988
Short name T333
Test name
Test status
Simulation time 1871579629 ps
CPU time 7.63 seconds
Started Jun 25 05:39:06 PM PDT 24
Finished Jun 25 05:39:16 PM PDT 24
Peak memory 221564 kb
Host smart-09c2f694-2056-478f-8d01-5d1f66092e2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4208560988 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_cnsty.4208560988
Directory /workspace/40.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_shadow_attack.119404727
Short name T295
Test name
Test status
Simulation time 245154369 ps
CPU time 1.08 seconds
Started Jun 25 05:39:05 PM PDT 24
Finished Jun 25 05:39:08 PM PDT 24
Peak memory 217440 kb
Host smart-899d0fc0-4b05-4820-9c75-ce1aa7a7dbc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=119404727 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_shadow_attack.119404727
Directory /workspace/40.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/40.rstmgr_por_stretcher.2570089546
Short name T20
Test name
Test status
Simulation time 167581059 ps
CPU time 0.86 seconds
Started Jun 25 05:39:06 PM PDT 24
Finished Jun 25 05:39:09 PM PDT 24
Peak memory 199848 kb
Host smart-49934d58-f6bf-441b-8b5d-27ca0cc8fcc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2570089546 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_por_stretcher.2570089546
Directory /workspace/40.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/40.rstmgr_reset.2393653993
Short name T228
Test name
Test status
Simulation time 844163101 ps
CPU time 4.67 seconds
Started Jun 25 05:39:08 PM PDT 24
Finished Jun 25 05:39:14 PM PDT 24
Peak memory 200340 kb
Host smart-dd069726-fce7-486c-b13f-c4c3fa002628
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2393653993 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_reset.2393653993
Directory /workspace/40.rstmgr_reset/latest

Test location /workspace/coverage/default/40.rstmgr_sec_cm_scan_intersig_mubi.981615992
Short name T503
Test name
Test status
Simulation time 171819267 ps
CPU time 1.2 seconds
Started Jun 25 05:39:03 PM PDT 24
Finished Jun 25 05:39:05 PM PDT 24
Peak memory 200084 kb
Host smart-1e7a375f-f081-4749-94dc-488c70b34c3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=981615992 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sec_cm_scan_intersig_mubi.981615992
Directory /workspace/40.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/40.rstmgr_smoke.3698350099
Short name T183
Test name
Test status
Simulation time 116904228 ps
CPU time 1.31 seconds
Started Jun 25 05:39:05 PM PDT 24
Finished Jun 25 05:39:09 PM PDT 24
Peak memory 200192 kb
Host smart-4ceb5237-6057-4707-b59a-f1edc8fa10f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3698350099 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_smoke.3698350099
Directory /workspace/40.rstmgr_smoke/latest

Test location /workspace/coverage/default/40.rstmgr_stress_all.638610913
Short name T427
Test name
Test status
Simulation time 10978826818 ps
CPU time 40.68 seconds
Started Jun 25 05:39:19 PM PDT 24
Finished Jun 25 05:40:01 PM PDT 24
Peak memory 200412 kb
Host smart-7140a158-06ad-486e-8645-320c62191f13
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638610913 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_stress_all.638610913
Directory /workspace/40.rstmgr_stress_all/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst.1418146609
Short name T327
Test name
Test status
Simulation time 478077705 ps
CPU time 2.95 seconds
Started Jun 25 05:39:07 PM PDT 24
Finished Jun 25 05:39:12 PM PDT 24
Peak memory 200080 kb
Host smart-c8229309-384a-420f-9113-ee0aec8fcccb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1418146609 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst.1418146609
Directory /workspace/40.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst_reset_race.1580202478
Short name T456
Test name
Test status
Simulation time 182197728 ps
CPU time 1.3 seconds
Started Jun 25 05:39:07 PM PDT 24
Finished Jun 25 05:39:10 PM PDT 24
Peak memory 200064 kb
Host smart-34baa24b-9aa1-4c29-afde-3aa5d7c23d61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1580202478 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst_reset_race.1580202478
Directory /workspace/40.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/41.rstmgr_alert_test.609337569
Short name T273
Test name
Test status
Simulation time 75777293 ps
CPU time 0.81 seconds
Started Jun 25 05:39:16 PM PDT 24
Finished Jun 25 05:39:19 PM PDT 24
Peak memory 199796 kb
Host smart-02791018-ffe8-41c6-9794-403401c20294
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609337569 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_alert_test.609337569
Directory /workspace/41.rstmgr_alert_test/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_cnsty.2340893907
Short name T44
Test name
Test status
Simulation time 2346130397 ps
CPU time 8.22 seconds
Started Jun 25 05:39:18 PM PDT 24
Finished Jun 25 05:39:28 PM PDT 24
Peak memory 220832 kb
Host smart-51b3ff86-9c05-4f1d-a4f4-60d2c345f7db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2340893907 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_cnsty.2340893907
Directory /workspace/41.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_shadow_attack.1341170795
Short name T356
Test name
Test status
Simulation time 244152709 ps
CPU time 1.23 seconds
Started Jun 25 05:39:18 PM PDT 24
Finished Jun 25 05:39:21 PM PDT 24
Peak memory 217316 kb
Host smart-40e80cb6-5f2a-4f2a-97c1-c92e5d8d1766
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1341170795 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_shadow_attack.1341170795
Directory /workspace/41.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/41.rstmgr_por_stretcher.834942123
Short name T238
Test name
Test status
Simulation time 114916674 ps
CPU time 0.79 seconds
Started Jun 25 05:39:15 PM PDT 24
Finished Jun 25 05:39:17 PM PDT 24
Peak memory 200124 kb
Host smart-8f4d4607-9e0e-4472-a5b9-ec38adff381f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=834942123 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_por_stretcher.834942123
Directory /workspace/41.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/41.rstmgr_reset.2498856674
Short name T105
Test name
Test status
Simulation time 1046043070 ps
CPU time 5.23 seconds
Started Jun 25 05:39:17 PM PDT 24
Finished Jun 25 05:39:25 PM PDT 24
Peak memory 200356 kb
Host smart-f57d5fb4-4eb8-46fe-9ea4-180649ec47b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2498856674 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_reset.2498856674
Directory /workspace/41.rstmgr_reset/latest

Test location /workspace/coverage/default/41.rstmgr_sec_cm_scan_intersig_mubi.2121798540
Short name T200
Test name
Test status
Simulation time 171904927 ps
CPU time 1.27 seconds
Started Jun 25 05:39:18 PM PDT 24
Finished Jun 25 05:39:22 PM PDT 24
Peak memory 200084 kb
Host smart-701d9657-9abd-404a-8294-7e5adebb14dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2121798540 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sec_cm_scan_intersig_mubi.2121798540
Directory /workspace/41.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/41.rstmgr_smoke.1599916908
Short name T468
Test name
Test status
Simulation time 194903511 ps
CPU time 1.42 seconds
Started Jun 25 05:39:16 PM PDT 24
Finished Jun 25 05:39:19 PM PDT 24
Peak memory 200196 kb
Host smart-2ca61049-f469-49f9-bafd-f7d8ed402f26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1599916908 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_smoke.1599916908
Directory /workspace/41.rstmgr_smoke/latest

Test location /workspace/coverage/default/41.rstmgr_stress_all.4053370462
Short name T119
Test name
Test status
Simulation time 11025913901 ps
CPU time 38.2 seconds
Started Jun 25 05:39:17 PM PDT 24
Finished Jun 25 05:39:57 PM PDT 24
Peak memory 210292 kb
Host smart-59caf87d-0c69-4fe7-ab86-69f9c9ddb109
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053370462 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_stress_all.4053370462
Directory /workspace/41.rstmgr_stress_all/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst_reset_race.862675875
Short name T136
Test name
Test status
Simulation time 89737839 ps
CPU time 0.97 seconds
Started Jun 25 05:39:16 PM PDT 24
Finished Jun 25 05:39:18 PM PDT 24
Peak memory 200076 kb
Host smart-5f0aa3b1-c011-4ffc-91fc-952e60bbd38f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=862675875 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst_reset_race.862675875
Directory /workspace/41.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/42.rstmgr_alert_test.627354803
Short name T126
Test name
Test status
Simulation time 72410870 ps
CPU time 0.82 seconds
Started Jun 25 05:39:15 PM PDT 24
Finished Jun 25 05:39:17 PM PDT 24
Peak memory 199792 kb
Host smart-eda8fc19-8b6b-4ae4-8edb-37144e11ad81
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627354803 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_alert_test.627354803
Directory /workspace/42.rstmgr_alert_test/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_cnsty.978028292
Short name T30
Test name
Test status
Simulation time 2162094113 ps
CPU time 7.95 seconds
Started Jun 25 05:39:16 PM PDT 24
Finished Jun 25 05:39:25 PM PDT 24
Peak memory 217696 kb
Host smart-77fa614a-0c4b-418b-b252-315c6f311deb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=978028292 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_cnsty.978028292
Directory /workspace/42.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_shadow_attack.1868093570
Short name T366
Test name
Test status
Simulation time 243203934 ps
CPU time 1.17 seconds
Started Jun 25 05:39:21 PM PDT 24
Finished Jun 25 05:39:24 PM PDT 24
Peak memory 217428 kb
Host smart-75fc3340-e9f0-4bdb-874c-36720c3c0be8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1868093570 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_shadow_attack.1868093570
Directory /workspace/42.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/42.rstmgr_por_stretcher.2482903958
Short name T8
Test name
Test status
Simulation time 127910203 ps
CPU time 0.86 seconds
Started Jun 25 05:39:15 PM PDT 24
Finished Jun 25 05:39:17 PM PDT 24
Peak memory 199908 kb
Host smart-62a4e71f-6918-4990-a10e-0144d3567d47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2482903958 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_por_stretcher.2482903958
Directory /workspace/42.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/42.rstmgr_reset.1521042988
Short name T212
Test name
Test status
Simulation time 906085866 ps
CPU time 4.61 seconds
Started Jun 25 05:39:16 PM PDT 24
Finished Jun 25 05:39:22 PM PDT 24
Peak memory 200340 kb
Host smart-6425bb2b-1505-4260-a32a-2da1a6dffd33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1521042988 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_reset.1521042988
Directory /workspace/42.rstmgr_reset/latest

Test location /workspace/coverage/default/42.rstmgr_sec_cm_scan_intersig_mubi.1164038077
Short name T508
Test name
Test status
Simulation time 136694430 ps
CPU time 1.18 seconds
Started Jun 25 05:39:17 PM PDT 24
Finished Jun 25 05:39:20 PM PDT 24
Peak memory 200064 kb
Host smart-8d341bd5-7189-474f-af6f-48a5167672b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1164038077 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sec_cm_scan_intersig_mubi.1164038077
Directory /workspace/42.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/42.rstmgr_smoke.1922034961
Short name T266
Test name
Test status
Simulation time 219244762 ps
CPU time 1.45 seconds
Started Jun 25 05:39:21 PM PDT 24
Finished Jun 25 05:39:24 PM PDT 24
Peak memory 200256 kb
Host smart-c141e97d-648a-4f4f-acbd-2bd62d2ef793
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1922034961 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_smoke.1922034961
Directory /workspace/42.rstmgr_smoke/latest

Test location /workspace/coverage/default/42.rstmgr_stress_all.441594028
Short name T269
Test name
Test status
Simulation time 15948040295 ps
CPU time 60.21 seconds
Started Jun 25 05:39:18 PM PDT 24
Finished Jun 25 05:40:20 PM PDT 24
Peak memory 208612 kb
Host smart-d9eedc97-4961-4053-9c65-c7e55a9a7fd9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441594028 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_stress_all.441594028
Directory /workspace/42.rstmgr_stress_all/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst.3593191017
Short name T129
Test name
Test status
Simulation time 446745270 ps
CPU time 2.38 seconds
Started Jun 25 05:39:18 PM PDT 24
Finished Jun 25 05:39:22 PM PDT 24
Peak memory 199184 kb
Host smart-da2035a1-fd43-409d-add0-bf99fb933d8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3593191017 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst.3593191017
Directory /workspace/42.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst_reset_race.505150409
Short name T480
Test name
Test status
Simulation time 218248608 ps
CPU time 1.38 seconds
Started Jun 25 05:39:17 PM PDT 24
Finished Jun 25 05:39:21 PM PDT 24
Peak memory 200092 kb
Host smart-cfb84956-b6d1-4587-88cb-d6bc25163155
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=505150409 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst_reset_race.505150409
Directory /workspace/42.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/43.rstmgr_alert_test.3882138382
Short name T311
Test name
Test status
Simulation time 77898623 ps
CPU time 0.81 seconds
Started Jun 25 05:39:16 PM PDT 24
Finished Jun 25 05:39:18 PM PDT 24
Peak memory 199864 kb
Host smart-8a9d15bf-5dfa-46a5-98c5-ecf46d9c6bf6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3882138382 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_alert_test.3882138382
Directory /workspace/43.rstmgr_alert_test/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_cnsty.2159264546
Short name T25
Test name
Test status
Simulation time 2370002074 ps
CPU time 8.44 seconds
Started Jun 25 05:39:20 PM PDT 24
Finished Jun 25 05:39:30 PM PDT 24
Peak memory 217852 kb
Host smart-fc05d191-b45e-4f15-9d7a-0eb8c8eaa37a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2159264546 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_cnsty.2159264546
Directory /workspace/43.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_shadow_attack.3625595573
Short name T428
Test name
Test status
Simulation time 243863048 ps
CPU time 1.08 seconds
Started Jun 25 05:39:18 PM PDT 24
Finished Jun 25 05:39:21 PM PDT 24
Peak memory 217452 kb
Host smart-a566f720-7c27-4756-95bb-050946ac2ed2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3625595573 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_shadow_attack.3625595573
Directory /workspace/43.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/43.rstmgr_por_stretcher.710239944
Short name T142
Test name
Test status
Simulation time 128369908 ps
CPU time 0.85 seconds
Started Jun 25 05:39:16 PM PDT 24
Finished Jun 25 05:39:19 PM PDT 24
Peak memory 199884 kb
Host smart-820191cf-b860-42b9-9727-6726423c35e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=710239944 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_por_stretcher.710239944
Directory /workspace/43.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/43.rstmgr_reset.4114301639
Short name T122
Test name
Test status
Simulation time 1975459167 ps
CPU time 6.94 seconds
Started Jun 25 05:39:15 PM PDT 24
Finished Jun 25 05:39:23 PM PDT 24
Peak memory 200340 kb
Host smart-4475da9a-db94-4fd2-8b58-aa2c08094a34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4114301639 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_reset.4114301639
Directory /workspace/43.rstmgr_reset/latest

Test location /workspace/coverage/default/43.rstmgr_sec_cm_scan_intersig_mubi.4045854647
Short name T184
Test name
Test status
Simulation time 100950057 ps
CPU time 1.02 seconds
Started Jun 25 05:39:20 PM PDT 24
Finished Jun 25 05:39:23 PM PDT 24
Peak memory 200072 kb
Host smart-ebbca042-ec61-4b2c-8f79-2b168381343b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4045854647 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sec_cm_scan_intersig_mubi.4045854647
Directory /workspace/43.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/43.rstmgr_smoke.1549190540
Short name T199
Test name
Test status
Simulation time 189444880 ps
CPU time 1.41 seconds
Started Jun 25 05:39:15 PM PDT 24
Finished Jun 25 05:39:17 PM PDT 24
Peak memory 200204 kb
Host smart-3a75a6fd-41a0-4579-a08b-c5f8fbf13778
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1549190540 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_smoke.1549190540
Directory /workspace/43.rstmgr_smoke/latest

Test location /workspace/coverage/default/43.rstmgr_stress_all.2402433651
Short name T233
Test name
Test status
Simulation time 7163127379 ps
CPU time 31.85 seconds
Started Jun 25 05:39:17 PM PDT 24
Finished Jun 25 05:39:51 PM PDT 24
Peak memory 200340 kb
Host smart-19819cc1-9ef8-481a-a438-a7c29f53936d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402433651 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_stress_all.2402433651
Directory /workspace/43.rstmgr_stress_all/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst.112555110
Short name T193
Test name
Test status
Simulation time 151913774 ps
CPU time 1.84 seconds
Started Jun 25 05:39:17 PM PDT 24
Finished Jun 25 05:39:21 PM PDT 24
Peak memory 200076 kb
Host smart-61e8b796-16fc-4cb5-bc8f-249936378a18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112555110 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst.112555110
Directory /workspace/43.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst_reset_race.532173473
Short name T283
Test name
Test status
Simulation time 138779337 ps
CPU time 1.11 seconds
Started Jun 25 05:39:20 PM PDT 24
Finished Jun 25 05:39:23 PM PDT 24
Peak memory 200100 kb
Host smart-120b042e-18a3-4ea1-a38a-2305c72b344b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=532173473 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst_reset_race.532173473
Directory /workspace/43.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/44.rstmgr_alert_test.2647129262
Short name T315
Test name
Test status
Simulation time 72874066 ps
CPU time 0.8 seconds
Started Jun 25 05:39:17 PM PDT 24
Finished Jun 25 05:39:20 PM PDT 24
Peak memory 199896 kb
Host smart-478e62a6-ae0e-4a68-9070-8aaf5a3c942b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647129262 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_alert_test.2647129262
Directory /workspace/44.rstmgr_alert_test/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_shadow_attack.1059384900
Short name T48
Test name
Test status
Simulation time 245572833 ps
CPU time 1.11 seconds
Started Jun 25 05:39:16 PM PDT 24
Finished Jun 25 05:39:19 PM PDT 24
Peak memory 218308 kb
Host smart-0a185944-75f2-4f6d-8355-8b00967330e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1059384900 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_shadow_attack.1059384900
Directory /workspace/44.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/44.rstmgr_por_stretcher.385244702
Short name T5
Test name
Test status
Simulation time 222364658 ps
CPU time 0.93 seconds
Started Jun 25 05:39:16 PM PDT 24
Finished Jun 25 05:39:19 PM PDT 24
Peak memory 199896 kb
Host smart-ea652733-1475-4fa3-81eb-91ed90c7b738
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=385244702 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_por_stretcher.385244702
Directory /workspace/44.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/44.rstmgr_reset.1538770020
Short name T321
Test name
Test status
Simulation time 977296526 ps
CPU time 4.96 seconds
Started Jun 25 05:39:14 PM PDT 24
Finished Jun 25 05:39:20 PM PDT 24
Peak memory 200304 kb
Host smart-be9f73d7-a02f-4990-b17f-a662af6bb8ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1538770020 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_reset.1538770020
Directory /workspace/44.rstmgr_reset/latest

Test location /workspace/coverage/default/44.rstmgr_sec_cm_scan_intersig_mubi.2581274092
Short name T301
Test name
Test status
Simulation time 105902907 ps
CPU time 1.01 seconds
Started Jun 25 05:39:15 PM PDT 24
Finished Jun 25 05:39:18 PM PDT 24
Peak memory 200084 kb
Host smart-a1646c5f-f59d-43bb-a5cc-400242b79e9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2581274092 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sec_cm_scan_intersig_mubi.2581274092
Directory /workspace/44.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/44.rstmgr_smoke.1713096123
Short name T234
Test name
Test status
Simulation time 227230982 ps
CPU time 1.63 seconds
Started Jun 25 05:39:15 PM PDT 24
Finished Jun 25 05:39:18 PM PDT 24
Peak memory 200272 kb
Host smart-6c58ab61-980b-407e-b1eb-30feb2b6a5bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1713096123 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_smoke.1713096123
Directory /workspace/44.rstmgr_smoke/latest

Test location /workspace/coverage/default/44.rstmgr_stress_all.2492074541
Short name T459
Test name
Test status
Simulation time 3485259412 ps
CPU time 18.52 seconds
Started Jun 25 05:39:15 PM PDT 24
Finished Jun 25 05:39:35 PM PDT 24
Peak memory 208580 kb
Host smart-50f4a034-b988-485f-b0b5-44de0890f311
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492074541 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_stress_all.2492074541
Directory /workspace/44.rstmgr_stress_all/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst.2203982193
Short name T445
Test name
Test status
Simulation time 273073372 ps
CPU time 1.84 seconds
Started Jun 25 05:39:16 PM PDT 24
Finished Jun 25 05:39:19 PM PDT 24
Peak memory 200060 kb
Host smart-9c51c5a6-319c-4f41-acc6-13ec09c4c987
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2203982193 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst.2203982193
Directory /workspace/44.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst_reset_race.3275755886
Short name T222
Test name
Test status
Simulation time 95915208 ps
CPU time 0.94 seconds
Started Jun 25 05:39:19 PM PDT 24
Finished Jun 25 05:39:22 PM PDT 24
Peak memory 200084 kb
Host smart-1e8e2049-a793-44e9-b1f0-d517aeb333b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3275755886 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst_reset_race.3275755886
Directory /workspace/44.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/45.rstmgr_alert_test.3847765884
Short name T512
Test name
Test status
Simulation time 66619698 ps
CPU time 0.77 seconds
Started Jun 25 05:39:20 PM PDT 24
Finished Jun 25 05:39:23 PM PDT 24
Peak memory 199892 kb
Host smart-499e4182-89eb-4843-86ba-6c29d43bba3f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847765884 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_alert_test.3847765884
Directory /workspace/45.rstmgr_alert_test/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_cnsty.234251887
Short name T45
Test name
Test status
Simulation time 2193340010 ps
CPU time 7.43 seconds
Started Jun 25 05:39:16 PM PDT 24
Finished Jun 25 05:39:26 PM PDT 24
Peak memory 217816 kb
Host smart-beed32df-f7f0-4ed4-a2eb-9cc798bd30ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=234251887 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_cnsty.234251887
Directory /workspace/45.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_shadow_attack.1989791238
Short name T352
Test name
Test status
Simulation time 244190320 ps
CPU time 1.12 seconds
Started Jun 25 05:39:17 PM PDT 24
Finished Jun 25 05:39:21 PM PDT 24
Peak memory 217440 kb
Host smart-fd7b588d-770e-453b-8a38-6296ba153684
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1989791238 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_shadow_attack.1989791238
Directory /workspace/45.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/45.rstmgr_por_stretcher.1832239244
Short name T324
Test name
Test status
Simulation time 98359387 ps
CPU time 0.8 seconds
Started Jun 25 05:39:16 PM PDT 24
Finished Jun 25 05:39:19 PM PDT 24
Peak memory 199892 kb
Host smart-2e1f54d2-3681-4b00-aec3-f860b450b47b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1832239244 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_por_stretcher.1832239244
Directory /workspace/45.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/45.rstmgr_reset.4092026686
Short name T363
Test name
Test status
Simulation time 1377954687 ps
CPU time 5.43 seconds
Started Jun 25 05:39:16 PM PDT 24
Finished Jun 25 05:39:24 PM PDT 24
Peak memory 200332 kb
Host smart-266af5e2-f5d1-4167-bb6f-f7fb3358c3ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4092026686 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_reset.4092026686
Directory /workspace/45.rstmgr_reset/latest

Test location /workspace/coverage/default/45.rstmgr_sec_cm_scan_intersig_mubi.407700787
Short name T167
Test name
Test status
Simulation time 99828950 ps
CPU time 1 seconds
Started Jun 25 05:39:17 PM PDT 24
Finished Jun 25 05:39:20 PM PDT 24
Peak memory 200020 kb
Host smart-20d8cfa9-94ec-4e5c-9909-476c8729d65d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=407700787 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sec_cm_scan_intersig_mubi.407700787
Directory /workspace/45.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/45.rstmgr_smoke.3256674798
Short name T485
Test name
Test status
Simulation time 116940732 ps
CPU time 1.24 seconds
Started Jun 25 05:39:14 PM PDT 24
Finished Jun 25 05:39:17 PM PDT 24
Peak memory 200268 kb
Host smart-c603ea5d-4c87-4a37-aef1-a9ce29d56be4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3256674798 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_smoke.3256674798
Directory /workspace/45.rstmgr_smoke/latest

Test location /workspace/coverage/default/45.rstmgr_stress_all.643140219
Short name T74
Test name
Test status
Simulation time 4337473368 ps
CPU time 18.47 seconds
Started Jun 25 05:39:17 PM PDT 24
Finished Jun 25 05:39:38 PM PDT 24
Peak memory 210388 kb
Host smart-16bae10a-4106-4a46-be0b-2a3ab9ec9734
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643140219 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_stress_all.643140219
Directory /workspace/45.rstmgr_stress_all/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst.3239970437
Short name T461
Test name
Test status
Simulation time 438208617 ps
CPU time 2.82 seconds
Started Jun 25 05:39:18 PM PDT 24
Finished Jun 25 05:39:23 PM PDT 24
Peak memory 200076 kb
Host smart-9aee1a82-2ff7-4c3f-bc3b-13246862ddbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3239970437 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst.3239970437
Directory /workspace/45.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst_reset_race.3939933353
Short name T131
Test name
Test status
Simulation time 139037194 ps
CPU time 1.09 seconds
Started Jun 25 05:39:22 PM PDT 24
Finished Jun 25 05:39:25 PM PDT 24
Peak memory 200092 kb
Host smart-9d31215a-aa5e-47fe-a889-4c14ccd2e3ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3939933353 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst_reset_race.3939933353
Directory /workspace/45.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/46.rstmgr_alert_test.3158149433
Short name T148
Test name
Test status
Simulation time 64688018 ps
CPU time 0.77 seconds
Started Jun 25 05:39:21 PM PDT 24
Finished Jun 25 05:39:24 PM PDT 24
Peak memory 199864 kb
Host smart-5148a85a-c820-42a2-a270-510bbf6bb689
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158149433 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_alert_test.3158149433
Directory /workspace/46.rstmgr_alert_test/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_cnsty.267508725
Short name T492
Test name
Test status
Simulation time 1233454749 ps
CPU time 6.19 seconds
Started Jun 25 05:39:14 PM PDT 24
Finished Jun 25 05:39:21 PM PDT 24
Peak memory 217760 kb
Host smart-4a931c5f-63b7-40ca-9040-950a923f393e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=267508725 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_cnsty.267508725
Directory /workspace/46.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_shadow_attack.1758409497
Short name T35
Test name
Test status
Simulation time 243873253 ps
CPU time 1.16 seconds
Started Jun 25 05:39:19 PM PDT 24
Finished Jun 25 05:39:22 PM PDT 24
Peak memory 217448 kb
Host smart-ffd4eeec-d1ba-474c-83ee-e4a7cdce01cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1758409497 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_shadow_attack.1758409497
Directory /workspace/46.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/46.rstmgr_por_stretcher.3270992112
Short name T272
Test name
Test status
Simulation time 199487793 ps
CPU time 0.87 seconds
Started Jun 25 05:39:16 PM PDT 24
Finished Jun 25 05:39:18 PM PDT 24
Peak memory 199884 kb
Host smart-81c372df-8f99-4f13-ad15-480a48297cb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3270992112 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_por_stretcher.3270992112
Directory /workspace/46.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/46.rstmgr_reset.2682679132
Short name T376
Test name
Test status
Simulation time 1378573544 ps
CPU time 5.37 seconds
Started Jun 25 05:39:21 PM PDT 24
Finished Jun 25 05:39:28 PM PDT 24
Peak memory 200372 kb
Host smart-a49e387b-1eaa-4097-a8a2-e215ed76aa76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2682679132 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_reset.2682679132
Directory /workspace/46.rstmgr_reset/latest

Test location /workspace/coverage/default/46.rstmgr_sec_cm_scan_intersig_mubi.939860126
Short name T416
Test name
Test status
Simulation time 109780670 ps
CPU time 1.12 seconds
Started Jun 25 05:39:20 PM PDT 24
Finished Jun 25 05:39:23 PM PDT 24
Peak memory 200084 kb
Host smart-5aee2457-0063-401c-b42c-27fcde5215ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=939860126 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sec_cm_scan_intersig_mubi.939860126
Directory /workspace/46.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/46.rstmgr_smoke.3556683417
Short name T402
Test name
Test status
Simulation time 258664900 ps
CPU time 1.62 seconds
Started Jun 25 05:39:16 PM PDT 24
Finished Jun 25 05:39:20 PM PDT 24
Peak memory 200284 kb
Host smart-a29d8add-5031-46d4-bab6-b61ebee1823f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3556683417 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_smoke.3556683417
Directory /workspace/46.rstmgr_smoke/latest

Test location /workspace/coverage/default/46.rstmgr_stress_all.2777439412
Short name T515
Test name
Test status
Simulation time 1437961560 ps
CPU time 6.28 seconds
Started Jun 25 05:39:20 PM PDT 24
Finished Jun 25 05:39:28 PM PDT 24
Peak memory 200332 kb
Host smart-5c5859b3-23ea-4923-9126-1b992cd5bb71
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777439412 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_stress_all.2777439412
Directory /workspace/46.rstmgr_stress_all/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst.2769678143
Short name T130
Test name
Test status
Simulation time 484960121 ps
CPU time 2.78 seconds
Started Jun 25 05:39:15 PM PDT 24
Finished Jun 25 05:39:20 PM PDT 24
Peak memory 200084 kb
Host smart-1c27447e-b370-4bfe-82af-13fdf70bd8fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2769678143 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst.2769678143
Directory /workspace/46.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst_reset_race.2861264038
Short name T308
Test name
Test status
Simulation time 285614152 ps
CPU time 1.55 seconds
Started Jun 25 05:39:19 PM PDT 24
Finished Jun 25 05:39:23 PM PDT 24
Peak memory 200288 kb
Host smart-13232bed-1760-4c78-a2b6-5050e06b821c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2861264038 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst_reset_race.2861264038
Directory /workspace/46.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/47.rstmgr_alert_test.816964716
Short name T275
Test name
Test status
Simulation time 70902741 ps
CPU time 0.84 seconds
Started Jun 25 05:39:16 PM PDT 24
Finished Jun 25 05:39:18 PM PDT 24
Peak memory 199868 kb
Host smart-b0028990-107c-45f7-83b1-78394bbd0fd5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816964716 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_alert_test.816964716
Directory /workspace/47.rstmgr_alert_test/latest

Test location /workspace/coverage/default/47.rstmgr_leaf_rst_cnsty.4247166424
Short name T258
Test name
Test status
Simulation time 1220835403 ps
CPU time 6.43 seconds
Started Jun 25 05:39:21 PM PDT 24
Finished Jun 25 05:39:29 PM PDT 24
Peak memory 217720 kb
Host smart-7c68abd9-4a89-4636-8fbc-9f416eef3ac6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4247166424 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_cnsty.4247166424
Directory /workspace/47.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/47.rstmgr_leaf_rst_shadow_attack.975285965
Short name T362
Test name
Test status
Simulation time 244371144 ps
CPU time 1.12 seconds
Started Jun 25 05:39:22 PM PDT 24
Finished Jun 25 05:39:25 PM PDT 24
Peak memory 217448 kb
Host smart-b20e19fa-166a-4605-ad0d-97cc40b2c713
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=975285965 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_shadow_attack.975285965
Directory /workspace/47.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/47.rstmgr_por_stretcher.1241849628
Short name T342
Test name
Test status
Simulation time 164733373 ps
CPU time 0.87 seconds
Started Jun 25 05:39:17 PM PDT 24
Finished Jun 25 05:39:20 PM PDT 24
Peak memory 199828 kb
Host smart-a91fae00-a90c-4d7f-9d45-7d31c4162930
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1241849628 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_por_stretcher.1241849628
Directory /workspace/47.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/47.rstmgr_reset.3060827439
Short name T386
Test name
Test status
Simulation time 1434740964 ps
CPU time 5.69 seconds
Started Jun 25 05:39:24 PM PDT 24
Finished Jun 25 05:39:32 PM PDT 24
Peak memory 200328 kb
Host smart-99a28e3d-dfdb-44fd-bb2b-cc254f76b510
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3060827439 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_reset.3060827439
Directory /workspace/47.rstmgr_reset/latest

Test location /workspace/coverage/default/47.rstmgr_sec_cm_scan_intersig_mubi.4180643682
Short name T267
Test name
Test status
Simulation time 148655585 ps
CPU time 1.18 seconds
Started Jun 25 05:39:17 PM PDT 24
Finished Jun 25 05:39:20 PM PDT 24
Peak memory 200080 kb
Host smart-54d9f04f-ab1c-4fca-9cca-2c17741fa230
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4180643682 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sec_cm_scan_intersig_mubi.4180643682
Directory /workspace/47.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/47.rstmgr_smoke.3382989105
Short name T435
Test name
Test status
Simulation time 243739809 ps
CPU time 1.6 seconds
Started Jun 25 05:39:22 PM PDT 24
Finished Jun 25 05:39:25 PM PDT 24
Peak memory 200260 kb
Host smart-29846df1-d8f5-4238-8007-59ad394bc7fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3382989105 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_smoke.3382989105
Directory /workspace/47.rstmgr_smoke/latest

Test location /workspace/coverage/default/47.rstmgr_stress_all.1244297028
Short name T188
Test name
Test status
Simulation time 5803540562 ps
CPU time 25.33 seconds
Started Jun 25 05:39:22 PM PDT 24
Finished Jun 25 05:39:49 PM PDT 24
Peak memory 200448 kb
Host smart-0a074e18-fb64-41a2-9f0f-939d6883719b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244297028 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_stress_all.1244297028
Directory /workspace/47.rstmgr_stress_all/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst.3286160679
Short name T407
Test name
Test status
Simulation time 327501445 ps
CPU time 2.43 seconds
Started Jun 25 05:39:22 PM PDT 24
Finished Jun 25 05:39:26 PM PDT 24
Peak memory 208276 kb
Host smart-72c64501-a255-4cc5-b646-82acc24b41f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3286160679 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst.3286160679
Directory /workspace/47.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst_reset_race.1608266651
Short name T349
Test name
Test status
Simulation time 73149310 ps
CPU time 0.78 seconds
Started Jun 25 05:39:19 PM PDT 24
Finished Jun 25 05:39:21 PM PDT 24
Peak memory 200088 kb
Host smart-996f6749-d90f-4acb-9479-5228290e14ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1608266651 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst_reset_race.1608266651
Directory /workspace/47.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/48.rstmgr_alert_test.3328949240
Short name T9
Test name
Test status
Simulation time 85991335 ps
CPU time 0.82 seconds
Started Jun 25 05:39:36 PM PDT 24
Finished Jun 25 05:39:40 PM PDT 24
Peak memory 199984 kb
Host smart-c44cfd5e-c4b1-498e-bf58-b5daca067470
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328949240 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_alert_test.3328949240
Directory /workspace/48.rstmgr_alert_test/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_cnsty.3970048816
Short name T29
Test name
Test status
Simulation time 2166290601 ps
CPU time 7.54 seconds
Started Jun 25 05:39:25 PM PDT 24
Finished Jun 25 05:39:34 PM PDT 24
Peak memory 221672 kb
Host smart-9f42adc6-8e54-4254-9253-a5a809cd85c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3970048816 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_cnsty.3970048816
Directory /workspace/48.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_shadow_attack.2080169580
Short name T538
Test name
Test status
Simulation time 244690897 ps
CPU time 1.17 seconds
Started Jun 25 05:39:36 PM PDT 24
Finished Jun 25 05:39:40 PM PDT 24
Peak memory 217556 kb
Host smart-a9e2089b-8c11-4014-b3e2-c7e121ccfee6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2080169580 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_shadow_attack.2080169580
Directory /workspace/48.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/48.rstmgr_por_stretcher.652380801
Short name T282
Test name
Test status
Simulation time 141572423 ps
CPU time 0.84 seconds
Started Jun 25 05:39:16 PM PDT 24
Finished Jun 25 05:39:18 PM PDT 24
Peak memory 199896 kb
Host smart-4e10e616-b7c3-4373-bf7b-1cac271beb06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=652380801 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_por_stretcher.652380801
Directory /workspace/48.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/48.rstmgr_reset.1356930515
Short name T322
Test name
Test status
Simulation time 1479343496 ps
CPU time 5.65 seconds
Started Jun 25 05:39:17 PM PDT 24
Finished Jun 25 05:39:25 PM PDT 24
Peak memory 200380 kb
Host smart-5f5bde3e-4e81-487c-be53-c2081e05c72f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1356930515 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_reset.1356930515
Directory /workspace/48.rstmgr_reset/latest

Test location /workspace/coverage/default/48.rstmgr_sec_cm_scan_intersig_mubi.3217482207
Short name T372
Test name
Test status
Simulation time 104398882 ps
CPU time 1.08 seconds
Started Jun 25 05:39:15 PM PDT 24
Finished Jun 25 05:39:17 PM PDT 24
Peak memory 200064 kb
Host smart-fa57ab10-e721-457b-aed1-8f9ebd2425a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3217482207 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sec_cm_scan_intersig_mubi.3217482207
Directory /workspace/48.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/48.rstmgr_smoke.3543976933
Short name T128
Test name
Test status
Simulation time 218542153 ps
CPU time 1.5 seconds
Started Jun 25 05:39:21 PM PDT 24
Finished Jun 25 05:39:25 PM PDT 24
Peak memory 200260 kb
Host smart-935fefb3-09eb-456d-9917-f5a4fc3d24df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3543976933 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_smoke.3543976933
Directory /workspace/48.rstmgr_smoke/latest

Test location /workspace/coverage/default/48.rstmgr_stress_all.3401022153
Short name T464
Test name
Test status
Simulation time 10060696666 ps
CPU time 37.85 seconds
Started Jun 25 05:39:25 PM PDT 24
Finished Jun 25 05:40:04 PM PDT 24
Peak memory 210124 kb
Host smart-b9317779-9ae7-48f0-9ed6-315a58a60d80
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401022153 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_stress_all.3401022153
Directory /workspace/48.rstmgr_stress_all/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst.227657467
Short name T145
Test name
Test status
Simulation time 134857213 ps
CPU time 1.69 seconds
Started Jun 25 05:39:19 PM PDT 24
Finished Jun 25 05:39:23 PM PDT 24
Peak memory 200076 kb
Host smart-e254b546-a227-4b57-8683-b38ce1c3c5a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=227657467 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst.227657467
Directory /workspace/48.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst_reset_race.3161699362
Short name T370
Test name
Test status
Simulation time 248371187 ps
CPU time 1.68 seconds
Started Jun 25 05:39:24 PM PDT 24
Finished Jun 25 05:39:27 PM PDT 24
Peak memory 200284 kb
Host smart-e8860296-5258-49af-9e32-f6e70fb78fe4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3161699362 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst_reset_race.3161699362
Directory /workspace/48.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/49.rstmgr_alert_test.2269224802
Short name T218
Test name
Test status
Simulation time 67238368 ps
CPU time 0.81 seconds
Started Jun 25 05:39:36 PM PDT 24
Finished Jun 25 05:39:39 PM PDT 24
Peak memory 199984 kb
Host smart-89e76307-9cdc-49f7-a820-132c0b6f194b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269224802 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_alert_test.2269224802
Directory /workspace/49.rstmgr_alert_test/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_cnsty.3744894008
Short name T525
Test name
Test status
Simulation time 1221033820 ps
CPU time 6.12 seconds
Started Jun 25 05:39:24 PM PDT 24
Finished Jun 25 05:39:32 PM PDT 24
Peak memory 217756 kb
Host smart-ea04e2f0-0dc7-4d30-a9db-9ad506a0fbbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3744894008 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_cnsty.3744894008
Directory /workspace/49.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_shadow_attack.3020160470
Short name T510
Test name
Test status
Simulation time 244746127 ps
CPU time 1.11 seconds
Started Jun 25 05:39:35 PM PDT 24
Finished Jun 25 05:39:39 PM PDT 24
Peak memory 217556 kb
Host smart-cbeb09b2-b374-462d-88e8-838b220fe35b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3020160470 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_shadow_attack.3020160470
Directory /workspace/49.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/49.rstmgr_por_stretcher.3350947527
Short name T2
Test name
Test status
Simulation time 100652625 ps
CPU time 0.76 seconds
Started Jun 25 05:39:25 PM PDT 24
Finished Jun 25 05:39:27 PM PDT 24
Peak memory 199900 kb
Host smart-8b648821-96ee-419e-b339-c00cd0a7bbd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3350947527 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_por_stretcher.3350947527
Directory /workspace/49.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/49.rstmgr_reset.133939640
Short name T339
Test name
Test status
Simulation time 728320592 ps
CPU time 3.77 seconds
Started Jun 25 05:39:25 PM PDT 24
Finished Jun 25 05:39:30 PM PDT 24
Peak memory 200336 kb
Host smart-116ec02e-b2bd-4149-a866-c59a0a8112dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=133939640 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_reset.133939640
Directory /workspace/49.rstmgr_reset/latest

Test location /workspace/coverage/default/49.rstmgr_sec_cm_scan_intersig_mubi.2404823332
Short name T246
Test name
Test status
Simulation time 173949666 ps
CPU time 1.18 seconds
Started Jun 25 05:39:22 PM PDT 24
Finished Jun 25 05:39:25 PM PDT 24
Peak memory 200068 kb
Host smart-35d907da-bd56-411a-98af-8917aa90ca95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2404823332 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sec_cm_scan_intersig_mubi.2404823332
Directory /workspace/49.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/49.rstmgr_smoke.20913091
Short name T198
Test name
Test status
Simulation time 233982630 ps
CPU time 1.5 seconds
Started Jun 25 05:39:23 PM PDT 24
Finished Jun 25 05:39:26 PM PDT 24
Peak memory 200288 kb
Host smart-c639f6a0-1363-4f6a-932f-2a71d56b33aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20913091 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_smoke.20913091
Directory /workspace/49.rstmgr_smoke/latest

Test location /workspace/coverage/default/49.rstmgr_stress_all.3232278181
Short name T121
Test name
Test status
Simulation time 7797419829 ps
CPU time 27.13 seconds
Started Jun 25 05:39:25 PM PDT 24
Finished Jun 25 05:39:53 PM PDT 24
Peak memory 208608 kb
Host smart-ff32d2d6-48bc-49c0-a9df-1c39f5759200
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232278181 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_stress_all.3232278181
Directory /workspace/49.rstmgr_stress_all/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst.4127715307
Short name T149
Test name
Test status
Simulation time 122115236 ps
CPU time 1.51 seconds
Started Jun 25 05:39:29 PM PDT 24
Finished Jun 25 05:39:33 PM PDT 24
Peak memory 200064 kb
Host smart-99485fe6-2ea6-444b-9ed3-1d21dd4e0cb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4127715307 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst.4127715307
Directory /workspace/49.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst_reset_race.944391767
Short name T235
Test name
Test status
Simulation time 137416471 ps
CPU time 1.12 seconds
Started Jun 25 05:39:24 PM PDT 24
Finished Jun 25 05:39:26 PM PDT 24
Peak memory 200012 kb
Host smart-0f72b3f0-b8e9-4f00-bf2b-40646b815541
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=944391767 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst_reset_race.944391767
Directory /workspace/49.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/5.rstmgr_alert_test.380641330
Short name T63
Test name
Test status
Simulation time 56776948 ps
CPU time 0.77 seconds
Started Jun 25 05:38:06 PM PDT 24
Finished Jun 25 05:38:07 PM PDT 24
Peak memory 199880 kb
Host smart-a8c30f63-bb14-4a75-a3c7-8a6dfa74f234
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380641330 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_alert_test.380641330
Directory /workspace/5.rstmgr_alert_test/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_cnsty.1252866078
Short name T387
Test name
Test status
Simulation time 1901288793 ps
CPU time 7.46 seconds
Started Jun 25 05:38:06 PM PDT 24
Finished Jun 25 05:38:14 PM PDT 24
Peak memory 221636 kb
Host smart-f2d9435a-b91f-4800-9da1-f4cb589664a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1252866078 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_cnsty.1252866078
Directory /workspace/5.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_shadow_attack.730458108
Short name T543
Test name
Test status
Simulation time 248237553 ps
CPU time 1.09 seconds
Started Jun 25 05:38:05 PM PDT 24
Finished Jun 25 05:38:07 PM PDT 24
Peak memory 217428 kb
Host smart-f134f49c-2d60-430a-9191-0c87baf56dec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=730458108 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_shadow_attack.730458108
Directory /workspace/5.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/5.rstmgr_por_stretcher.1216772569
Short name T229
Test name
Test status
Simulation time 217155369 ps
CPU time 0.99 seconds
Started Jun 25 05:37:57 PM PDT 24
Finished Jun 25 05:38:00 PM PDT 24
Peak memory 199900 kb
Host smart-021fdb28-0dd7-463e-9cbd-96aae4bc667d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1216772569 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_por_stretcher.1216772569
Directory /workspace/5.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/5.rstmgr_reset.2154461016
Short name T396
Test name
Test status
Simulation time 1461377123 ps
CPU time 6.23 seconds
Started Jun 25 05:37:55 PM PDT 24
Finished Jun 25 05:38:03 PM PDT 24
Peak memory 200268 kb
Host smart-70661523-ef61-4b47-80b8-4df961c2856f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2154461016 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_reset.2154461016
Directory /workspace/5.rstmgr_reset/latest

Test location /workspace/coverage/default/5.rstmgr_sec_cm_scan_intersig_mubi.3066057311
Short name T524
Test name
Test status
Simulation time 147612819 ps
CPU time 1.15 seconds
Started Jun 25 05:37:56 PM PDT 24
Finished Jun 25 05:37:59 PM PDT 24
Peak memory 199980 kb
Host smart-65ad84fb-e362-48ae-8645-ea9b9a4a97d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3066057311 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sec_cm_scan_intersig_mubi.3066057311
Directory /workspace/5.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/5.rstmgr_smoke.2696179353
Short name T493
Test name
Test status
Simulation time 221664014 ps
CPU time 1.51 seconds
Started Jun 25 05:37:57 PM PDT 24
Finished Jun 25 05:38:01 PM PDT 24
Peak memory 200260 kb
Host smart-0a3a5c94-defd-4d5b-8810-798d35edebdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2696179353 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_smoke.2696179353
Directory /workspace/5.rstmgr_smoke/latest

Test location /workspace/coverage/default/5.rstmgr_stress_all.3098557122
Short name T226
Test name
Test status
Simulation time 1292673657 ps
CPU time 6.52 seconds
Started Jun 25 05:38:05 PM PDT 24
Finished Jun 25 05:38:12 PM PDT 24
Peak memory 200368 kb
Host smart-b43f47ad-6eb1-4b91-a367-af375fd6ba4e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098557122 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_stress_all.3098557122
Directory /workspace/5.rstmgr_stress_all/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst.2451145711
Short name T332
Test name
Test status
Simulation time 139275787 ps
CPU time 1.86 seconds
Started Jun 25 05:38:00 PM PDT 24
Finished Jun 25 05:38:04 PM PDT 24
Peak memory 200068 kb
Host smart-6a674914-f6ec-4015-9dda-5c9601101cac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2451145711 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst.2451145711
Directory /workspace/5.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst_reset_race.58610191
Short name T163
Test name
Test status
Simulation time 140610911 ps
CPU time 1.29 seconds
Started Jun 25 05:37:56 PM PDT 24
Finished Jun 25 05:38:00 PM PDT 24
Peak memory 200012 kb
Host smart-0f847d54-6c21-4f06-b26d-513287cc47ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58610191 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst_reset_race.58610191
Directory /workspace/5.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/6.rstmgr_alert_test.1782577683
Short name T530
Test name
Test status
Simulation time 63815694 ps
CPU time 0.81 seconds
Started Jun 25 05:38:05 PM PDT 24
Finished Jun 25 05:38:07 PM PDT 24
Peak memory 199864 kb
Host smart-1f6673cc-07af-47bf-bb9a-bf8df0814ddb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782577683 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_alert_test.1782577683
Directory /workspace/6.rstmgr_alert_test/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_cnsty.909457487
Short name T354
Test name
Test status
Simulation time 2172179987 ps
CPU time 8.39 seconds
Started Jun 25 05:38:07 PM PDT 24
Finished Jun 25 05:38:17 PM PDT 24
Peak memory 217552 kb
Host smart-78dde2e2-0f06-433e-a359-106bee812d05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=909457487 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_cnsty.909457487
Directory /workspace/6.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_shadow_attack.3074894163
Short name T231
Test name
Test status
Simulation time 243988963 ps
CPU time 1.11 seconds
Started Jun 25 05:38:06 PM PDT 24
Finished Jun 25 05:38:09 PM PDT 24
Peak memory 217380 kb
Host smart-d0410e91-f903-4a7d-966c-e07b54c43d69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3074894163 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_shadow_attack.3074894163
Directory /workspace/6.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/6.rstmgr_por_stretcher.2246918417
Short name T232
Test name
Test status
Simulation time 84910582 ps
CPU time 0.8 seconds
Started Jun 25 05:38:05 PM PDT 24
Finished Jun 25 05:38:06 PM PDT 24
Peak memory 199900 kb
Host smart-fb5d077d-0990-4c2b-8319-584f1fd749fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2246918417 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_por_stretcher.2246918417
Directory /workspace/6.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/6.rstmgr_reset.1952602505
Short name T453
Test name
Test status
Simulation time 1958412928 ps
CPU time 7.53 seconds
Started Jun 25 05:38:06 PM PDT 24
Finished Jun 25 05:38:14 PM PDT 24
Peak memory 200332 kb
Host smart-4cfb0fa8-cbaa-4c60-b53a-33e98b7d00d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1952602505 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_reset.1952602505
Directory /workspace/6.rstmgr_reset/latest

Test location /workspace/coverage/default/6.rstmgr_sec_cm_scan_intersig_mubi.3449051387
Short name T158
Test name
Test status
Simulation time 101733155 ps
CPU time 1.06 seconds
Started Jun 25 05:38:06 PM PDT 24
Finished Jun 25 05:38:08 PM PDT 24
Peak memory 200072 kb
Host smart-f66dbb3d-c664-40dd-a52e-dc035db9fcf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3449051387 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sec_cm_scan_intersig_mubi.3449051387
Directory /workspace/6.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/6.rstmgr_smoke.2120414693
Short name T68
Test name
Test status
Simulation time 112911921 ps
CPU time 1.19 seconds
Started Jun 25 05:38:09 PM PDT 24
Finished Jun 25 05:38:12 PM PDT 24
Peak memory 200276 kb
Host smart-7a8ee9b8-ff30-4bbc-a25a-04ce5480575d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2120414693 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_smoke.2120414693
Directory /workspace/6.rstmgr_smoke/latest

Test location /workspace/coverage/default/6.rstmgr_stress_all.1598345150
Short name T201
Test name
Test status
Simulation time 1053577806 ps
CPU time 5.2 seconds
Started Jun 25 05:38:06 PM PDT 24
Finished Jun 25 05:38:13 PM PDT 24
Peak memory 200332 kb
Host smart-ef0839ef-ec53-476b-a54e-449a90534874
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598345150 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_stress_all.1598345150
Directory /workspace/6.rstmgr_stress_all/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst.3604685544
Short name T213
Test name
Test status
Simulation time 137206592 ps
CPU time 1.66 seconds
Started Jun 25 05:38:05 PM PDT 24
Finished Jun 25 05:38:07 PM PDT 24
Peak memory 200072 kb
Host smart-6e774f27-ffdc-4494-9aea-790aa6a13252
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3604685544 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst.3604685544
Directory /workspace/6.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst_reset_race.1611163439
Short name T221
Test name
Test status
Simulation time 187040751 ps
CPU time 1.26 seconds
Started Jun 25 05:38:08 PM PDT 24
Finished Jun 25 05:38:10 PM PDT 24
Peak memory 200088 kb
Host smart-69ea7c44-f1c0-4142-a191-6d23089045ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1611163439 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst_reset_race.1611163439
Directory /workspace/6.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/7.rstmgr_alert_test.3667388290
Short name T303
Test name
Test status
Simulation time 65073252 ps
CPU time 0.78 seconds
Started Jun 25 05:38:04 PM PDT 24
Finished Jun 25 05:38:05 PM PDT 24
Peak memory 199808 kb
Host smart-4f66f94a-8be3-4e21-afe0-b2e02ba08e66
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3667388290 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_alert_test.3667388290
Directory /workspace/7.rstmgr_alert_test/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_cnsty.2278032112
Short name T248
Test name
Test status
Simulation time 1228541733 ps
CPU time 5.66 seconds
Started Jun 25 05:38:07 PM PDT 24
Finished Jun 25 05:38:15 PM PDT 24
Peak memory 217568 kb
Host smart-364899da-2421-4448-a217-ec3424df9af4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2278032112 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_cnsty.2278032112
Directory /workspace/7.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_shadow_attack.1153387959
Short name T182
Test name
Test status
Simulation time 244066628 ps
CPU time 1.16 seconds
Started Jun 25 05:38:08 PM PDT 24
Finished Jun 25 05:38:11 PM PDT 24
Peak memory 217432 kb
Host smart-4891c240-ee26-4d40-9cab-d873ab5e6c4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1153387959 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_shadow_attack.1153387959
Directory /workspace/7.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/7.rstmgr_por_stretcher.375078439
Short name T495
Test name
Test status
Simulation time 143659067 ps
CPU time 0.89 seconds
Started Jun 25 05:38:05 PM PDT 24
Finished Jun 25 05:38:07 PM PDT 24
Peak memory 199888 kb
Host smart-adb55bae-da23-4855-bcaf-dae1a997b935
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=375078439 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_por_stretcher.375078439
Directory /workspace/7.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/7.rstmgr_reset.249068332
Short name T520
Test name
Test status
Simulation time 995449363 ps
CPU time 5 seconds
Started Jun 25 05:38:05 PM PDT 24
Finished Jun 25 05:38:11 PM PDT 24
Peak memory 200376 kb
Host smart-dc1ccd1f-22f7-4764-ac53-060971fd2d3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=249068332 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_reset.249068332
Directory /workspace/7.rstmgr_reset/latest

Test location /workspace/coverage/default/7.rstmgr_sec_cm_scan_intersig_mubi.125216678
Short name T143
Test name
Test status
Simulation time 152494265 ps
CPU time 1.32 seconds
Started Jun 25 05:38:04 PM PDT 24
Finished Jun 25 05:38:06 PM PDT 24
Peak memory 200096 kb
Host smart-0b2b9f75-5617-419a-bd71-d3870b83ccfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=125216678 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sec_cm_scan_intersig_mubi.125216678
Directory /workspace/7.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/7.rstmgr_smoke.212505127
Short name T423
Test name
Test status
Simulation time 122197640 ps
CPU time 1.27 seconds
Started Jun 25 05:38:08 PM PDT 24
Finished Jun 25 05:38:11 PM PDT 24
Peak memory 200280 kb
Host smart-9ceeb78d-0fcf-4249-a5f8-9afcfebc8a5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=212505127 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_smoke.212505127
Directory /workspace/7.rstmgr_smoke/latest

Test location /workspace/coverage/default/7.rstmgr_stress_all.3662144061
Short name T399
Test name
Test status
Simulation time 210909339 ps
CPU time 1.46 seconds
Started Jun 25 05:38:05 PM PDT 24
Finished Jun 25 05:38:08 PM PDT 24
Peak memory 200212 kb
Host smart-3cc0e2dd-8ff7-49f4-b3f4-12b834445b1a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662144061 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_stress_all.3662144061
Directory /workspace/7.rstmgr_stress_all/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst.1361152803
Short name T513
Test name
Test status
Simulation time 123666465 ps
CPU time 1.55 seconds
Started Jun 25 05:38:07 PM PDT 24
Finished Jun 25 05:38:10 PM PDT 24
Peak memory 200124 kb
Host smart-45e0c1a1-ebbc-479c-b3ab-6b52f70d2e6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1361152803 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst.1361152803
Directory /workspace/7.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst_reset_race.1398514826
Short name T227
Test name
Test status
Simulation time 88362585 ps
CPU time 0.91 seconds
Started Jun 25 05:38:06 PM PDT 24
Finished Jun 25 05:38:08 PM PDT 24
Peak memory 200076 kb
Host smart-662bc1bd-5d0d-4eac-ab6a-7bb66dc4c4b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1398514826 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst_reset_race.1398514826
Directory /workspace/7.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/8.rstmgr_alert_test.3760713142
Short name T382
Test name
Test status
Simulation time 76522629 ps
CPU time 0.83 seconds
Started Jun 25 05:38:17 PM PDT 24
Finished Jun 25 05:38:19 PM PDT 24
Peak memory 199880 kb
Host smart-d8a49ce8-2067-493e-ac3f-f41f1bf60174
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760713142 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_alert_test.3760713142
Directory /workspace/8.rstmgr_alert_test/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_cnsty.1996713321
Short name T316
Test name
Test status
Simulation time 1224379800 ps
CPU time 6.06 seconds
Started Jun 25 05:38:07 PM PDT 24
Finished Jun 25 05:38:14 PM PDT 24
Peak memory 217608 kb
Host smart-e21d7157-ed13-4aa2-ab4b-96fb2769b490
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1996713321 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_cnsty.1996713321
Directory /workspace/8.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_shadow_attack.2504817549
Short name T429
Test name
Test status
Simulation time 244231326 ps
CPU time 1.17 seconds
Started Jun 25 05:38:06 PM PDT 24
Finished Jun 25 05:38:09 PM PDT 24
Peak memory 217448 kb
Host smart-1b12eb7f-0936-4a2a-a666-92bbd4033251
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2504817549 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_shadow_attack.2504817549
Directory /workspace/8.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/8.rstmgr_por_stretcher.1568530399
Short name T276
Test name
Test status
Simulation time 97873551 ps
CPU time 0.77 seconds
Started Jun 25 05:38:05 PM PDT 24
Finished Jun 25 05:38:07 PM PDT 24
Peak memory 199816 kb
Host smart-92798530-9a43-4ea8-abbc-2a3c9143e6a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1568530399 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_por_stretcher.1568530399
Directory /workspace/8.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/8.rstmgr_reset.2567050175
Short name T169
Test name
Test status
Simulation time 903155910 ps
CPU time 4.91 seconds
Started Jun 25 05:38:07 PM PDT 24
Finished Jun 25 05:38:14 PM PDT 24
Peak memory 200328 kb
Host smart-9a0029fb-a1d8-4710-8bee-631523faddb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2567050175 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_reset.2567050175
Directory /workspace/8.rstmgr_reset/latest

Test location /workspace/coverage/default/8.rstmgr_sec_cm_scan_intersig_mubi.602497133
Short name T443
Test name
Test status
Simulation time 180368007 ps
CPU time 1.25 seconds
Started Jun 25 05:38:07 PM PDT 24
Finished Jun 25 05:38:09 PM PDT 24
Peak memory 200084 kb
Host smart-dba8b957-7e3b-4280-ae00-61085b8e411d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=602497133 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sec_cm_scan_intersig_mubi.602497133
Directory /workspace/8.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/8.rstmgr_smoke.1388314721
Short name T215
Test name
Test status
Simulation time 247777929 ps
CPU time 1.58 seconds
Started Jun 25 05:38:07 PM PDT 24
Finished Jun 25 05:38:10 PM PDT 24
Peak memory 200256 kb
Host smart-6245387b-d57c-4030-bb13-8e55156fabeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1388314721 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_smoke.1388314721
Directory /workspace/8.rstmgr_smoke/latest

Test location /workspace/coverage/default/8.rstmgr_stress_all.2443871713
Short name T202
Test name
Test status
Simulation time 6822677664 ps
CPU time 30.89 seconds
Started Jun 25 05:38:05 PM PDT 24
Finished Jun 25 05:38:36 PM PDT 24
Peak memory 208516 kb
Host smart-daef1b11-51b4-4b78-98a0-d4e6e2b36c27
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443871713 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_stress_all.2443871713
Directory /workspace/8.rstmgr_stress_all/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst.1544314252
Short name T389
Test name
Test status
Simulation time 137816215 ps
CPU time 1.68 seconds
Started Jun 25 05:38:08 PM PDT 24
Finished Jun 25 05:38:11 PM PDT 24
Peak memory 200072 kb
Host smart-cfb3a0b1-9a53-41dd-b4bd-1670dc6d95f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1544314252 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst.1544314252
Directory /workspace/8.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst_reset_race.2146622903
Short name T451
Test name
Test status
Simulation time 228866130 ps
CPU time 1.29 seconds
Started Jun 25 05:38:07 PM PDT 24
Finished Jun 25 05:38:10 PM PDT 24
Peak memory 200076 kb
Host smart-a6ec3555-5066-4a66-88fd-6f134429f3bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2146622903 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst_reset_race.2146622903
Directory /workspace/8.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/9.rstmgr_alert_test.4082891891
Short name T241
Test name
Test status
Simulation time 84161344 ps
CPU time 0.83 seconds
Started Jun 25 05:38:15 PM PDT 24
Finished Jun 25 05:38:17 PM PDT 24
Peak memory 199868 kb
Host smart-908d8bd9-37a5-4c2a-ad5f-39f23e39ccb4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082891891 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_alert_test.4082891891
Directory /workspace/9.rstmgr_alert_test/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_cnsty.1604673516
Short name T26
Test name
Test status
Simulation time 1220875535 ps
CPU time 5.13 seconds
Started Jun 25 05:38:18 PM PDT 24
Finished Jun 25 05:38:24 PM PDT 24
Peak memory 221628 kb
Host smart-6030ce89-c9d0-4766-a3ed-6edaff942e84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1604673516 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_cnsty.1604673516
Directory /workspace/9.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_shadow_attack.2714910303
Short name T161
Test name
Test status
Simulation time 246994707 ps
CPU time 1.12 seconds
Started Jun 25 05:38:15 PM PDT 24
Finished Jun 25 05:38:17 PM PDT 24
Peak memory 217456 kb
Host smart-b6d4b31d-d227-48e0-abd3-99ff11016032
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2714910303 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_shadow_attack.2714910303
Directory /workspace/9.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/9.rstmgr_por_stretcher.380784956
Short name T160
Test name
Test status
Simulation time 137541192 ps
CPU time 0.83 seconds
Started Jun 25 05:38:14 PM PDT 24
Finished Jun 25 05:38:16 PM PDT 24
Peak memory 199812 kb
Host smart-6d566295-5846-4ea8-a0d3-0bcaee3f2774
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=380784956 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_por_stretcher.380784956
Directory /workspace/9.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/9.rstmgr_reset.136974363
Short name T338
Test name
Test status
Simulation time 1409509907 ps
CPU time 6.04 seconds
Started Jun 25 05:38:13 PM PDT 24
Finished Jun 25 05:38:21 PM PDT 24
Peak memory 200352 kb
Host smart-d211d798-9730-41fb-b129-0cd7a16509c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=136974363 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_reset.136974363
Directory /workspace/9.rstmgr_reset/latest

Test location /workspace/coverage/default/9.rstmgr_sec_cm_scan_intersig_mubi.1518872935
Short name T141
Test name
Test status
Simulation time 105415909 ps
CPU time 0.98 seconds
Started Jun 25 05:38:16 PM PDT 24
Finished Jun 25 05:38:18 PM PDT 24
Peak memory 200028 kb
Host smart-a791c769-d295-4325-bfca-a23cd0630897
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1518872935 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sec_cm_scan_intersig_mubi.1518872935
Directory /workspace/9.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/9.rstmgr_smoke.3049003993
Short name T177
Test name
Test status
Simulation time 196498203 ps
CPU time 1.46 seconds
Started Jun 25 05:38:12 PM PDT 24
Finished Jun 25 05:38:15 PM PDT 24
Peak memory 200268 kb
Host smart-de9bf82a-9b71-43b0-b4cc-266294b366c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3049003993 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_smoke.3049003993
Directory /workspace/9.rstmgr_smoke/latest

Test location /workspace/coverage/default/9.rstmgr_stress_all.1118565536
Short name T318
Test name
Test status
Simulation time 7890128501 ps
CPU time 26.63 seconds
Started Jun 25 05:38:23 PM PDT 24
Finished Jun 25 05:38:51 PM PDT 24
Peak memory 210480 kb
Host smart-5878e4ac-83ef-402a-9e95-1668e79a2710
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118565536 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_stress_all.1118565536
Directory /workspace/9.rstmgr_stress_all/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst.2730484457
Short name T490
Test name
Test status
Simulation time 259326762 ps
CPU time 1.82 seconds
Started Jun 25 05:38:23 PM PDT 24
Finished Jun 25 05:38:27 PM PDT 24
Peak memory 200068 kb
Host smart-e747750f-e0ff-42ac-90be-5696c58d13f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2730484457 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst.2730484457
Directory /workspace/9.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst_reset_race.1100983336
Short name T225
Test name
Test status
Simulation time 144483904 ps
CPU time 1.08 seconds
Started Jun 25 05:38:23 PM PDT 24
Finished Jun 25 05:38:26 PM PDT 24
Peak memory 200072 kb
Host smart-af1fc838-ab9e-437f-8228-69a4ef8de6c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1100983336 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst_reset_race.1100983336
Directory /workspace/9.rstmgr_sw_rst_reset_race/latest
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