Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	550793	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

329383

1

T1

118

T2

130

T4

7

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	467251	1			T1	186		T2	186		T3	1
values[0x0]	206438	1			T1	95		T2	86		T4	11
values[0x1]	206487	1			T1	98		T2	107		T4	8

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	462627	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

417549

1

T1

156

T2

176

T3

1

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	2760	1			T2	1		T7	31		T11	6
valid_sources[0x01]	2905	1			T1	1		T5	2		T7	27
valid_sources[0x02]	3492	1			T1	2		T5	4		T7	36
valid_sources[0x03]	3128	1			T1	1		T5	3		T7	15
valid_sources[0x04]	3804	1			T1	3		T2	3		T5	7
valid_sources[0x05]	2937	1			T2	1		T5	1		T7	24
valid_sources[0x06]	2987	1			T1	1		T5	2		T7	17
valid_sources[0x07]	4462	1			T1	3		T2	3		T5	4
valid_sources[0x08]	3008	1			T1	1		T2	1		T5	4
valid_sources[0x09]	2494	1			T1	1		T5	3		T7	27
valid_sources[0x0a]	4095	1			T1	2		T2	5		T5	2
valid_sources[0x0b]	3474	1			T2	2		T5	10		T7	20
valid_sources[0x0c]	3461	1			T2	4		T5	3		T7	27
valid_sources[0x0d]	3827	1			T1	1		T5	2		T7	32
valid_sources[0x0e]	3820	1			T5	4		T7	19		T11	12
valid_sources[0x0f]	3062	1			T1	2		T2	2		T5	6
valid_sources[0x10]	3278	1			T2	2		T5	4		T7	25
valid_sources[0x11]	3393	1			T1	1		T5	4		T7	11
valid_sources[0x12]	2765	1			T2	1		T5	6		T7	23
valid_sources[0x13]	3212	1			T1	2		T5	1		T7	30
valid_sources[0x14]	3574	1			T1	1		T2	2		T5	4
valid_sources[0x15]	6706	1			T1	1		T2	4		T7	27
valid_sources[0x16]	3389	1			T1	3		T5	1		T7	24
valid_sources[0x17]	2815	1			T1	3		T5	2		T7	30
valid_sources[0x18]	5190	1			T2	2		T5	3		T7	30
valid_sources[0x19]	4466	1			T2	2		T5	3		T7	30
valid_sources[0x1a]	3213	1			T1	5		T2	2		T5	7
valid_sources[0x1b]	3182	1			T2	3		T5	5		T7	22
valid_sources[0x1c]	3024	1			T2	2		T5	3		T7	19
valid_sources[0x1d]	4172	1			T5	8		T7	18		T10	6
valid_sources[0x1e]	2824	1			T1	2		T5	3		T7	19
valid_sources[0x1f]	3004	1			T1	3		T7	42		T11	7
valid_sources[0x20]	2722	1			T1	7		T7	24		T11	9
valid_sources[0x21]	3622	1			T5	4		T7	28		T11	13
valid_sources[0x22]	3012	1			T5	2		T7	28		T10	2
valid_sources[0x23]	3085	1			T1	1		T2	6		T5	7
valid_sources[0x24]	2579	1			T1	3		T5	2		T7	25
valid_sources[0x25]	3166	1			T2	1		T5	7		T7	24
valid_sources[0x26]	2987	1			T7	21		T11	8		T12	13
valid_sources[0x27]	3021	1			T1	1		T2	1		T5	7
valid_sources[0x28]	3300	1			T2	3		T5	4		T7	22
valid_sources[0x29]	3239	1			T5	3		T7	22		T11	2
valid_sources[0x2a]	3045	1			T1	1		T2	2		T5	1
valid_sources[0x2b]	5322	1			T1	1		T5	2		T7	18
valid_sources[0x2c]	3321	1			T1	1		T5	4		T7	29
valid_sources[0x2d]	4055	1			T1	1		T2	4		T3	1
valid_sources[0x2e]	3857	1			T1	1		T5	3		T7	18
valid_sources[0x2f]	2870	1			T2	1		T5	2		T7	15
valid_sources[0x30]	3826	1			T5	11		T7	20		T10	1
valid_sources[0x31]	6176	1			T2	1		T5	4		T7	22
valid_sources[0x32]	3481	1			T1	2		T5	1		T7	25
valid_sources[0x33]	2859	1			T1	1		T2	6		T5	2
valid_sources[0x34]	3691	1			T1	1		T5	3		T7	9
valid_sources[0x35]	3468	1			T1	2		T2	2		T5	3
valid_sources[0x36]	3420	1			T1	8		T2	5		T5	1
valid_sources[0x37]	3168	1			T2	8		T7	25		T11	8
valid_sources[0x38]	3220	1			T2	1		T5	2		T7	35
valid_sources[0x39]	4555	1			T5	6		T7	25		T10	6
valid_sources[0x3a]	2785	1			T1	3		T2	2		T5	3
valid_sources[0x3b]	2998	1			T1	2		T2	2		T7	26
valid_sources[0x3c]	2914	1			T1	5		T2	3		T5	2
valid_sources[0x3d]	3299	1			T1	2		T5	2		T7	22
valid_sources[0x3e]	3194	1			T1	2		T5	3		T7	13
valid_sources[0x3f]	2959	1			T5	2		T7	25		T10	4
valid_sources[0x40]	3363	1			T5	6		T7	31		T11	9
valid_sources[0x41]	3616	1			T1	1		T5	2		T7	28
valid_sources[0x42]	3425	1			T1	4		T2	1		T5	1
valid_sources[0x43]	3254	1			T5	1		T7	28		T11	16
valid_sources[0x44]	3175	1			T2	1		T5	1		T7	28
valid_sources[0x45]	5245	1			T1	1		T5	2		T7	28
valid_sources[0x46]	3362	1			T1	2		T5	1		T7	24
valid_sources[0x47]	3299	1			T1	2		T2	1		T5	5
valid_sources[0x48]	2828	1			T1	3		T5	4		T7	30
valid_sources[0x49]	3019	1			T1	1		T2	3		T5	5
valid_sources[0x4a]	3337	1			T1	2		T5	1		T7	33
valid_sources[0x4b]	2982	1			T5	5		T7	14		T11	10
valid_sources[0x4c]	3593	1			T5	2		T7	19		T11	11
valid_sources[0x4d]	2747	1			T5	9		T7	28		T11	11
valid_sources[0x4e]	3180	1			T2	1		T5	1		T7	27
valid_sources[0x4f]	3789	1			T1	6		T5	2		T7	26
valid_sources[0x50]	2455	1			T1	1		T5	7		T7	25
valid_sources[0x51]	3798	1			T1	1		T2	2		T5	3
valid_sources[0x52]	3464	1			T1	3		T7	36		T11	20
valid_sources[0x53]	4213	1			T2	2		T5	3		T7	28
valid_sources[0x54]	3913	1			T1	1		T2	5		T4	19
valid_sources[0x55]	2943	1			T1	1		T2	4		T5	1
valid_sources[0x56]	3749	1			T1	1		T7	17		T10	5
valid_sources[0x57]	2930	1			T1	2		T5	3		T7	27
valid_sources[0x58]	3129	1			T1	6		T7	26		T11	6
valid_sources[0x59]	2999	1			T1	2		T2	2		T5	5
valid_sources[0x5a]	3964	1			T2	1		T5	1		T7	18
valid_sources[0x5b]	7391	1			T2	1		T7	31		T11	8
valid_sources[0x5c]	2873	1			T1	1		T2	4		T5	2
valid_sources[0x5d]	3346	1			T1	1		T5	3		T7	32
valid_sources[0x5e]	2810	1			T1	3		T5	6		T7	25
valid_sources[0x5f]	3289	1			T1	2		T5	3		T7	29
valid_sources[0x60]	4362	1			T1	1		T2	1		T5	1
valid_sources[0x61]	6862	1			T2	4		T5	3		T7	19
valid_sources[0x62]	2747	1			T1	1		T2	2		T5	3
valid_sources[0x63]	3397	1			T1	4		T2	3		T5	4
valid_sources[0x64]	3406	1			T1	4		T5	2		T7	24
valid_sources[0x65]	3177	1			T2	1		T7	21		T11	6
valid_sources[0x66]	2876	1			T5	4		T7	23		T11	8
valid_sources[0x67]	3572	1			T1	5		T5	4		T7	20
valid_sources[0x68]	2702	1			T1	5		T2	4		T5	2
valid_sources[0x69]	3849	1			T2	1		T5	1		T7	33
valid_sources[0x6a]	3558	1			T5	4		T7	17		T11	13
valid_sources[0x6b]	3604	1			T1	1		T2	2		T5	5
valid_sources[0x6c]	3496	1			T1	1		T5	4		T7	20
valid_sources[0x6d]	3052	1			T1	2		T2	1		T5	4
valid_sources[0x6e]	2985	1			T5	3		T7	23		T11	17
valid_sources[0x6f]	3609	1			T2	1		T5	2		T7	23
valid_sources[0x70]	3149	1			T1	1		T5	2		T7	20
valid_sources[0x71]	3483	1			T1	1		T2	2		T5	2
valid_sources[0x72]	2992	1			T2	2		T5	9		T7	40
valid_sources[0x73]	3282	1			T1	3		T5	3		T7	21
valid_sources[0x74]	3493	1			T2	1		T5	2		T7	27
valid_sources[0x75]	3384	1			T1	3		T5	4		T7	23
valid_sources[0x76]	3618	1			T1	3		T2	1		T5	8
valid_sources[0x77]	3901	1			T1	4		T5	5		T7	24
valid_sources[0x78]	2910	1			T1	1		T2	2		T5	3
valid_sources[0x79]	2622	1			T1	1		T5	2		T7	21
valid_sources[0x7a]	3351	1			T2	4		T5	4		T7	14
valid_sources[0x7b]	3224	1			T2	4		T5	7		T7	28
valid_sources[0x7c]	2734	1			T5	7		T7	22		T11	11
valid_sources[0x7d]	3211	1			T1	6		T5	2		T7	18
valid_sources[0x7e]	2723	1			T5	2		T7	20		T10	3
valid_sources[0x7f]	2610	1			T1	1		T2	2		T5	4
valid_sources[0x80]	3384	1			T1	1		T2	1		T5	4

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

218987

1

T1

76

T2

76

T5

212

values[0x0]

all_enables

biggest_size

71857

1

T1

28

T2

36

T4

6

values[0x1]

all_enables

biggest_size

38539

1

T1

14

T2

18

T4

1