Unified Coverage Report :: Module :: rstmgr_cascading_sva_if

Module : rstmgr_cascading_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_cascading_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_cascading_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_cascading_sva_if

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	100	1	1	100.00
ALWAYS	103	1	1	100.00
ALWAYS	107	1	1	100.00
ALWAYS	127	1	1	100.00
ALWAYS	138	1	1	100.00
ALWAYS	141	1	1	100.00
ALWAYS	144	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
100	1	1
103	1	1
107	1	1
127	1	1
138	1	1
141	1	1
144	1	1

---

Cond Coverage for Module : rstmgr_cascading_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       103
 EXPRESSION (((!scanmode)) || scan_rst_ni)
             ------1------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T7
0	1	Covered	T2,T7,T11
1	0	Covered	T7,T11,T12

 LINE       107
 EXPRESSION (por_n_i[rstmgr_pkg::DomainAonSel] && ((!scanmode)))
             ----------------1----------------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T3,T6,T7
1	0	Covered	T1,T2,T7
1	1	Covered	T1,T2,T3

---

Assert Coverage for Module : rstmgr_cascading_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	31	31	100.00	31	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	31	31	100.00	31	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CascadeEffAonToRstPorAboveFall_A	48495433	8139	0	0
CascadeEffAonToRstPorAboveRise_A	48495433	8139	0	0
CascadeEffAonToRstPorIoAboveFall_A	46554336	8139	0	0
CascadeEffAonToRstPorIoAboveRise_A	46554336	8139	0	0
CascadeEffAonToRstPorIoDiv2AboveFall_A	23277556	8139	0	0
CascadeEffAonToRstPorIoDiv2AboveRise_A	23277556	8139	0	0
CascadeEffAonToRstPorIoDiv4AboveFall_A	11638457	8139	0	0
CascadeEffAonToRstPorIoDiv4AboveRise_A	11638457	8139	0	0
CascadeEffAonToRstPorUcbAboveFall_A	23277769	8139	0	0
CascadeEffAonToRstPorUcbAboveRise_A	23277769	8139	0	0
CascadeLcToLcAboveFall_A	48495433	19813	0	0
CascadeLcToLcAboveRise_A	48495433	19813	0	0
CascadeLcToLcAonAboveFall_A	1469451	19813	0	0
CascadeLcToLcAonAboveRise_A	1469451	19813	0	0
CascadeLcToLcShadowedAboveFall_A	48495433	19813	0	0
CascadeLcToLcShadowedAboveRise_A	48495433	19813	0	0
CascadePorToAonAboveFall_A	1469451	6675	0	0
CascadeSysToSysAboveFall_A	48495433	19813	0	0
CascadeSysToSysAboveRise_A	48495433	19813	0	0
ScanRstToAonRise_A	1469451	188	0	0
StablePorToAonRise_A	1469451	8139	0	0
g_power_domains[0].CascadeLcToSysAboveFall_A	10353383	19813	0	0
g_power_domains[0].CascadeLcToSysAboveRise_A	10353383	19813	0	0
g_power_domains[0].CascadeLocalRstToLcAboveFall_A	10353383	19813	0	0
g_power_domains[0].CascadeLocalRstToLcAboveRise_A	10353383	19813	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A	11638457	19813	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A	11638457	19813	0	0
g_power_domains[1].CascadeLcToSysAboveFall_A	10353383	19813	0	0
g_power_domains[1].CascadeLcToSysAboveRise_A	10353383	19813	0	0
g_power_domains[1].CascadeLocalRstToLcAboveFall_A	10353383	19813	0	0
g_power_domains[1].CascadeLocalRstToLcAboveRise_A	10353383	19813	0	0

CascadeEffAonToRstPorAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	48495433	8139	0	0
T1	11902	2	0	0
T2	20272	2	0	0
T3	22614	2	0	0
T4	7088	1	0	0
T5	43138	1	0	0
T6	7790	2	0	0
T7	319247	31	0	0
T8	13139	2	0	0
T9	6518	1	0	0
T10	17137	2	0	0

CascadeEffAonToRstPorAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	48495433	8139	0	0
T1	11902	2	0	0
T2	20272	2	0	0
T3	22614	2	0	0
T4	7088	1	0	0
T5	43138	1	0	0
T6	7790	2	0	0
T7	319247	31	0	0
T8	13139	2	0	0
T9	6518	1	0	0
T10	17137	2	0	0

CascadeEffAonToRstPorIoAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	46554336	8139	0	0
T1	11429	2	0	0
T2	19459	2	0	0
T3	21709	2	0	0
T4	6803	1	0	0
T5	41410	1	0	0
T6	7478	2	0	0
T7	306434	31	0	0
T8	12613	2	0	0
T9	6257	1	0	0
T10	16450	2	0	0

CascadeEffAonToRstPorIoAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	46554336	8139	0	0
T1	11429	2	0	0
T2	19459	2	0	0
T3	21709	2	0	0
T4	6803	1	0	0
T5	41410	1	0	0
T6	7478	2	0	0
T7	306434	31	0	0
T8	12613	2	0	0
T9	6257	1	0	0
T10	16450	2	0	0

CascadeEffAonToRstPorIoDiv2AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23277556	8139	0	0
T1	5710	2	0	0
T2	9730	2	0	0
T3	10855	2	0	0
T4	3401	1	0	0
T5	20706	1	0	0
T6	3739	2	0	0
T7	153224	31	0	0
T8	6307	2	0	0
T9	3129	1	0	0
T10	8227	2	0	0

CascadeEffAonToRstPorIoDiv2AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23277556	8139	0	0
T1	5710	2	0	0
T2	9730	2	0	0
T3	10855	2	0	0
T4	3401	1	0	0
T5	20706	1	0	0
T6	3739	2	0	0
T7	153224	31	0	0
T8	6307	2	0	0
T9	3129	1	0	0
T10	8227	2	0	0

CascadeEffAonToRstPorIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11638457	8139	0	0
T1	2855	2	0	0
T2	4864	2	0	0
T3	5426	2	0	0
T4	1700	1	0	0
T5	10353	1	0	0
T6	1869	2	0	0
T7	76613	31	0	0
T8	3152	2	0	0
T9	1563	1	0	0
T10	4111	2	0	0

CascadeEffAonToRstPorIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11638457	8139	0	0
T1	2855	2	0	0
T2	4864	2	0	0
T3	5426	2	0	0
T4	1700	1	0	0
T5	10353	1	0	0
T6	1869	2	0	0
T7	76613	31	0	0
T8	3152	2	0	0
T9	1563	1	0	0
T10	4111	2	0	0

CascadeEffAonToRstPorUcbAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23277769	8139	0	0
T1	5710	2	0	0
T2	9730	2	0	0
T3	10855	2	0	0
T4	3401	1	0	0
T5	20706	1	0	0
T6	3739	2	0	0
T7	153245	31	0	0
T8	6307	2	0	0
T9	3129	1	0	0
T10	8223	2	0	0

CascadeEffAonToRstPorUcbAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23277769	8139	0	0
T1	5710	2	0	0
T2	9730	2	0	0
T3	10855	2	0	0
T4	3401	1	0	0
T5	20706	1	0	0
T6	3739	2	0	0
T7	153245	31	0	0
T8	6307	2	0	0
T9	3129	1	0	0
T10	8223	2	0	0

CascadeLcToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	48495433	19813	0	0
T1	11902	6	0	0
T2	20272	6	0	0
T3	22614	2	0	0
T4	7088	1	0	0
T5	43138	1	0	0
T6	7790	2	0	0
T7	319247	92	0	0
T8	13139	2	0	0
T9	6518	1	0	0
T10	17137	6	0	0

CascadeLcToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	48495433	19813	0	0
T1	11902	6	0	0
T2	20272	6	0	0
T3	22614	2	0	0
T4	7088	1	0	0
T5	43138	1	0	0
T6	7790	2	0	0
T7	319247	92	0	0
T8	13139	2	0	0
T9	6518	1	0	0
T10	17137	6	0	0

CascadeLcToLcAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1469451	19813	0	0
T1	355	6	0	0
T2	607	6	0	0
T3	676	2	0	0
T4	211	1	0	0
T5	1292	1	0	0
T6	233	2	0	0
T7	9677	92	0	0
T8	394	2	0	0
T9	195	1	0	0
T10	512	6	0	0

CascadeLcToLcAonAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1469451	19813	0	0
T1	355	6	0	0
T2	607	6	0	0
T3	676	2	0	0
T4	211	1	0	0
T5	1292	1	0	0
T6	233	2	0	0
T7	9677	92	0	0
T8	394	2	0	0
T9	195	1	0	0
T10	512	6	0	0

CascadeLcToLcShadowedAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	48495433	19813	0	0
T1	11902	6	0	0
T2	20272	6	0	0
T3	22614	2	0	0
T4	7088	1	0	0
T5	43138	1	0	0
T6	7790	2	0	0
T7	319247	92	0	0
T8	13139	2	0	0
T9	6518	1	0	0
T10	17137	6	0	0

CascadeLcToLcShadowedAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	48495433	19813	0	0
T1	11902	6	0	0
T2	20272	6	0	0
T3	22614	2	0	0
T4	7088	1	0	0
T5	43138	1	0	0
T6	7790	2	0	0
T7	319247	92	0	0
T8	13139	2	0	0
T9	6518	1	0	0
T10	17137	6	0	0

CascadePorToAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1469451	6675	0	0
T1	355	1	0	0
T2	607	1	0	0
T3	676	21	0	0
T4	211	1	0	0
T5	1292	1	0	0
T6	233	4	0	0
T7	9677	18	0	0
T8	394	8	0	0
T9	195	1	0	0
T10	512	1	0	0

CascadeSysToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	48495433	19813	0	0
T1	11902	6	0	0
T2	20272	6	0	0
T3	22614	2	0	0
T4	7088	1	0	0
T5	43138	1	0	0
T6	7790	2	0	0
T7	319247	92	0	0
T8	13139	2	0	0
T9	6518	1	0	0
T10	17137	6	0	0

CascadeSysToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	48495433	19813	0	0
T1	11902	6	0	0
T2	20272	6	0	0
T3	22614	2	0	0
T4	7088	1	0	0
T5	43138	1	0	0
T6	7790	2	0	0
T7	319247	92	0	0
T8	13139	2	0	0
T9	6518	1	0	0
T10	17137	6	0	0

ScanRstToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1469451	188	0	0
T2	607	1	0	0
T3	676	0	0	0
T4	211	0	0	0
T5	1292	0	0	0
T6	233	0	0	0
T7	9677	0	0	0
T8	394	0	0	0
T9	195	0	0	0
T10	512	0	0	0
T11	3781	0	0	0
T12	0	2	0	0
T13	0	1	0	0
T33	0	2	0	0
T35	0	6	0	0
T48	0	4	0	0
T99	0	2	0	0
T104	0	2	0	0
T105	0	1	0	0
T107	0	14	0	0

StablePorToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1469451	8139	0	0
T1	355	2	0	0
T2	607	2	0	0
T3	676	2	0	0
T4	211	1	0	0
T5	1292	1	0	0
T6	233	2	0	0
T7	9677	31	0	0
T8	394	2	0	0
T9	195	1	0	0
T10	512	2	0	0

g_power_domains[0].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10353383	19813	0	0
T1	2614	6	0	0
T2	4580	6	0	0
T3	5384	2	0	0
T4	1609	1	0	0
T5	10334	1	0	0
T6	1730	2	0	0
T7	70581	92	0	0
T8	3086	2	0	0
T9	1521	1	0	0
T10	3824	6	0	0

g_power_domains[0].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10353383	19813	0	0
T1	2614	6	0	0
T2	4580	6	0	0
T3	5384	2	0	0
T4	1609	1	0	0
T5	10334	1	0	0
T6	1730	2	0	0
T7	70581	92	0	0
T8	3086	2	0	0
T9	1521	1	0	0
T10	3824	6	0	0

g_power_domains[0].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10353383	19813	0	0
T1	2614	6	0	0
T2	4580	6	0	0
T3	5384	2	0	0
T4	1609	1	0	0
T5	10334	1	0	0
T6	1730	2	0	0
T7	70581	92	0	0
T8	3086	2	0	0
T9	1521	1	0	0
T10	3824	6	0	0

g_power_domains[0].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10353383	19813	0	0
T1	2614	6	0	0
T2	4580	6	0	0
T3	5384	2	0	0
T4	1609	1	0	0
T5	10334	1	0	0
T6	1730	2	0	0
T7	70581	92	0	0
T8	3086	2	0	0
T9	1521	1	0	0
T10	3824	6	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11638457	19813	0	0
T1	2855	6	0	0
T2	4864	6	0	0
T3	5426	2	0	0
T4	1700	1	0	0
T5	10353	1	0	0
T6	1869	2	0	0
T7	76613	92	0	0
T8	3152	2	0	0
T9	1563	1	0	0
T10	4111	6	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11638457	19813	0	0
T1	2855	6	0	0
T2	4864	6	0	0
T3	5426	2	0	0
T4	1700	1	0	0
T5	10353	1	0	0
T6	1869	2	0	0
T7	76613	92	0	0
T8	3152	2	0	0
T9	1563	1	0	0
T10	4111	6	0	0

g_power_domains[1].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10353383	19813	0	0
T1	2614	6	0	0
T2	4580	6	0	0
T3	5384	2	0	0
T4	1609	1	0	0
T5	10334	1	0	0
T6	1730	2	0	0
T7	70581	92	0	0
T8	3086	2	0	0
T9	1521	1	0	0
T10	3824	6	0	0

g_power_domains[1].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10353383	19813	0	0
T1	2614	6	0	0
T2	4580	6	0	0
T3	5384	2	0	0
T4	1609	1	0	0
T5	10334	1	0	0
T6	1730	2	0	0
T7	70581	92	0	0
T8	3086	2	0	0
T9	1521	1	0	0
T10	3824	6	0	0

g_power_domains[1].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10353383	19813	0	0
T1	2614	6	0	0
T2	4580	6	0	0
T3	5384	2	0	0
T4	1609	1	0	0
T5	10334	1	0	0
T6	1730	2	0	0
T7	70581	92	0	0
T8	3086	2	0	0
T9	1521	1	0	0
T10	3824	6	0	0

g_power_domains[1].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10353383	19813	0	0
T1	2614	6	0	0
T2	4580	6	0	0
T3	5384	2	0	0
T4	1609	1	0	0
T5	10334	1	0	0
T6	1730	2	0	0
T7	70581	92	0	0
T8	3086	2	0	0
T9	1521	1	0	0
T10	3824	6	0	0