Unified Coverage Report :: Module :: rstmgr_sw_rst_sva_if

Module : rstmgr_sw_rst_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_sw_rst_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_sw_rst_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_sw_rst_sva_if

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
21	8	8

---

Cond Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Covered	Percent
Conditions	24	24	100.00
Logical	24	24	100.00
Non-Logical	0	0
Event	0	0

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[0])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T7,T12
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[1])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T5,T7
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[2])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T7,T12
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[3])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T7,T12
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[4])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T5
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[5])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T5,T7
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[6])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T5,T7
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[7])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T7,T12
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions[0].RstEnOff_A	11638457	12573	0	0
gen_assertions[0].RstEnOn_A	11638457	1051	0	0
gen_assertions[0].RstNOff_A	11638457	12573	0	0
gen_assertions[0].RstNOn_A	11638457	1051	0	0
gen_assertions[1].RstEnOff_A	46554336	11441	0	0
gen_assertions[1].RstEnOn_A	46554336	1049	0	0
gen_assertions[1].RstNOff_A	46554336	11441	0	0
gen_assertions[1].RstNOn_A	46554336	1049	0	0
gen_assertions[2].RstEnOff_A	23277556	11473	0	0
gen_assertions[2].RstEnOn_A	23277556	1031	0	0
gen_assertions[2].RstNOff_A	23277556	11473	0	0
gen_assertions[2].RstNOn_A	23277556	1031	0	0
gen_assertions[3].RstEnOff_A	23277769	11538	0	0
gen_assertions[3].RstEnOn_A	23277769	1095	0	0
gen_assertions[3].RstNOff_A	23277769	11538	0	0
gen_assertions[3].RstNOn_A	23277769	1095	0	0
gen_assertions[4].RstEnOff_A	1469451	19611	0	0
gen_assertions[4].RstEnOn_A	1469451	1135	0	0
gen_assertions[4].RstNOff_A	1469451	19611	0	0
gen_assertions[4].RstNOn_A	1469451	1135	0	0
gen_assertions[5].RstEnOff_A	11638457	12796	0	0
gen_assertions[5].RstEnOn_A	11638457	1159	0	0
gen_assertions[5].RstNOff_A	11638457	12796	0	0
gen_assertions[5].RstNOn_A	11638457	1159	0	0
gen_assertions[6].RstEnOff_A	11638457	12857	0	0
gen_assertions[6].RstEnOn_A	11638457	1229	0	0
gen_assertions[6].RstNOff_A	11638457	12857	0	0
gen_assertions[6].RstNOn_A	11638457	1229	0	0
gen_assertions[7].RstEnOff_A	11638457	12905	0	0
gen_assertions[7].RstEnOn_A	11638457	1272	0	0
gen_assertions[7].RstNOff_A	11638457	12905	0	0
gen_assertions[7].RstNOn_A	11638457	1272	0	0

gen_assertions[0].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11638457	12573	0	0
T1	2855	4	0	0
T2	4864	4	0	0
T3	5426	0	0	0
T4	1700	0	0	0
T5	10353	3	0	0
T6	1869	0	0	0
T7	76613	86	0	0
T8	3152	0	0	0
T9	1563	0	0	0
T10	4111	4	0	0
T11	0	30	0	0
T12	0	43	0	0
T13	0	23	0	0
T21	0	75	0	0
T66	0	5	0	0

gen_assertions[0].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11638457	1051	0	0
T5	10353	3	0	0
T6	1869	0	0	0
T7	76613	28	0	0
T8	3152	0	0	0
T9	1563	0	0	0
T10	4111	0	0	0
T11	29877	0	0	0
T12	51921	8	0	0
T13	34486	0	0	0
T23	0	1	0	0
T33	0	16	0	0
T34	0	17	0	0
T35	0	30	0	0
T37	0	1	0	0
T66	8222	5	0	0
T84	0	3	0	0

gen_assertions[0].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11638457	12573	0	0
T1	2855	4	0	0
T2	4864	4	0	0
T3	5426	0	0	0
T4	1700	0	0	0
T5	10353	3	0	0
T6	1869	0	0	0
T7	76613	86	0	0
T8	3152	0	0	0
T9	1563	0	0	0
T10	4111	4	0	0
T11	0	30	0	0
T12	0	43	0	0
T13	0	23	0	0
T21	0	75	0	0
T66	0	5	0	0

gen_assertions[0].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11638457	1051	0	0
T5	10353	3	0	0
T6	1869	0	0	0
T7	76613	28	0	0
T8	3152	0	0	0
T9	1563	0	0	0
T10	4111	0	0	0
T11	29877	0	0	0
T12	51921	8	0	0
T13	34486	0	0	0
T23	0	1	0	0
T33	0	16	0	0
T34	0	17	0	0
T35	0	30	0	0
T37	0	1	0	0
T66	8222	5	0	0
T84	0	3	0	0

gen_assertions[1].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	46554336	11441	0	0
T1	11429	4	0	0
T2	19459	5	0	0
T3	21709	0	0	0
T4	6803	0	0	0
T5	41410	3	0	0
T6	7478	0	0	0
T7	306434	92	0	0
T8	12613	0	0	0
T9	6257	0	0	0
T10	16450	4	0	0
T11	0	27	0	0
T12	0	37	0	0
T13	0	22	0	0
T21	0	70	0	0
T66	0	5	0	0

gen_assertions[1].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	46554336	1049	0	0
T2	19459	1	0	0
T3	21709	0	0	0
T4	6803	0	0	0
T5	41410	3	0	0
T6	7478	0	0	0
T7	306434	34	0	0
T8	12613	0	0	0
T9	6257	0	0	0
T10	16450	0	0	0
T11	119516	0	0	0
T12	0	7	0	0
T22	0	1	0	0
T33	0	21	0	0
T34	0	17	0	0
T35	0	32	0	0
T37	0	3	0	0
T66	0	5	0	0

gen_assertions[1].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	46554336	11441	0	0
T1	11429	4	0	0
T2	19459	5	0	0
T3	21709	0	0	0
T4	6803	0	0	0
T5	41410	3	0	0
T6	7478	0	0	0
T7	306434	92	0	0
T8	12613	0	0	0
T9	6257	0	0	0
T10	16450	4	0	0
T11	0	27	0	0
T12	0	37	0	0
T13	0	22	0	0
T21	0	70	0	0
T66	0	5	0	0

gen_assertions[1].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	46554336	1049	0	0
T2	19459	1	0	0
T3	21709	0	0	0
T4	6803	0	0	0
T5	41410	3	0	0
T6	7478	0	0	0
T7	306434	34	0	0
T8	12613	0	0	0
T9	6257	0	0	0
T10	16450	0	0	0
T11	119516	0	0	0
T12	0	7	0	0
T22	0	1	0	0
T33	0	21	0	0
T34	0	17	0	0
T35	0	32	0	0
T37	0	3	0	0
T66	0	5	0	0

gen_assertions[2].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23277556	11473	0	0
T1	5710	4	0	0
T2	9730	4	0	0
T3	10855	0	0	0
T4	3401	0	0	0
T5	20706	6	0	0
T6	3739	0	0	0
T7	153224	95	0	0
T8	6307	0	0	0
T9	3129	0	0	0
T10	8227	4	0	0
T11	0	27	0	0
T12	0	37	0	0
T13	0	22	0	0
T21	0	70	0	0
T66	0	6	0	0

gen_assertions[2].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23277556	1031	0	0
T5	20706	6	0	0
T6	3739	0	0	0
T7	153224	39	0	0
T8	6307	0	0	0
T9	3129	0	0	0
T10	8227	0	0	0
T11	59760	0	0	0
T12	103861	7	0	0
T13	68964	0	0	0
T23	0	1	0	0
T33	0	21	0	0
T34	0	19	0	0
T35	0	27	0	0
T37	0	3	0	0
T66	16447	6	0	0
T84	0	1	0	0

gen_assertions[2].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23277556	11473	0	0
T1	5710	4	0	0
T2	9730	4	0	0
T3	10855	0	0	0
T4	3401	0	0	0
T5	20706	6	0	0
T6	3739	0	0	0
T7	153224	95	0	0
T8	6307	0	0	0
T9	3129	0	0	0
T10	8227	4	0	0
T11	0	27	0	0
T12	0	37	0	0
T13	0	22	0	0
T21	0	70	0	0
T66	0	6	0	0

gen_assertions[2].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23277556	1031	0	0
T5	20706	6	0	0
T6	3739	0	0	0
T7	153224	39	0	0
T8	6307	0	0	0
T9	3129	0	0	0
T10	8227	0	0	0
T11	59760	0	0	0
T12	103861	7	0	0
T13	68964	0	0	0
T23	0	1	0	0
T33	0	21	0	0
T34	0	19	0	0
T35	0	27	0	0
T37	0	3	0	0
T66	16447	6	0	0
T84	0	1	0	0

gen_assertions[3].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23277769	11538	0	0
T1	5710	4	0	0
T2	9730	4	0	0
T3	10855	0	0	0
T4	3401	0	0	0
T5	20706	6	0	0
T6	3739	0	0	0
T7	153245	91	0	0
T8	6307	0	0	0
T9	3129	0	0	0
T10	8223	4	0	0
T11	0	27	0	0
T12	0	36	0	0
T13	0	22	0	0
T21	0	70	0	0
T66	0	9	0	0

gen_assertions[3].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23277769	1095	0	0
T5	20706	6	0	0
T6	3739	0	0	0
T7	153245	35	0	0
T8	6307	0	0	0
T9	3129	0	0	0
T10	8223	0	0	0
T11	59756	0	0	0
T12	103855	7	0	0
T13	68968	0	0	0
T33	0	17	0	0
T34	0	16	0	0
T35	0	29	0	0
T37	0	5	0	0
T66	16447	9	0	0
T85	0	5	0	0
T86	0	5	0	0

gen_assertions[3].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23277769	11538	0	0
T1	5710	4	0	0
T2	9730	4	0	0
T3	10855	0	0	0
T4	3401	0	0	0
T5	20706	6	0	0
T6	3739	0	0	0
T7	153245	91	0	0
T8	6307	0	0	0
T9	3129	0	0	0
T10	8223	4	0	0
T11	0	27	0	0
T12	0	36	0	0
T13	0	22	0	0
T21	0	70	0	0
T66	0	9	0	0

gen_assertions[3].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23277769	1095	0	0
T5	20706	6	0	0
T6	3739	0	0	0
T7	153245	35	0	0
T8	6307	0	0	0
T9	3129	0	0	0
T10	8223	0	0	0
T11	59756	0	0	0
T12	103855	7	0	0
T13	68968	0	0	0
T33	0	17	0	0
T34	0	16	0	0
T35	0	29	0	0
T37	0	5	0	0
T66	16447	9	0	0
T85	0	5	0	0
T86	0	5	0	0

gen_assertions[4].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1469451	19611	0	0
T1	355	7	0	0
T2	607	7	0	0
T3	676	2	0	0
T4	211	1	0	0
T5	1292	8	0	0
T6	233	2	0	0
T7	9677	126	0	0
T8	394	2	0	0
T9	195	1	0	0
T10	512	6	0	0

gen_assertions[4].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1469451	1135	0	0
T1	355	1	0	0
T2	607	1	0	0
T3	676	0	0	0
T4	211	0	0	0
T5	1292	7	0	0
T6	233	0	0	0
T7	9677	38	0	0
T8	394	0	0	0
T9	195	0	0	0
T10	512	0	0	0
T12	0	7	0	0
T33	0	17	0	0
T34	0	19	0	0
T35	0	27	0	0
T37	0	5	0	0
T66	0	7	0	0

gen_assertions[4].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1469451	19611	0	0
T1	355	7	0	0
T2	607	7	0	0
T3	676	2	0	0
T4	211	1	0	0
T5	1292	8	0	0
T6	233	2	0	0
T7	9677	126	0	0
T8	394	2	0	0
T9	195	1	0	0
T10	512	6	0	0

gen_assertions[4].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1469451	1135	0	0
T1	355	1	0	0
T2	607	1	0	0
T3	676	0	0	0
T4	211	0	0	0
T5	1292	7	0	0
T6	233	0	0	0
T7	9677	38	0	0
T8	394	0	0	0
T9	195	0	0	0
T10	512	0	0	0
T12	0	7	0	0
T33	0	17	0	0
T34	0	19	0	0
T35	0	27	0	0
T37	0	5	0	0
T66	0	7	0	0

gen_assertions[5].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11638457	12796	0	0
T1	2855	4	0	0
T2	4864	5	0	0
T3	5426	0	0	0
T4	1700	0	0	0
T5	10353	9	0	0
T6	1869	0	0	0
T7	76613	93	0	0
T8	3152	0	0	0
T9	1563	0	0	0
T10	4111	4	0	0
T11	0	30	0	0
T12	0	42	0	0
T13	0	23	0	0
T21	0	75	0	0
T66	0	9	0	0

gen_assertions[5].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11638457	1159	0	0
T2	4864	1	0	0
T3	5426	0	0	0
T4	1700	0	0	0
T5	10353	9	0	0
T6	1869	0	0	0
T7	76613	33	0	0
T8	3152	0	0	0
T9	1563	0	0	0
T10	4111	0	0	0
T11	29877	0	0	0
T12	0	6	0	0
T23	0	1	0	0
T33	0	15	0	0
T34	0	17	0	0
T35	0	33	0	0
T37	0	6	0	0
T66	0	9	0	0

gen_assertions[5].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11638457	12796	0	0
T1	2855	4	0	0
T2	4864	5	0	0
T3	5426	0	0	0
T4	1700	0	0	0
T5	10353	9	0	0
T6	1869	0	0	0
T7	76613	93	0	0
T8	3152	0	0	0
T9	1563	0	0	0
T10	4111	4	0	0
T11	0	30	0	0
T12	0	42	0	0
T13	0	23	0	0
T21	0	75	0	0
T66	0	9	0	0

gen_assertions[5].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11638457	1159	0	0
T2	4864	1	0	0
T3	5426	0	0	0
T4	1700	0	0	0
T5	10353	9	0	0
T6	1869	0	0	0
T7	76613	33	0	0
T8	3152	0	0	0
T9	1563	0	0	0
T10	4111	0	0	0
T11	29877	0	0	0
T12	0	6	0	0
T23	0	1	0	0
T33	0	15	0	0
T34	0	17	0	0
T35	0	33	0	0
T37	0	6	0	0
T66	0	9	0	0

gen_assertions[6].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11638457	12857	0	0
T1	2855	4	0	0
T2	4864	5	0	0
T3	5426	0	0	0
T4	1700	0	0	0
T5	10353	10	0	0
T6	1869	0	0	0
T7	76613	96	0	0
T8	3152	0	0	0
T9	1563	0	0	0
T10	4111	4	0	0
T11	0	30	0	0
T12	0	40	0	0
T13	0	23	0	0
T21	0	75	0	0
T66	0	12	0	0

gen_assertions[6].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11638457	1229	0	0
T2	4864	1	0	0
T3	5426	0	0	0
T4	1700	0	0	0
T5	10353	10	0	0
T6	1869	0	0	0
T7	76613	36	0	0
T8	3152	0	0	0
T9	1563	0	0	0
T10	4111	0	0	0
T11	29877	0	0	0
T12	0	5	0	0
T33	0	19	0	0
T34	0	19	0	0
T35	0	30	0	0
T37	0	8	0	0
T66	0	12	0	0
T85	0	7	0	0

gen_assertions[6].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11638457	12857	0	0
T1	2855	4	0	0
T2	4864	5	0	0
T3	5426	0	0	0
T4	1700	0	0	0
T5	10353	10	0	0
T6	1869	0	0	0
T7	76613	96	0	0
T8	3152	0	0	0
T9	1563	0	0	0
T10	4111	4	0	0
T11	0	30	0	0
T12	0	40	0	0
T13	0	23	0	0
T21	0	75	0	0
T66	0	12	0	0

gen_assertions[6].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11638457	1229	0	0
T2	4864	1	0	0
T3	5426	0	0	0
T4	1700	0	0	0
T5	10353	10	0	0
T6	1869	0	0	0
T7	76613	36	0	0
T8	3152	0	0	0
T9	1563	0	0	0
T10	4111	0	0	0
T11	29877	0	0	0
T12	0	5	0	0
T33	0	19	0	0
T34	0	19	0	0
T35	0	30	0	0
T37	0	8	0	0
T66	0	12	0	0
T85	0	7	0	0

gen_assertions[7].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11638457	12905	0	0
T1	2855	4	0	0
T2	4864	4	0	0
T3	5426	0	0	0
T4	1700	0	0	0
T5	10353	8	0	0
T6	1869	0	0	0
T7	76613	94	0	0
T8	3152	0	0	0
T9	1563	0	0	0
T10	4111	4	0	0
T11	0	30	0	0
T12	0	40	0	0
T13	0	23	0	0
T21	0	75	0	0
T66	0	11	0	0

gen_assertions[7].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11638457	1272	0	0
T5	10353	8	0	0
T6	1869	0	0	0
T7	76613	35	0	0
T8	3152	0	0	0
T9	1563	0	0	0
T10	4111	0	0	0
T11	29877	0	0	0
T12	51921	5	0	0
T13	34486	0	0	0
T33	0	19	0	0
T34	0	16	0	0
T35	0	33	0	0
T37	0	9	0	0
T66	8222	11	0	0
T85	0	9	0	0
T86	0	10	0	0

gen_assertions[7].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11638457	12905	0	0
T1	2855	4	0	0
T2	4864	4	0	0
T3	5426	0	0	0
T4	1700	0	0	0
T5	10353	8	0	0
T6	1869	0	0	0
T7	76613	94	0	0
T8	3152	0	0	0
T9	1563	0	0	0
T10	4111	4	0	0
T11	0	30	0	0
T12	0	40	0	0
T13	0	23	0	0
T21	0	75	0	0
T66	0	11	0	0

gen_assertions[7].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11638457	1272	0	0
T5	10353	8	0	0
T6	1869	0	0	0
T7	76613	35	0	0
T8	3152	0	0	0
T9	1563	0	0	0
T10	4111	0	0	0
T11	29877	0	0	0
T12	51921	5	0	0
T13	34486	0	0	0
T33	0	19	0	0
T34	0	16	0	0
T35	0	33	0	0
T37	0	9	0	0
T66	8222	11	0	0
T85	0	9	0	0
T86	0	10	0	0