Unified Coverage Report :: Module :: rstmgr_csr_assert_fpv

Module : rstmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rstmgr_csr_assert_0/rstmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rstmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rstmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	19	19	100.00	19	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	19	19	100.00	19	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	11190720	9138	0	0
alert_regwen_rd_A	11190720	3988	0	0
cpu_regwen_rd_A	11190720	4172	0	0
sw_rst_ctrl_n_0_rd_A	11190720	7678	0	0
sw_rst_ctrl_n_1_rd_A	11190720	8014	0	0
sw_rst_ctrl_n_2_rd_A	11190720	7873	0	0
sw_rst_ctrl_n_3_rd_A	11190720	7959	0	0
sw_rst_ctrl_n_4_rd_A	11190720	7652	0	0
sw_rst_ctrl_n_5_rd_A	11190720	7781	0	0
sw_rst_ctrl_n_6_rd_A	11190720	7525	0	0
sw_rst_ctrl_n_7_rd_A	11190720	7930	0	0
sw_rst_regwen_0_rd_A	11190720	4762	0	0
sw_rst_regwen_1_rd_A	11190720	4734	0	0
sw_rst_regwen_2_rd_A	11190720	4464	0	0
sw_rst_regwen_3_rd_A	11190720	4651	0	0
sw_rst_regwen_4_rd_A	11190720	4738	0	0
sw_rst_regwen_5_rd_A	11190720	4397	0	0
sw_rst_regwen_6_rd_A	11190720	4683	0	0
sw_rst_regwen_7_rd_A	11190720	4564	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11190720	9138	0	0
T70	10749	1	0	0
T71	5416	299	0	0
T73	12155	656	0	0
T74	14618	422	0	0
T88	17800	2	0	0
T90	7378	364	0	0
T91	4676	11	0	0
T92	21737	2	0	0
T93	11018	380	0	0
T95	16936	3	0	0

alert_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11190720	3988	0	0
T12	47482	73	0	0
T13	30490	50	0	0
T14	2627	0	0	0
T21	52737	0	0	0
T22	5950	0	0	0
T23	5197	0	0	0
T33	171136	226	0	0
T34	91381	77	0	0
T47	0	39	0	0
T48	0	112	0	0
T49	0	52	0	0
T51	1183	0	0	0
T61	0	66	0	0
T66	8132	0	0	0
T82	0	55	0	0
T106	0	37	0	0

cpu_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11190720	4172	0	0
T12	47482	56	0	0
T13	30490	34	0	0
T14	2627	0	0	0
T21	52737	0	0	0
T22	5950	0	0	0
T23	5197	0	0	0
T33	171136	227	0	0
T34	91381	113	0	0
T47	0	57	0	0
T48	0	120	0	0
T49	0	63	0	0
T51	1183	0	0	0
T61	0	104	0	0
T66	8132	0	0	0
T82	0	80	0	0
T106	0	34	0	0

sw_rst_ctrl_n_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11190720	7678	0	0
T5	10334	150	0	0
T6	1730	0	0	0
T7	70581	0	0	0
T8	3086	0	0	0
T9	1521	0	0	0
T10	3824	0	0	0
T11	25231	0	0	0
T12	47482	141	0	0
T13	30490	32	0	0
T22	0	6	0	0
T23	0	4	0	0
T33	0	517	0	0
T34	0	323	0	0
T37	0	132	0	0
T43	0	19	0	0
T66	8132	0	0	0
T124	0	28	0	0

sw_rst_ctrl_n_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11190720	8014	0	0
T5	10334	187	0	0
T6	1730	0	0	0
T7	70581	0	0	0
T8	3086	0	0	0
T9	1521	0	0	0
T10	3824	0	0	0
T11	25231	0	0	0
T12	47482	121	0	0
T13	30490	44	0	0
T22	0	16	0	0
T23	0	6	0	0
T33	0	478	0	0
T34	0	312	0	0
T37	0	129	0	0
T43	0	31	0	0
T66	8132	0	0	0
T124	0	34	0	0

sw_rst_ctrl_n_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11190720	7873	0	0
T5	10334	109	0	0
T6	1730	0	0	0
T7	70581	0	0	0
T8	3086	0	0	0
T9	1521	0	0	0
T10	3824	0	0	0
T11	25231	0	0	0
T12	47482	114	0	0
T13	30490	48	0	0
T22	0	10	0	0
T23	0	10	0	0
T33	0	539	0	0
T34	0	334	0	0
T37	0	139	0	0
T43	0	21	0	0
T66	8132	0	0	0
T124	0	31	0	0

sw_rst_ctrl_n_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11190720	7959	0	0
T5	10334	160	0	0
T6	1730	0	0	0
T7	70581	0	0	0
T8	3086	0	0	0
T9	1521	0	0	0
T10	3824	0	0	0
T11	25231	0	0	0
T12	47482	125	0	0
T13	30490	62	0	0
T22	0	17	0	0
T23	0	6	0	0
T33	0	481	0	0
T34	0	313	0	0
T37	0	102	0	0
T43	0	22	0	0
T66	8132	0	0	0
T124	0	19	0	0

sw_rst_ctrl_n_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11190720	7652	0	0
T5	10334	143	0	0
T6	1730	0	0	0
T7	70581	0	0	0
T8	3086	0	0	0
T9	1521	0	0	0
T10	3824	0	0	0
T11	25231	0	0	0
T12	47482	121	0	0
T13	30490	48	0	0
T22	0	21	0	0
T23	0	6	0	0
T33	0	472	0	0
T34	0	299	0	0
T37	0	157	0	0
T43	0	14	0	0
T66	8132	0	0	0
T124	0	23	0	0

sw_rst_ctrl_n_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11190720	7781	0	0
T5	10334	131	0	0
T6	1730	0	0	0
T7	70581	0	0	0
T8	3086	0	0	0
T9	1521	0	0	0
T10	3824	0	0	0
T11	25231	0	0	0
T12	47482	147	0	0
T13	30490	48	0	0
T22	0	7	0	0
T23	0	6	0	0
T33	0	540	0	0
T34	0	342	0	0
T37	0	128	0	0
T43	0	24	0	0
T66	8132	0	0	0
T124	0	28	0	0

sw_rst_ctrl_n_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11190720	7525	0	0
T5	10334	156	0	0
T6	1730	0	0	0
T7	70581	0	0	0
T8	3086	0	0	0
T9	1521	0	0	0
T10	3824	0	0	0
T11	25231	0	0	0
T12	47482	130	0	0
T13	30490	26	0	0
T22	0	15	0	0
T23	0	7	0	0
T33	0	458	0	0
T34	0	311	0	0
T37	0	110	0	0
T43	0	10	0	0
T66	8132	0	0	0
T124	0	34	0	0

sw_rst_ctrl_n_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11190720	7930	0	0
T5	10334	168	0	0
T6	1730	0	0	0
T7	70581	0	0	0
T8	3086	0	0	0
T9	1521	0	0	0
T10	3824	0	0	0
T11	25231	0	0	0
T12	47482	140	0	0
T13	30490	39	0	0
T22	0	14	0	0
T23	0	12	0	0
T33	0	532	0	0
T34	0	334	0	0
T37	0	125	0	0
T43	0	19	0	0
T66	8132	0	0	0
T124	0	35	0	0

sw_rst_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11190720	4762	0	0
T5	10334	26	0	0
T6	1730	0	0	0
T7	70581	0	0	0
T8	3086	0	0	0
T9	1521	0	0	0
T10	3824	0	0	0
T11	25231	0	0	0
T12	47482	47	0	0
T13	30490	49	0	0
T22	0	10	0	0
T23	0	11	0	0
T33	0	260	0	0
T34	0	99	0	0
T37	0	23	0	0
T44	0	7	0	0
T47	0	54	0	0
T66	8132	0	0	0

sw_rst_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11190720	4734	0	0
T5	10334	24	0	0
T6	1730	0	0	0
T7	70581	0	0	0
T8	3086	0	0	0
T9	1521	0	0	0
T10	3824	0	0	0
T11	25231	0	0	0
T12	47482	62	0	0
T13	30490	37	0	0
T22	0	3	0	0
T23	0	10	0	0
T33	0	277	0	0
T34	0	128	0	0
T37	0	36	0	0
T44	0	9	0	0
T47	0	15	0	0
T66	8132	0	0	0

sw_rst_regwen_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11190720	4464	0	0
T5	10334	34	0	0
T6	1730	0	0	0
T7	70581	0	0	0
T8	3086	0	0	0
T9	1521	0	0	0
T10	3824	0	0	0
T11	25231	0	0	0
T12	47482	60	0	0
T13	30490	41	0	0
T22	0	4	0	0
T23	0	4	0	0
T33	0	232	0	0
T34	0	86	0	0
T37	0	30	0	0
T44	0	12	0	0
T47	0	47	0	0
T66	8132	0	0	0

sw_rst_regwen_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11190720	4651	0	0
T5	10334	45	0	0
T6	1730	0	0	0
T7	70581	0	0	0
T8	3086	0	0	0
T9	1521	0	0	0
T10	3824	0	0	0
T11	25231	0	0	0
T12	47482	37	0	0
T13	30490	36	0	0
T22	0	7	0	0
T23	0	7	0	0
T33	0	279	0	0
T34	0	126	0	0
T37	0	21	0	0
T44	0	12	0	0
T47	0	57	0	0
T66	8132	0	0	0

sw_rst_regwen_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11190720	4738	0	0
T5	10334	36	0	0
T6	1730	0	0	0
T7	70581	0	0	0
T8	3086	0	0	0
T9	1521	0	0	0
T10	3824	0	0	0
T11	25231	0	0	0
T12	47482	88	0	0
T13	30490	39	0	0
T22	0	3	0	0
T23	0	6	0	0
T33	0	249	0	0
T34	0	86	0	0
T37	0	34	0	0
T44	0	4	0	0
T47	0	58	0	0
T66	8132	0	0	0

sw_rst_regwen_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11190720	4397	0	0
T5	10334	36	0	0
T6	1730	0	0	0
T7	70581	0	0	0
T8	3086	0	0	0
T9	1521	0	0	0
T10	3824	0	0	0
T11	25231	0	0	0
T12	47482	67	0	0
T13	30490	12	0	0
T22	0	7	0	0
T33	0	252	0	0
T34	0	107	0	0
T37	0	60	0	0
T44	0	3	0	0
T47	0	31	0	0
T48	0	145	0	0
T66	8132	0	0	0

sw_rst_regwen_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11190720	4683	0	0
T5	10334	25	0	0
T6	1730	0	0	0
T7	70581	0	0	0
T8	3086	0	0	0
T9	1521	0	0	0
T10	3824	0	0	0
T11	25231	0	0	0
T12	47482	41	0	0
T13	30490	19	0	0
T22	0	7	0	0
T23	0	5	0	0
T33	0	312	0	0
T34	0	96	0	0
T37	0	26	0	0
T44	0	2	0	0
T47	0	56	0	0
T66	8132	0	0	0

sw_rst_regwen_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11190720	4564	0	0
T5	10334	16	0	0
T6	1730	0	0	0
T7	70581	0	0	0
T8	3086	0	0	0
T9	1521	0	0	0
T10	3824	0	0	0
T11	25231	0	0	0
T12	47482	46	0	0
T13	30490	34	0	0
T22	0	7	0	0
T23	0	2	0	0
T33	0	253	0	0
T34	0	94	0	0
T37	0	37	0	0
T44	0	9	0	0
T47	0	43	0	0
T66	8132	0	0	0