Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	556791	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

335768

1

T1

13

T3

347

T4

304

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	474529	1			T1	18		T3	443		T4	427
values[0x0]	208432	1			T1	12		T3	205		T4	190
values[0x1]	209598	1			T1	8		T3	192		T4	191

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	467099	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

425460

1

T1

15

T3

418

T4

374

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	6202	1			T3	3		T4	2		T5	27
valid_sources[0x01]	2904	1			T4	4		T5	17		T6	14
valid_sources[0x02]	5664	1			T3	9		T4	5		T5	28
valid_sources[0x03]	6639	1			T3	3		T4	2		T6	13
valid_sources[0x04]	2733	1			T3	1		T4	4		T5	3
valid_sources[0x05]	2919	1			T1	1		T3	6		T4	3
valid_sources[0x06]	3554	1			T3	2		T4	3		T5	3
valid_sources[0x07]	4013	1			T4	4		T5	6		T6	17
valid_sources[0x08]	2967	1			T3	4		T4	2		T5	24
valid_sources[0x09]	3068	1			T3	3		T4	3		T5	3
valid_sources[0x0a]	3223	1			T3	4		T4	2		T5	15
valid_sources[0x0b]	4446	1			T3	2		T4	2		T5	26
valid_sources[0x0c]	2969	1			T3	3		T4	4		T5	12
valid_sources[0x0d]	3063	1			T3	2		T4	6		T6	10
valid_sources[0x0e]	3025	1			T3	3		T5	15		T6	10
valid_sources[0x0f]	3811	1			T3	3		T4	5		T5	22
valid_sources[0x10]	4066	1			T3	7		T4	2		T5	15
valid_sources[0x11]	3864	1			T3	4		T4	7		T5	19
valid_sources[0x12]	3279	1			T3	6		T4	2		T5	3
valid_sources[0x13]	3610	1			T3	3		T4	5		T5	13
valid_sources[0x14]	5159	1			T3	6		T4	2		T5	9
valid_sources[0x15]	3180	1			T3	8		T4	3		T5	28
valid_sources[0x16]	3743	1			T1	2		T3	3		T4	4
valid_sources[0x17]	2929	1			T3	6		T4	6		T5	8
valid_sources[0x18]	3321	1			T3	6		T4	3		T5	11
valid_sources[0x19]	3090	1			T3	1		T4	5		T5	3
valid_sources[0x1a]	2926	1			T3	1		T4	2		T5	8
valid_sources[0x1b]	3932	1			T3	1		T4	2		T5	1
valid_sources[0x1c]	3604	1			T3	1		T4	2		T6	10
valid_sources[0x1d]	3745	1			T3	5		T4	4		T5	9
valid_sources[0x1e]	3254	1			T3	5		T4	5		T5	6
valid_sources[0x1f]	2906	1			T3	3		T4	1		T5	37
valid_sources[0x20]	3316	1			T4	4		T5	30		T6	21
valid_sources[0x21]	3805	1			T3	3		T4	1		T5	19
valid_sources[0x22]	3636	1			T4	3		T5	18		T6	16
valid_sources[0x23]	3441	1			T1	2		T3	3		T4	3
valid_sources[0x24]	3082	1			T3	6		T4	2		T5	11
valid_sources[0x25]	3199	1			T3	5		T4	1		T5	2
valid_sources[0x26]	3171	1			T1	1		T3	3		T4	4
valid_sources[0x27]	3345	1			T3	1		T4	5		T5	3
valid_sources[0x28]	4736	1			T3	2		T4	5		T5	2
valid_sources[0x29]	3348	1			T3	1		T4	3		T5	12
valid_sources[0x2a]	3894	1			T3	4		T4	2		T5	5
valid_sources[0x2b]	2521	1			T3	3		T4	2		T6	13
valid_sources[0x2c]	3210	1			T1	4		T3	5		T4	1
valid_sources[0x2d]	2513	1			T3	4		T4	7		T5	8
valid_sources[0x2e]	4134	1			T3	5		T4	5		T5	27
valid_sources[0x2f]	2482	1			T1	1		T3	1		T4	3
valid_sources[0x30]	2659	1			T1	1		T3	2		T4	1
valid_sources[0x31]	3376	1			T3	6		T4	6		T5	10
valid_sources[0x32]	2850	1			T3	4		T4	4		T6	12
valid_sources[0x33]	4414	1			T3	1		T5	3		T6	13
valid_sources[0x34]	3666	1			T3	2		T5	12		T6	10
valid_sources[0x35]	3483	1			T3	5		T4	2		T5	7
valid_sources[0x36]	2510	1			T3	2		T4	2		T5	21
valid_sources[0x37]	3870	1			T1	1		T3	2		T4	5
valid_sources[0x38]	3637	1			T3	5		T5	4		T6	8
valid_sources[0x39]	2888	1			T3	3		T4	2		T5	1
valid_sources[0x3a]	2886	1			T3	3		T4	2		T5	22
valid_sources[0x3b]	3233	1			T3	2		T4	2		T5	13
valid_sources[0x3c]	2914	1			T1	1		T3	2		T5	7
valid_sources[0x3d]	3435	1			T4	6		T6	10		T7	51
valid_sources[0x3e]	4141	1			T3	3		T4	3		T5	9
valid_sources[0x3f]	3098	1			T3	2		T4	10		T5	19
valid_sources[0x40]	3357	1			T3	7		T4	1		T5	24
valid_sources[0x41]	3141	1			T1	1		T3	3		T4	5
valid_sources[0x42]	2422	1			T3	1		T4	1		T5	6
valid_sources[0x43]	3252	1			T4	5		T6	23		T7	70
valid_sources[0x44]	3734	1			T3	3		T4	7		T5	12
valid_sources[0x45]	2883	1			T3	4		T4	2		T5	9
valid_sources[0x46]	6614	1			T1	1		T3	3		T4	5
valid_sources[0x47]	3058	1			T3	5		T4	5		T5	20
valid_sources[0x48]	3266	1			T3	3		T4	4		T5	6
valid_sources[0x49]	2927	1			T1	1		T3	4		T4	2
valid_sources[0x4a]	4060	1			T3	7		T4	2		T5	6
valid_sources[0x4b]	3095	1			T3	4		T4	3		T5	10
valid_sources[0x4c]	3085	1			T3	4		T4	4		T5	11
valid_sources[0x4d]	2546	1			T1	2		T4	4		T5	9
valid_sources[0x4e]	4260	1			T3	2		T4	3		T5	4
valid_sources[0x4f]	3866	1			T3	7		T4	1		T5	16
valid_sources[0x50]	4287	1			T1	1		T3	1		T4	2
valid_sources[0x51]	3219	1			T3	3		T4	3		T5	19
valid_sources[0x52]	2434	1			T3	7		T4	1		T5	13
valid_sources[0x53]	2853	1			T3	5		T4	2		T5	12
valid_sources[0x54]	3122	1			T3	2		T4	5		T5	1
valid_sources[0x55]	6674	1			T3	2		T4	1		T5	13
valid_sources[0x56]	3851	1			T3	1		T4	1		T5	9
valid_sources[0x57]	2711	1			T3	2		T4	7		T5	13
valid_sources[0x58]	3285	1			T3	2		T4	2		T5	4
valid_sources[0x59]	3340	1			T3	4		T4	4		T5	35
valid_sources[0x5a]	3018	1			T3	4		T4	3		T5	21
valid_sources[0x5b]	3207	1			T3	3		T4	3		T5	15
valid_sources[0x5c]	3399	1			T3	3		T4	6		T5	3
valid_sources[0x5d]	2870	1			T3	5		T4	1		T5	25
valid_sources[0x5e]	3724	1			T3	7		T4	5		T5	27
valid_sources[0x5f]	3639	1			T3	3		T4	2		T5	24
valid_sources[0x60]	3309	1			T3	4		T4	1		T5	6
valid_sources[0x61]	7239	1			T3	1		T4	7		T5	25
valid_sources[0x62]	2659	1			T3	4		T4	2		T5	5
valid_sources[0x63]	2854	1			T3	3		T4	3		T6	9
valid_sources[0x64]	3903	1			T3	3		T4	2		T5	30
valid_sources[0x65]	3652	1			T3	4		T4	1		T5	4
valid_sources[0x66]	2525	1			T3	5		T4	2		T5	10
valid_sources[0x67]	2749	1			T3	2		T4	4		T6	29
valid_sources[0x68]	2837	1			T1	1		T3	2		T4	6
valid_sources[0x69]	3434	1			T3	2		T4	3		T5	19
valid_sources[0x6a]	2642	1			T3	4		T4	4		T5	6
valid_sources[0x6b]	3109	1			T3	3		T4	3		T5	9
valid_sources[0x6c]	2771	1			T3	3		T4	1		T5	32
valid_sources[0x6d]	2882	1			T3	3		T4	3		T5	8
valid_sources[0x6e]	3328	1			T3	2		T4	7		T5	1
valid_sources[0x6f]	2421	1			T3	6		T4	1		T5	21
valid_sources[0x70]	3003	1			T3	6		T4	5		T5	38
valid_sources[0x71]	3141	1			T3	5		T4	2		T5	15
valid_sources[0x72]	3056	1			T3	5		T4	6		T5	11
valid_sources[0x73]	2862	1			T3	4		T4	1		T5	5
valid_sources[0x74]	3112	1			T3	2		T4	5		T5	15
valid_sources[0x75]	2766	1			T3	7		T4	1		T6	19
valid_sources[0x76]	3490	1			T3	7		T4	1		T6	11
valid_sources[0x77]	2610	1			T3	2		T4	2		T5	12
valid_sources[0x78]	3600	1			T3	2		T4	9		T5	12
valid_sources[0x79]	2837	1			T3	7		T4	3		T6	11
valid_sources[0x7a]	3302	1			T3	2		T4	5		T5	17
valid_sources[0x7b]	3451	1			T1	3		T3	6		T5	30
valid_sources[0x7c]	3522	1			T3	4		T4	1		T5	5
valid_sources[0x7d]	2844	1			T3	1		T4	3		T6	12
valid_sources[0x7e]	3218	1			T4	4		T5	14		T6	5
valid_sources[0x7f]	2819	1			T3	2		T4	1		T5	13
valid_sources[0x80]	4967	1			T3	3		T4	6		T5	4

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

222792

1

T1

9

T3

227

T4

214

values[0x0]

all_enables

biggest_size

73423

1

T1

3

T3

84

T4

57

values[0x1]

all_enables

biggest_size

39553

1

T1

1

T3

36

T4

33