Unified Coverage Report :: Module :: rstmgr_cascading_sva_if

Module : rstmgr_cascading_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_cascading_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_cascading_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_cascading_sva_if

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	100	1	1	100.00
ALWAYS	103	1	1	100.00
ALWAYS	107	1	1	100.00
ALWAYS	127	1	1	100.00
ALWAYS	138	1	1	100.00
ALWAYS	141	1	1	100.00
ALWAYS	144	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
100	1	1
103	1	1
107	1	1
127	1	1
138	1	1
141	1	1
144	1	1

---

Cond Coverage for Module : rstmgr_cascading_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       103
 EXPRESSION (((!scanmode)) || scan_rst_ni)
             ------1------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T11
0	1	Covered	T6,T7,T11
1	0	Covered	T7,T11,T12

 LINE       107
 EXPRESSION (por_n_i[rstmgr_pkg::DomainAonSel] && ((!scanmode)))
             ----------------1----------------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T6
1	0	Covered	T6,T7,T11
1	1	Covered	T1,T2,T3

---

Assert Coverage for Module : rstmgr_cascading_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	31	31	100.00	31	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	31	31	100.00	31	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CascadeEffAonToRstPorAboveFall_A	51464187	8583	0	0
CascadeEffAonToRstPorAboveRise_A	51464187	8583	0	0
CascadeEffAonToRstPorIoAboveFall_A	49403613	8583	0	0
CascadeEffAonToRstPorIoAboveRise_A	49403613	8583	0	0
CascadeEffAonToRstPorIoDiv2AboveFall_A	24702512	8583	0	0
CascadeEffAonToRstPorIoDiv2AboveRise_A	24702512	8583	0	0
CascadeEffAonToRstPorIoDiv4AboveFall_A	12350925	8583	0	0
CascadeEffAonToRstPorIoDiv4AboveRise_A	12350925	8583	0	0
CascadeEffAonToRstPorUcbAboveFall_A	24702601	8583	0	0
CascadeEffAonToRstPorUcbAboveRise_A	24702601	8583	0	0
CascadeLcToLcAboveFall_A	51464187	20431	0	0
CascadeLcToLcAboveRise_A	51464187	20431	0	0
CascadeLcToLcAonAboveFall_A	1558132	20431	0	0
CascadeLcToLcAonAboveRise_A	1558132	20431	0	0
CascadeLcToLcShadowedAboveFall_A	51464187	20431	0	0
CascadeLcToLcShadowedAboveRise_A	51464187	20431	0	0
CascadePorToAonAboveFall_A	1558132	7138	0	0
CascadeSysToSysAboveFall_A	51464187	20431	0	0
CascadeSysToSysAboveRise_A	51464187	20431	0	0
ScanRstToAonRise_A	1558132	193	0	0
StablePorToAonRise_A	1558132	8583	0	0
g_power_domains[0].CascadeLcToSysAboveFall_A	11061609	20431	0	0
g_power_domains[0].CascadeLcToSysAboveRise_A	11061609	20431	0	0
g_power_domains[0].CascadeLocalRstToLcAboveFall_A	11061609	20431	0	0
g_power_domains[0].CascadeLocalRstToLcAboveRise_A	11061609	20431	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A	12350925	20431	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A	12350925	20431	0	0
g_power_domains[1].CascadeLcToSysAboveFall_A	11061609	20431	0	0
g_power_domains[1].CascadeLcToSysAboveRise_A	11061609	20431	0	0
g_power_domains[1].CascadeLocalRstToLcAboveFall_A	11061609	20431	0	0
g_power_domains[1].CascadeLocalRstToLcAboveRise_A	11061609	20431	0	0

CascadeEffAonToRstPorAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51464187	8583	0	0
T1	8404	1	0	0
T2	24330	8	0	0
T3	41881	1	0	0
T4	12649	1	0	0
T5	216353	27	0	0
T6	170389	27	0	0
T7	773058	101	0	0
T8	18901	2	0	0
T9	187703	27	0	0
T10	6810	1	0	0

CascadeEffAonToRstPorAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51464187	8583	0	0
T1	8404	1	0	0
T2	24330	8	0	0
T3	41881	1	0	0
T4	12649	1	0	0
T5	216353	27	0	0
T6	170389	27	0	0
T7	773058	101	0	0
T8	18901	2	0	0
T9	187703	27	0	0
T10	6810	1	0	0

CascadeEffAonToRstPorIoAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	49403613	8583	0	0
T1	8068	1	0	0
T2	23352	8	0	0
T3	40204	1	0	0
T4	12142	1	0	0
T5	207685	27	0	0
T6	163594	27	0	0
T7	742101	101	0	0
T8	18145	2	0	0
T9	180219	27	0	0
T10	6538	1	0	0

CascadeEffAonToRstPorIoAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	49403613	8583	0	0
T1	8068	1	0	0
T2	23352	8	0	0
T3	40204	1	0	0
T4	12142	1	0	0
T5	207685	27	0	0
T6	163594	27	0	0
T7	742101	101	0	0
T8	18145	2	0	0
T9	180219	27	0	0
T10	6538	1	0	0

CascadeEffAonToRstPorIoDiv2AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24702512	8583	0	0
T1	4034	1	0	0
T2	11676	8	0	0
T3	20101	1	0	0
T4	6071	1	0	0
T5	103872	27	0	0
T6	81791	27	0	0
T7	371051	101	0	0
T8	9072	2	0	0
T9	90135	27	0	0
T10	3269	1	0	0

CascadeEffAonToRstPorIoDiv2AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24702512	8583	0	0
T1	4034	1	0	0
T2	11676	8	0	0
T3	20101	1	0	0
T4	6071	1	0	0
T5	103872	27	0	0
T6	81791	27	0	0
T7	371051	101	0	0
T8	9072	2	0	0
T9	90135	27	0	0
T10	3269	1	0	0

CascadeEffAonToRstPorIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12350925	8583	0	0
T1	2017	1	0	0
T2	5838	8	0	0
T3	10049	1	0	0
T4	3035	1	0	0
T5	51928	27	0	0
T6	40892	27	0	0
T7	185516	101	0	0
T8	4535	2	0	0
T9	45045	27	0	0
T10	1634	1	0	0

CascadeEffAonToRstPorIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12350925	8583	0	0
T1	2017	1	0	0
T2	5838	8	0	0
T3	10049	1	0	0
T4	3035	1	0	0
T5	51928	27	0	0
T6	40892	27	0	0
T7	185516	101	0	0
T8	4535	2	0	0
T9	45045	27	0	0
T10	1634	1	0	0

CascadeEffAonToRstPorUcbAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24702601	8583	0	0
T1	4033	1	0	0
T2	11678	8	0	0
T3	20102	1	0	0
T4	6070	1	0	0
T5	103843	27	0	0
T6	81800	27	0	0
T7	371052	101	0	0
T8	9072	2	0	0
T9	90129	27	0	0
T10	3268	1	0	0

CascadeEffAonToRstPorUcbAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24702601	8583	0	0
T1	4033	1	0	0
T2	11678	8	0	0
T3	20102	1	0	0
T4	6070	1	0	0
T5	103843	27	0	0
T6	81800	27	0	0
T7	371052	101	0	0
T8	9072	2	0	0
T9	90129	27	0	0
T10	3268	1	0	0

CascadeLcToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51464187	20431	0	0
T1	8404	3	0	0
T2	24330	8	0	0
T3	41881	1	0	0
T4	12649	1	0	0
T5	216353	102	0	0
T6	170389	57	0	0
T7	773058	288	0	0
T8	18901	2	0	0
T9	187703	102	0	0
T10	6810	4	0	0

CascadeLcToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51464187	20431	0	0
T1	8404	3	0	0
T2	24330	8	0	0
T3	41881	1	0	0
T4	12649	1	0	0
T5	216353	102	0	0
T6	170389	57	0	0
T7	773058	288	0	0
T8	18901	2	0	0
T9	187703	102	0	0
T10	6810	4	0	0

CascadeLcToLcAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1558132	20431	0	0
T1	251	3	0	0
T2	732	8	0	0
T3	1255	1	0	0
T4	378	1	0	0
T5	6506	102	0	0
T6	5166	57	0	0
T7	23423	288	0	0
T8	565	2	0	0
T9	5646	102	0	0
T10	202	4	0	0

CascadeLcToLcAonAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1558132	20431	0	0
T1	251	3	0	0
T2	732	8	0	0
T3	1255	1	0	0
T4	378	1	0	0
T5	6506	102	0	0
T6	5166	57	0	0
T7	23423	288	0	0
T8	565	2	0	0
T9	5646	102	0	0
T10	202	4	0	0

CascadeLcToLcShadowedAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51464187	20431	0	0
T1	8404	3	0	0
T2	24330	8	0	0
T3	41881	1	0	0
T4	12649	1	0	0
T5	216353	102	0	0
T6	170389	57	0	0
T7	773058	288	0	0
T8	18901	2	0	0
T9	187703	102	0	0
T10	6810	4	0	0

CascadeLcToLcShadowedAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51464187	20431	0	0
T1	8404	3	0	0
T2	24330	8	0	0
T3	41881	1	0	0
T4	12649	1	0	0
T5	216353	102	0	0
T6	170389	57	0	0
T7	773058	288	0	0
T8	18901	2	0	0
T9	187703	102	0	0
T10	6810	4	0	0

CascadePorToAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1558132	7138	0	0
T1	251	1	0	0
T2	732	8	0	0
T3	1255	1	0	0
T4	378	1	0	0
T5	6506	27	0	0
T6	5166	16	0	0
T7	23423	60	0	0
T8	565	16	0	0
T9	5646	27	0	0
T10	202	1	0	0

CascadeSysToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51464187	20431	0	0
T1	8404	3	0	0
T2	24330	8	0	0
T3	41881	1	0	0
T4	12649	1	0	0
T5	216353	102	0	0
T6	170389	57	0	0
T7	773058	288	0	0
T8	18901	2	0	0
T9	187703	102	0	0
T10	6810	4	0	0

CascadeSysToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51464187	20431	0	0
T1	8404	3	0	0
T2	24330	8	0	0
T3	41881	1	0	0
T4	12649	1	0	0
T5	216353	102	0	0
T6	170389	57	0	0
T7	773058	288	0	0
T8	18901	2	0	0
T9	187703	102	0	0
T10	6810	4	0	0

ScanRstToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1558132	193	0	0
T6	5166	7	0	0
T7	23423	1	0	0
T8	565	0	0	0
T9	5646	0	0	0
T10	202	0	0	0
T11	4590	0	0	0
T12	16871	1	0	0
T13	439	1	0	0
T14	729	0	0	0
T24	198	0	0	0
T25	0	1	0	0
T74	0	1	0	0
T91	0	1	0	0
T92	0	4	0	0
T93	0	1	0	0
T95	0	3	0	0

StablePorToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1558132	8583	0	0
T1	251	1	0	0
T2	732	8	0	0
T3	1255	1	0	0
T4	378	1	0	0
T5	6506	27	0	0
T6	5166	27	0	0
T7	23423	101	0	0
T8	565	2	0	0
T9	5646	27	0	0
T10	202	1	0	0

g_power_domains[0].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11061609	20431	0	0
T1	1823	3	0	0
T2	5294	8	0	0
T3	9984	1	0	0
T4	3016	1	0	0
T5	49061	102	0	0
T6	35597	57	0	0
T7	159380	288	0	0
T8	4349	2	0	0
T9	41946	102	0	0
T10	1403	4	0	0

g_power_domains[0].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11061609	20431	0	0
T1	1823	3	0	0
T2	5294	8	0	0
T3	9984	1	0	0
T4	3016	1	0	0
T5	49061	102	0	0
T6	35597	57	0	0
T7	159380	288	0	0
T8	4349	2	0	0
T9	41946	102	0	0
T10	1403	4	0	0

g_power_domains[0].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11061609	20431	0	0
T1	1823	3	0	0
T2	5294	8	0	0
T3	9984	1	0	0
T4	3016	1	0	0
T5	49061	102	0	0
T6	35597	57	0	0
T7	159380	288	0	0
T8	4349	2	0	0
T9	41946	102	0	0
T10	1403	4	0	0

g_power_domains[0].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11061609	20431	0	0
T1	1823	3	0	0
T2	5294	8	0	0
T3	9984	1	0	0
T4	3016	1	0	0
T5	49061	102	0	0
T6	35597	57	0	0
T7	159380	288	0	0
T8	4349	2	0	0
T9	41946	102	0	0
T10	1403	4	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12350925	20431	0	0
T1	2017	3	0	0
T2	5838	8	0	0
T3	10049	1	0	0
T4	3035	1	0	0
T5	51928	102	0	0
T6	40892	57	0	0
T7	185516	288	0	0
T8	4535	2	0	0
T9	45045	102	0	0
T10	1634	4	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12350925	20431	0	0
T1	2017	3	0	0
T2	5838	8	0	0
T3	10049	1	0	0
T4	3035	1	0	0
T5	51928	102	0	0
T6	40892	57	0	0
T7	185516	288	0	0
T8	4535	2	0	0
T9	45045	102	0	0
T10	1634	4	0	0

g_power_domains[1].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11061609	20431	0	0
T1	1823	3	0	0
T2	5294	8	0	0
T3	9984	1	0	0
T4	3016	1	0	0
T5	49061	102	0	0
T6	35597	57	0	0
T7	159380	288	0	0
T8	4349	2	0	0
T9	41946	102	0	0
T10	1403	4	0	0

g_power_domains[1].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11061609	20431	0	0
T1	1823	3	0	0
T2	5294	8	0	0
T3	9984	1	0	0
T4	3016	1	0	0
T5	49061	102	0	0
T6	35597	57	0	0
T7	159380	288	0	0
T8	4349	2	0	0
T9	41946	102	0	0
T10	1403	4	0	0

g_power_domains[1].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11061609	20431	0	0
T1	1823	3	0	0
T2	5294	8	0	0
T3	9984	1	0	0
T4	3016	1	0	0
T5	49061	102	0	0
T6	35597	57	0	0
T7	159380	288	0	0
T8	4349	2	0	0
T9	41946	102	0	0
T10	1403	4	0	0

g_power_domains[1].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11061609	20431	0	0
T1	1823	3	0	0
T2	5294	8	0	0
T3	9984	1	0	0
T4	3016	1	0	0
T5	49061	102	0	0
T6	35597	57	0	0
T7	159380	288	0	0
T8	4349	2	0	0
T9	41946	102	0	0
T10	1403	4	0	0