Unified Coverage Report :: Module :: rstmgr_sw_rst_sva_if

Module : rstmgr_sw_rst_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_sw_rst_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_sw_rst_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_sw_rst_sva_if

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
21	8	8

---

Cond Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Covered	Percent
Conditions	24	24	100.00
Logical	24	24	100.00
Non-Logical	0	0
Event	0	0

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[0])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T4,T10
1	0	Covered	T1,T2,T5

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[1])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T4,T12
1	0	Covered	T1,T2,T5

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[2])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T4,T46
1	0	Covered	T1,T2,T5

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[3])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T4,T73
1	0	Covered	T1,T2,T5

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[4])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T4,T46
1	0	Covered	T1,T2,T5

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[5])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T4,T46
1	0	Covered	T1,T2,T5

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[6])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T4,T12
1	0	Covered	T1,T2,T5

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[7])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T4,T12
1	0	Covered	T1,T2,T5

---

Assert Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions[0].RstEnOff_A	12350925	12674	0	0
gen_assertions[0].RstEnOn_A	12350925	1007	0	0
gen_assertions[0].RstNOff_A	12350925	12674	0	0
gen_assertions[0].RstNOn_A	12350925	1007	0	0
gen_assertions[1].RstEnOff_A	49403613	11511	0	0
gen_assertions[1].RstEnOn_A	49403613	969	0	0
gen_assertions[1].RstNOff_A	49403613	11511	0	0
gen_assertions[1].RstNOn_A	49403613	969	0	0
gen_assertions[2].RstEnOff_A	24702512	11529	0	0
gen_assertions[2].RstEnOn_A	24702512	945	0	0
gen_assertions[2].RstNOff_A	24702512	11529	0	0
gen_assertions[2].RstNOn_A	24702512	945	0	0
gen_assertions[3].RstEnOff_A	24702601	11593	0	0
gen_assertions[3].RstEnOn_A	24702601	996	0	0
gen_assertions[3].RstNOff_A	24702601	11593	0	0
gen_assertions[3].RstNOn_A	24702601	996	0	0
gen_assertions[4].RstEnOff_A	1558132	20217	0	0
gen_assertions[4].RstEnOn_A	1558132	1073	0	0
gen_assertions[4].RstNOff_A	1558132	20217	0	0
gen_assertions[4].RstNOn_A	1558132	1073	0	0
gen_assertions[5].RstEnOff_A	12350925	12900	0	0
gen_assertions[5].RstEnOn_A	12350925	1093	0	0
gen_assertions[5].RstNOff_A	12350925	12900	0	0
gen_assertions[5].RstNOn_A	12350925	1093	0	0
gen_assertions[6].RstEnOff_A	12350925	12976	0	0
gen_assertions[6].RstEnOn_A	12350925	1168	0	0
gen_assertions[6].RstNOff_A	12350925	12976	0	0
gen_assertions[6].RstNOn_A	12350925	1168	0	0
gen_assertions[7].RstEnOff_A	12350925	13016	0	0
gen_assertions[7].RstEnOn_A	12350925	1213	0	0
gen_assertions[7].RstNOff_A	12350925	13016	0	0
gen_assertions[7].RstNOn_A	12350925	1213	0	0

gen_assertions[0].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12350925	12674	0	0
T1	2017	2	0	0
T2	5838	0	0	0
T3	10049	4	0	0
T4	3035	2	0	0
T5	51928	75	0	0
T6	40892	30	0	0
T7	185516	187	0	0
T8	4535	0	0	0
T9	45045	75	0	0
T10	1634	3	0	0
T11	0	30	0	0
T12	0	110	0	0

gen_assertions[0].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12350925	1007	0	0
T3	10049	4	0	0
T4	3035	2	0	0
T5	51928	0	0	0
T6	40892	0	0	0
T7	185516	0	0	0
T8	4535	0	0	0
T9	45045	0	0	0
T10	1634	2	0	0
T11	36368	0	0	0
T24	1599	0	0	0
T46	0	6	0	0
T73	0	1	0	0
T75	0	1	0	0
T76	0	5	0	0
T77	0	1	0	0
T78	0	1	0	0
T79	0	3	0	0

gen_assertions[0].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12350925	12674	0	0
T1	2017	2	0	0
T2	5838	0	0	0
T3	10049	4	0	0
T4	3035	2	0	0
T5	51928	75	0	0
T6	40892	30	0	0
T7	185516	187	0	0
T8	4535	0	0	0
T9	45045	75	0	0
T10	1634	3	0	0
T11	0	30	0	0
T12	0	110	0	0

gen_assertions[0].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12350925	1007	0	0
T3	10049	4	0	0
T4	3035	2	0	0
T5	51928	0	0	0
T6	40892	0	0	0
T7	185516	0	0	0
T8	4535	0	0	0
T9	45045	0	0	0
T10	1634	2	0	0
T11	36368	0	0	0
T24	1599	0	0	0
T46	0	6	0	0
T73	0	1	0	0
T75	0	1	0	0
T76	0	5	0	0
T77	0	1	0	0
T78	0	1	0	0
T79	0	3	0	0

gen_assertions[1].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	49403613	11511	0	0
T1	8068	2	0	0
T2	23352	0	0	0
T3	40204	2	0	0
T4	12142	4	0	0
T5	207685	72	0	0
T6	163594	29	0	0
T7	742101	163	0	0
T8	18145	0	0	0
T9	180219	68	0	0
T10	6538	2	0	0
T11	0	25	0	0
T12	0	96	0	0

gen_assertions[1].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	49403613	969	0	0
T3	40204	2	0	0
T4	12142	4	0	0
T5	207685	0	0	0
T6	163594	0	0	0
T7	742101	0	0	0
T8	18145	0	0	0
T9	180219	0	0	0
T10	6538	0	0	0
T11	145485	0	0	0
T12	0	1	0	0
T24	6400	0	0	0
T45	0	1	0	0
T46	0	7	0	0
T76	0	6	0	0
T78	0	3	0	0
T79	0	5	0	0
T80	0	5	0	0
T81	0	7	0	0

gen_assertions[1].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	49403613	11511	0	0
T1	8068	2	0	0
T2	23352	0	0	0
T3	40204	2	0	0
T4	12142	4	0	0
T5	207685	72	0	0
T6	163594	29	0	0
T7	742101	163	0	0
T8	18145	0	0	0
T9	180219	68	0	0
T10	6538	2	0	0
T11	0	25	0	0
T12	0	96	0	0

gen_assertions[1].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	49403613	969	0	0
T3	40204	2	0	0
T4	12142	4	0	0
T5	207685	0	0	0
T6	163594	0	0	0
T7	742101	0	0	0
T8	18145	0	0	0
T9	180219	0	0	0
T10	6538	0	0	0
T11	145485	0	0	0
T12	0	1	0	0
T24	6400	0	0	0
T45	0	1	0	0
T46	0	7	0	0
T76	0	6	0	0
T78	0	3	0	0
T79	0	5	0	0
T80	0	5	0	0
T81	0	7	0	0

gen_assertions[2].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24702512	11529	0	0
T1	4034	2	0	0
T2	11676	0	0	0
T3	20101	5	0	0
T4	6071	4	0	0
T5	103872	72	0	0
T6	81791	29	0	0
T7	371051	163	0	0
T8	9072	0	0	0
T9	90135	68	0	0
T10	3269	2	0	0
T11	0	25	0	0
T12	0	95	0	0

gen_assertions[2].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24702512	945	0	0
T3	20101	5	0	0
T4	6071	4	0	0
T5	103872	0	0	0
T6	81791	0	0	0
T7	371051	0	0	0
T8	9072	0	0	0
T9	90135	0	0	0
T10	3269	0	0	0
T11	72752	0	0	0
T24	3200	0	0	0
T46	0	8	0	0
T76	0	8	0	0
T78	0	4	0	0
T79	0	6	0	0
T80	0	8	0	0
T81	0	7	0	0
T82	0	2	0	0
T83	0	1	0	0

gen_assertions[2].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24702512	11529	0	0
T1	4034	2	0	0
T2	11676	0	0	0
T3	20101	5	0	0
T4	6071	4	0	0
T5	103872	72	0	0
T6	81791	29	0	0
T7	371051	163	0	0
T8	9072	0	0	0
T9	90135	68	0	0
T10	3269	2	0	0
T11	0	25	0	0
T12	0	95	0	0

gen_assertions[2].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24702512	945	0	0
T3	20101	5	0	0
T4	6071	4	0	0
T5	103872	0	0	0
T6	81791	0	0	0
T7	371051	0	0	0
T8	9072	0	0	0
T9	90135	0	0	0
T10	3269	0	0	0
T11	72752	0	0	0
T24	3200	0	0	0
T46	0	8	0	0
T76	0	8	0	0
T78	0	4	0	0
T79	0	6	0	0
T80	0	8	0	0
T81	0	7	0	0
T82	0	2	0	0
T83	0	1	0	0

gen_assertions[3].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24702601	11593	0	0
T1	4033	2	0	0
T2	11678	0	0	0
T3	20102	7	0	0
T4	6070	6	0	0
T5	103843	72	0	0
T6	81800	29	0	0
T7	371052	163	0	0
T8	9072	0	0	0
T9	90129	68	0	0
T10	3268	2	0	0
T11	0	25	0	0
T12	0	95	0	0

gen_assertions[3].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24702601	996	0	0
T3	20102	7	0	0
T4	6070	6	0	0
T5	103843	0	0	0
T6	81800	0	0	0
T7	371052	0	0	0
T8	9072	0	0	0
T9	90129	0	0	0
T10	3268	0	0	0
T11	72729	0	0	0
T24	3200	0	0	0
T46	0	8	0	0
T73	0	1	0	0
T76	0	8	0	0
T78	0	5	0	0
T79	0	5	0	0
T80	0	7	0	0
T81	0	8	0	0
T84	0	10	0	0

gen_assertions[3].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24702601	11593	0	0
T1	4033	2	0	0
T2	11678	0	0	0
T3	20102	7	0	0
T4	6070	6	0	0
T5	103843	72	0	0
T6	81800	29	0	0
T7	371052	163	0	0
T8	9072	0	0	0
T9	90129	68	0	0
T10	3268	2	0	0
T11	0	25	0	0
T12	0	95	0	0

gen_assertions[3].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24702601	996	0	0
T3	20102	7	0	0
T4	6070	6	0	0
T5	103843	0	0	0
T6	81800	0	0	0
T7	371052	0	0	0
T8	9072	0	0	0
T9	90129	0	0	0
T10	3268	0	0	0
T11	72729	0	0	0
T24	3200	0	0	0
T46	0	8	0	0
T73	0	1	0	0
T76	0	8	0	0
T78	0	5	0	0
T79	0	5	0	0
T80	0	7	0	0
T81	0	8	0	0
T84	0	10	0	0

gen_assertions[4].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1558132	20217	0	0
T1	251	3	0	0
T2	732	2	0	0
T3	1255	8	0	0
T4	378	8	0	0
T5	6506	97	0	0
T6	5166	57	0	0
T7	23423	284	0	0
T8	565	2	0	0
T9	5646	90	0	0
T10	202	4	0	0

gen_assertions[4].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1558132	1073	0	0
T3	1255	7	0	0
T4	378	7	0	0
T5	6506	0	0	0
T6	5166	0	0	0
T7	23423	0	0	0
T8	565	0	0	0
T9	5646	0	0	0
T10	202	0	0	0
T11	4590	0	0	0
T24	198	0	0	0
T46	0	9	0	0
T76	0	9	0	0
T77	0	1	0	0
T78	0	6	0	0
T79	0	3	0	0
T80	0	7	0	0
T81	0	11	0	0
T85	0	1	0	0

gen_assertions[4].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1558132	20217	0	0
T1	251	3	0	0
T2	732	2	0	0
T3	1255	8	0	0
T4	378	8	0	0
T5	6506	97	0	0
T6	5166	57	0	0
T7	23423	284	0	0
T8	565	2	0	0
T9	5646	90	0	0
T10	202	4	0	0

gen_assertions[4].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1558132	1073	0	0
T3	1255	7	0	0
T4	378	7	0	0
T5	6506	0	0	0
T6	5166	0	0	0
T7	23423	0	0	0
T8	565	0	0	0
T9	5646	0	0	0
T10	202	0	0	0
T11	4590	0	0	0
T24	198	0	0	0
T46	0	9	0	0
T76	0	9	0	0
T77	0	1	0	0
T78	0	6	0	0
T79	0	3	0	0
T80	0	7	0	0
T81	0	11	0	0
T85	0	1	0	0

gen_assertions[5].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12350925	12900	0	0
T1	2017	2	0	0
T2	5838	0	0	0
T3	10049	8	0	0
T4	3035	6	0	0
T5	51928	75	0	0
T6	40892	30	0	0
T7	185516	187	0	0
T8	4535	0	0	0
T9	45045	75	0	0
T10	1634	3	0	0
T11	0	30	0	0
T12	0	110	0	0

gen_assertions[5].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12350925	1093	0	0
T3	10049	8	0	0
T4	3035	6	0	0
T5	51928	0	0	0
T6	40892	0	0	0
T7	185516	0	0	0
T8	4535	0	0	0
T9	45045	0	0	0
T10	1634	0	0	0
T11	36368	0	0	0
T24	1599	0	0	0
T46	0	13	0	0
T76	0	9	0	0
T77	0	1	0	0
T78	0	7	0	0
T79	0	2	0	0
T80	0	8	0	0
T81	0	9	0	0
T85	0	1	0	0

gen_assertions[5].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12350925	12900	0	0
T1	2017	2	0	0
T2	5838	0	0	0
T3	10049	8	0	0
T4	3035	6	0	0
T5	51928	75	0	0
T6	40892	30	0	0
T7	185516	187	0	0
T8	4535	0	0	0
T9	45045	75	0	0
T10	1634	3	0	0
T11	0	30	0	0
T12	0	110	0	0

gen_assertions[5].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12350925	1093	0	0
T3	10049	8	0	0
T4	3035	6	0	0
T5	51928	0	0	0
T6	40892	0	0	0
T7	185516	0	0	0
T8	4535	0	0	0
T9	45045	0	0	0
T10	1634	0	0	0
T11	36368	0	0	0
T24	1599	0	0	0
T46	0	13	0	0
T76	0	9	0	0
T77	0	1	0	0
T78	0	7	0	0
T79	0	2	0	0
T80	0	8	0	0
T81	0	9	0	0
T85	0	1	0	0

gen_assertions[6].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12350925	12976	0	0
T1	2017	2	0	0
T2	5838	0	0	0
T3	10049	10	0	0
T4	3035	8	0	0
T5	51928	75	0	0
T6	40892	30	0	0
T7	185516	187	0	0
T8	4535	0	0	0
T9	45045	75	0	0
T10	1634	3	0	0
T11	0	30	0	0
T12	0	111	0	0

gen_assertions[6].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12350925	1168	0	0
T3	10049	10	0	0
T4	3035	8	0	0
T5	51928	0	0	0
T6	40892	0	0	0
T7	185516	0	0	0
T8	4535	0	0	0
T9	45045	0	0	0
T10	1634	0	0	0
T11	36368	0	0	0
T12	0	1	0	0
T24	1599	0	0	0
T46	0	12	0	0
T76	0	10	0	0
T78	0	8	0	0
T79	0	4	0	0
T80	0	11	0	0
T81	0	10	0	0
T83	0	1	0	0

gen_assertions[6].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12350925	12976	0	0
T1	2017	2	0	0
T2	5838	0	0	0
T3	10049	10	0	0
T4	3035	8	0	0
T5	51928	75	0	0
T6	40892	30	0	0
T7	185516	187	0	0
T8	4535	0	0	0
T9	45045	75	0	0
T10	1634	3	0	0
T11	0	30	0	0
T12	0	111	0	0

gen_assertions[6].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12350925	1168	0	0
T3	10049	10	0	0
T4	3035	8	0	0
T5	51928	0	0	0
T6	40892	0	0	0
T7	185516	0	0	0
T8	4535	0	0	0
T9	45045	0	0	0
T10	1634	0	0	0
T11	36368	0	0	0
T12	0	1	0	0
T24	1599	0	0	0
T46	0	12	0	0
T76	0	10	0	0
T78	0	8	0	0
T79	0	4	0	0
T80	0	11	0	0
T81	0	10	0	0
T83	0	1	0	0

gen_assertions[7].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12350925	13016	0	0
T1	2017	2	0	0
T2	5838	0	0	0
T3	10049	10	0	0
T4	3035	11	0	0
T5	51928	75	0	0
T6	40892	30	0	0
T7	185516	187	0	0
T8	4535	0	0	0
T9	45045	75	0	0
T10	1634	3	0	0
T11	0	30	0	0
T12	0	111	0	0

gen_assertions[7].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12350925	1213	0	0
T3	10049	10	0	0
T4	3035	11	0	0
T5	51928	0	0	0
T6	40892	0	0	0
T7	185516	0	0	0
T8	4535	0	0	0
T9	45045	0	0	0
T10	1634	0	0	0
T11	36368	0	0	0
T12	0	1	0	0
T24	1599	0	0	0
T46	0	13	0	0
T73	0	1	0	0
T76	0	11	0	0
T78	0	9	0	0
T79	0	4	0	0
T80	0	13	0	0
T81	0	13	0	0

gen_assertions[7].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12350925	13016	0	0
T1	2017	2	0	0
T2	5838	0	0	0
T3	10049	10	0	0
T4	3035	11	0	0
T5	51928	75	0	0
T6	40892	30	0	0
T7	185516	187	0	0
T8	4535	0	0	0
T9	45045	75	0	0
T10	1634	3	0	0
T11	0	30	0	0
T12	0	111	0	0

gen_assertions[7].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12350925	1213	0	0
T3	10049	10	0	0
T4	3035	11	0	0
T5	51928	0	0	0
T6	40892	0	0	0
T7	185516	0	0	0
T8	4535	0	0	0
T9	45045	0	0	0
T10	1634	0	0	0
T11	36368	0	0	0
T12	0	1	0	0
T24	1599	0	0	0
T46	0	13	0	0
T73	0	1	0	0
T76	0	11	0	0
T78	0	9	0	0
T79	0	4	0	0
T80	0	13	0	0
T81	0	13	0	0