Unified Coverage Report :: Module :: rstmgr_csr_assert_fpv

Module : rstmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rstmgr_csr_assert_0/rstmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rstmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rstmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	19	19	100.00	19	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	19	19	100.00	19	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	11824929	7451	0	0
alert_regwen_rd_A	11824929	3736	0	0
cpu_regwen_rd_A	11824929	3710	0	0
sw_rst_ctrl_n_0_rd_A	11824929	7768	0	0
sw_rst_ctrl_n_1_rd_A	11824929	7649	0	0
sw_rst_ctrl_n_2_rd_A	11824929	7500	0	0
sw_rst_ctrl_n_3_rd_A	11824929	7576	0	0
sw_rst_ctrl_n_4_rd_A	11824929	7565	0	0
sw_rst_ctrl_n_5_rd_A	11824929	7653	0	0
sw_rst_ctrl_n_6_rd_A	11824929	7731	0	0
sw_rst_ctrl_n_7_rd_A	11824929	7814	0	0
sw_rst_regwen_0_rd_A	11824929	4005	0	0
sw_rst_regwen_1_rd_A	11824929	4316	0	0
sw_rst_regwen_2_rd_A	11824929	4132	0	0
sw_rst_regwen_3_rd_A	11824929	4083	0	0
sw_rst_regwen_4_rd_A	11824929	4204	0	0
sw_rst_regwen_5_rd_A	11824929	4096	0	0
sw_rst_regwen_6_rd_A	11824929	4023	0	0
sw_rst_regwen_7_rd_A	11824929	4020	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11824929	7451	0	0
T52	21086	3	0	0
T53	11536	2	0	0
T54	3805	265	0	0
T55	2914	9	0	0
T56	1891	27	0	0
T57	22748	1	0	0
T86	23775	3	0	0
T87	2531	268	0	0
T88	3370	26	0	0
T89	2698	69	0	0

alert_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11824929	3736	0	0
T12	119712	210	0	0
T13	3140	0	0	0
T15	2880	0	0	0
T25	23885	0	0	0
T26	34899	0	0	0
T27	26109	0	0	0
T45	4362	0	0	0
T73	2743	0	0	0
T93	0	57	0	0
T96	5080	0	0	0
T97	5481	0	0	0
T100	0	367	0	0
T102	0	191	0	0
T125	0	73	0	0
T126	0	26	0	0
T127	0	24	0	0
T128	0	65	0	0
T129	0	211	0	0
T130	0	25	0	0

cpu_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11824929	3710	0	0
T12	119712	152	0	0
T13	3140	0	0	0
T15	2880	0	0	0
T25	23885	0	0	0
T26	34899	0	0	0
T27	26109	0	0	0
T45	4362	0	0	0
T73	2743	0	0	0
T93	0	44	0	0
T96	5080	0	0	0
T97	5481	0	0	0
T100	0	382	0	0
T102	0	162	0	0
T125	0	50	0	0
T126	0	39	0	0
T127	0	45	0	0
T128	0	71	0	0
T129	0	241	0	0
T130	0	50	0	0

sw_rst_ctrl_n_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11824929	7768	0	0
T1	1823	7	0	0
T2	5294	0	0	0
T3	9984	167	0	0
T4	3016	0	0	0
T5	49061	0	0	0
T6	35597	0	0	0
T7	159380	0	0	0
T8	4349	0	0	0
T9	41946	0	0	0
T10	1403	0	0	0
T12	0	167	0	0
T83	0	10	0	0
T93	0	49	0	0
T131	0	16	0	0
T132	0	49	0	0
T133	0	37	0	0
T134	0	8	0	0
T135	0	40	0	0

sw_rst_ctrl_n_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11824929	7649	0	0
T1	1823	2	0	0
T2	5294	0	0	0
T3	9984	171	0	0
T4	3016	0	0	0
T5	49061	0	0	0
T6	35597	0	0	0
T7	159380	0	0	0
T8	4349	0	0	0
T9	41946	0	0	0
T10	1403	0	0	0
T12	0	150	0	0
T83	0	10	0	0
T93	0	41	0	0
T131	0	11	0	0
T132	0	42	0	0
T133	0	41	0	0
T134	0	8	0	0
T135	0	43	0	0

sw_rst_ctrl_n_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11824929	7500	0	0
T1	1823	6	0	0
T2	5294	0	0	0
T3	9984	151	0	0
T4	3016	0	0	0
T5	49061	0	0	0
T6	35597	0	0	0
T7	159380	0	0	0
T8	4349	0	0	0
T9	41946	0	0	0
T10	1403	0	0	0
T12	0	176	0	0
T83	0	14	0	0
T93	0	52	0	0
T131	0	22	0	0
T132	0	55	0	0
T133	0	32	0	0
T134	0	5	0	0
T135	0	58	0	0

sw_rst_ctrl_n_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11824929	7576	0	0
T1	1823	3	0	0
T2	5294	0	0	0
T3	9984	211	0	0
T4	3016	0	0	0
T5	49061	0	0	0
T6	35597	0	0	0
T7	159380	0	0	0
T8	4349	0	0	0
T9	41946	0	0	0
T10	1403	0	0	0
T12	0	186	0	0
T83	0	12	0	0
T93	0	46	0	0
T131	0	12	0	0
T132	0	40	0	0
T133	0	28	0	0
T134	0	13	0	0
T135	0	65	0	0

sw_rst_ctrl_n_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11824929	7565	0	0
T1	1823	9	0	0
T2	5294	0	0	0
T3	9984	137	0	0
T4	3016	0	0	0
T5	49061	0	0	0
T6	35597	0	0	0
T7	159380	0	0	0
T8	4349	0	0	0
T9	41946	0	0	0
T10	1403	0	0	0
T12	0	173	0	0
T83	0	13	0	0
T93	0	38	0	0
T131	0	8	0	0
T132	0	29	0	0
T133	0	55	0	0
T134	0	7	0	0
T135	0	37	0	0

sw_rst_ctrl_n_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11824929	7653	0	0
T1	1823	8	0	0
T2	5294	0	0	0
T3	9984	146	0	0
T4	3016	0	0	0
T5	49061	0	0	0
T6	35597	0	0	0
T7	159380	0	0	0
T8	4349	0	0	0
T9	41946	0	0	0
T10	1403	0	0	0
T12	0	182	0	0
T83	0	11	0	0
T93	0	51	0	0
T131	0	11	0	0
T132	0	51	0	0
T133	0	26	0	0
T134	0	11	0	0
T135	0	62	0	0

sw_rst_ctrl_n_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11824929	7731	0	0
T1	1823	14	0	0
T2	5294	0	0	0
T3	9984	139	0	0
T4	3016	0	0	0
T5	49061	0	0	0
T6	35597	0	0	0
T7	159380	0	0	0
T8	4349	0	0	0
T9	41946	0	0	0
T10	1403	0	0	0
T12	0	188	0	0
T83	0	18	0	0
T93	0	55	0	0
T131	0	29	0	0
T132	0	41	0	0
T133	0	33	0	0
T134	0	3	0	0
T135	0	75	0	0

sw_rst_ctrl_n_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11824929	7814	0	0
T1	1823	15	0	0
T2	5294	0	0	0
T3	9984	149	0	0
T4	3016	0	0	0
T5	49061	0	0	0
T6	35597	0	0	0
T7	159380	0	0	0
T8	4349	0	0	0
T9	41946	0	0	0
T10	1403	0	0	0
T12	0	215	0	0
T83	0	16	0	0
T93	0	54	0	0
T131	0	18	0	0
T132	0	42	0	0
T133	0	17	0	0
T134	0	5	0	0
T135	0	67	0	0

sw_rst_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11824929	4005	0	0
T3	9984	25	0	0
T4	3016	0	0	0
T5	49061	0	0	0
T6	35597	0	0	0
T7	159380	0	0	0
T8	4349	0	0	0
T9	41946	0	0	0
T10	1403	0	0	0
T11	32148	0	0	0
T12	0	173	0	0
T24	1581	0	0	0
T83	0	1	0	0
T93	0	47	0	0
T100	0	361	0	0
T102	0	200	0	0
T131	0	7	0	0
T134	0	8	0	0
T136	0	6	0	0
T137	0	3	0	0

sw_rst_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11824929	4316	0	0
T3	9984	36	0	0
T4	3016	0	0	0
T5	49061	0	0	0
T6	35597	0	0	0
T7	159380	0	0	0
T8	4349	0	0	0
T9	41946	0	0	0
T10	1403	0	0	0
T11	32148	0	0	0
T12	0	155	0	0
T24	1581	0	0	0
T83	0	9	0	0
T93	0	31	0	0
T100	0	335	0	0
T102	0	168	0	0
T131	0	17	0	0
T134	0	13	0	0
T136	0	5	0	0
T137	0	5	0	0

sw_rst_regwen_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11824929	4132	0	0
T3	9984	38	0	0
T4	3016	0	0	0
T5	49061	0	0	0
T6	35597	0	0	0
T7	159380	0	0	0
T8	4349	0	0	0
T9	41946	0	0	0
T10	1403	0	0	0
T11	32148	0	0	0
T12	0	175	0	0
T24	1581	0	0	0
T83	0	15	0	0
T93	0	81	0	0
T100	0	362	0	0
T102	0	185	0	0
T131	0	7	0	0
T134	0	3	0	0
T136	0	7	0	0
T137	0	3	0	0

sw_rst_regwen_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11824929	4083	0	0
T3	9984	44	0	0
T4	3016	0	0	0
T5	49061	0	0	0
T6	35597	0	0	0
T7	159380	0	0	0
T8	4349	0	0	0
T9	41946	0	0	0
T10	1403	0	0	0
T11	32148	0	0	0
T12	0	174	0	0
T24	1581	0	0	0
T83	0	5	0	0
T93	0	57	0	0
T100	0	373	0	0
T102	0	163	0	0
T131	0	8	0	0
T134	0	5	0	0
T136	0	10	0	0
T137	0	8	0	0

sw_rst_regwen_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11824929	4204	0	0
T3	9984	39	0	0
T4	3016	0	0	0
T5	49061	0	0	0
T6	35597	0	0	0
T7	159380	0	0	0
T8	4349	0	0	0
T9	41946	0	0	0
T10	1403	0	0	0
T11	32148	0	0	0
T12	0	200	0	0
T24	1581	0	0	0
T83	0	4	0	0
T93	0	63	0	0
T100	0	365	0	0
T102	0	129	0	0
T131	0	8	0	0
T134	0	5	0	0
T136	0	10	0	0
T137	0	8	0	0

sw_rst_regwen_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11824929	4096	0	0
T3	9984	28	0	0
T4	3016	0	0	0
T5	49061	0	0	0
T6	35597	0	0	0
T7	159380	0	0	0
T8	4349	0	0	0
T9	41946	0	0	0
T10	1403	0	0	0
T11	32148	0	0	0
T12	0	167	0	0
T24	1581	0	0	0
T83	0	11	0	0
T93	0	52	0	0
T100	0	374	0	0
T102	0	187	0	0
T131	0	3	0	0
T134	0	1	0	0
T136	0	7	0	0
T137	0	15	0	0

sw_rst_regwen_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11824929	4023	0	0
T3	9984	43	0	0
T4	3016	0	0	0
T5	49061	0	0	0
T6	35597	0	0	0
T7	159380	0	0	0
T8	4349	0	0	0
T9	41946	0	0	0
T10	1403	0	0	0
T11	32148	0	0	0
T12	0	154	0	0
T24	1581	0	0	0
T83	0	8	0	0
T93	0	51	0	0
T100	0	364	0	0
T102	0	168	0	0
T131	0	3	0	0
T134	0	9	0	0
T136	0	16	0	0
T137	0	6	0	0

sw_rst_regwen_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11824929	4020	0	0
T3	9984	34	0	0
T4	3016	0	0	0
T5	49061	0	0	0
T6	35597	0	0	0
T7	159380	0	0	0
T8	4349	0	0	0
T9	41946	0	0	0
T10	1403	0	0	0
T11	32148	0	0	0
T12	0	182	0	0
T24	1581	0	0	0
T83	0	5	0	0
T93	0	53	0	0
T100	0	331	0	0
T102	0	138	0	0
T131	0	15	0	0
T136	0	16	0	0
T137	0	6	0	0
T138	0	35	0	0