Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	596400	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

359465

1

T1

937

T3

819

T4

147

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	507953	1			T1	1418		T2	1		T3	1256
values[0x0]	223649	1			T1	539		T3	515		T4	97
values[0x1]	224263	1			T1	479		T3	483		T4	96

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	500376	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

455489

1

T1

1201

T3

1041

T4

181

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	4256	1			T5	16		T9	59		T10	5
valid_sources[0x01]	4648	1			T1	13		T5	19		T9	7
valid_sources[0x02]	2556	1			T4	4		T5	21		T9	2
valid_sources[0x03]	3590	1			T1	2		T4	11		T5	14
valid_sources[0x04]	2799	1			T5	18		T9	3		T10	17
valid_sources[0x05]	3920	1			T1	99		T5	11		T9	1
valid_sources[0x06]	4981	1			T5	7		T10	15		T11	19
valid_sources[0x07]	3347	1			T5	4		T9	20		T10	10
valid_sources[0x08]	10030	1			T5	13		T9	30		T10	11
valid_sources[0x09]	6549	1			T5	11		T9	7		T10	13
valid_sources[0x0a]	3317	1			T4	1		T5	8		T10	6
valid_sources[0x0b]	3401	1			T5	21		T9	24		T10	17
valid_sources[0x0c]	3593	1			T4	5		T5	17		T9	7
valid_sources[0x0d]	2854	1			T5	19		T9	11		T10	8
valid_sources[0x0e]	3718	1			T4	5		T5	15		T10	10
valid_sources[0x0f]	3452	1			T5	10		T9	1		T10	15
valid_sources[0x10]	2869	1			T5	18		T9	4		T10	10
valid_sources[0x11]	3679	1			T1	93		T5	13		T9	9
valid_sources[0x12]	3141	1			T4	2		T5	15		T9	13
valid_sources[0x13]	3222	1			T5	9		T9	4		T10	11
valid_sources[0x14]	3665	1			T5	10		T9	46		T10	4
valid_sources[0x15]	6367	1			T5	9		T10	14		T11	14
valid_sources[0x16]	3170	1			T3	8		T5	9		T9	3
valid_sources[0x17]	3561	1			T3	229		T4	14		T5	19
valid_sources[0x18]	3593	1			T5	9		T9	5		T10	9
valid_sources[0x19]	2716	1			T1	13		T5	2		T9	26
valid_sources[0x1a]	3191	1			T4	1		T5	9		T9	3
valid_sources[0x1b]	3865	1			T1	204		T5	12		T9	3
valid_sources[0x1c]	3723	1			T3	337		T4	6		T5	6
valid_sources[0x1d]	3298	1			T5	14		T9	18		T10	13
valid_sources[0x1e]	3285	1			T5	4		T10	10		T11	14
valid_sources[0x1f]	6000	1			T4	12		T5	5		T10	12
valid_sources[0x20]	2668	1			T5	7		T9	1		T10	14
valid_sources[0x21]	3065	1			T5	13		T10	6		T11	15
valid_sources[0x22]	2644	1			T5	12		T9	1		T10	12
valid_sources[0x23]	3244	1			T5	7		T9	20		T10	11
valid_sources[0x24]	3988	1			T4	8		T5	17		T9	2
valid_sources[0x25]	3095	1			T5	9		T9	1		T10	12
valid_sources[0x26]	3768	1			T4	12		T5	12		T9	3
valid_sources[0x27]	3395	1			T5	6		T9	27		T10	15
valid_sources[0x28]	3660	1			T5	3		T9	28		T10	9
valid_sources[0x29]	3304	1			T1	11		T5	12		T9	3
valid_sources[0x2a]	2952	1			T5	4		T9	26		T10	10
valid_sources[0x2b]	3934	1			T5	18		T9	3		T10	20
valid_sources[0x2c]	6313	1			T5	7		T9	2		T10	11
valid_sources[0x2d]	3105	1			T1	3		T5	7		T9	18
valid_sources[0x2e]	3930	1			T1	1		T5	12		T9	16
valid_sources[0x2f]	2987	1			T5	12		T9	20		T10	19
valid_sources[0x30]	3407	1			T4	7		T5	8		T9	51
valid_sources[0x31]	3627	1			T5	11		T9	2		T10	13
valid_sources[0x32]	3705	1			T5	20		T9	1		T10	14
valid_sources[0x33]	2933	1			T5	9		T10	11		T11	7
valid_sources[0x34]	3323	1			T1	6		T5	26		T9	34
valid_sources[0x35]	2713	1			T5	10		T10	12		T11	9
valid_sources[0x36]	4350	1			T5	26		T9	43		T10	6
valid_sources[0x37]	3352	1			T1	6		T3	112		T4	9
valid_sources[0x38]	3339	1			T5	8		T9	6		T10	17
valid_sources[0x39]	3774	1			T5	21		T10	13		T11	16
valid_sources[0x3a]	4282	1			T5	31		T9	6		T10	12
valid_sources[0x3b]	3321	1			T5	9		T10	14		T11	14
valid_sources[0x3c]	3282	1			T5	10		T9	18		T10	14
valid_sources[0x3d]	3611	1			T5	10		T10	17		T11	12
valid_sources[0x3e]	3111	1			T5	19		T10	6		T11	9
valid_sources[0x3f]	2934	1			T5	25		T9	9		T10	12
valid_sources[0x40]	4107	1			T5	8		T9	61		T10	10
valid_sources[0x41]	3087	1			T5	10		T10	8		T11	11
valid_sources[0x42]	2902	1			T1	3		T5	12		T9	5
valid_sources[0x43]	2653	1			T1	3		T5	8		T10	9
valid_sources[0x44]	3704	1			T3	1		T5	5		T10	7
valid_sources[0x45]	7288	1			T5	17		T9	13		T10	12
valid_sources[0x46]	3093	1			T5	14		T10	10		T11	17
valid_sources[0x47]	4165	1			T5	4		T9	12		T10	15
valid_sources[0x48]	3343	1			T5	20		T9	2		T10	11
valid_sources[0x49]	3435	1			T5	18		T9	11		T10	15
valid_sources[0x4a]	3050	1			T5	8		T9	27		T10	17
valid_sources[0x4b]	3075	1			T4	3		T5	5		T9	17
valid_sources[0x4c]	7444	1			T5	12		T9	11		T10	14
valid_sources[0x4d]	3373	1			T1	13		T5	20		T9	6
valid_sources[0x4e]	4013	1			T4	17		T5	4		T9	11
valid_sources[0x4f]	6464	1			T5	13		T9	8		T10	12
valid_sources[0x50]	3005	1			T5	23		T9	11		T10	8
valid_sources[0x51]	3888	1			T5	19		T10	18		T11	8
valid_sources[0x52]	3439	1			T5	11		T9	9		T10	10
valid_sources[0x53]	3369	1			T5	11		T9	8		T10	9
valid_sources[0x54]	2802	1			T5	10		T9	1		T10	8
valid_sources[0x55]	3705	1			T5	6		T9	15		T10	21
valid_sources[0x56]	3488	1			T1	5		T5	15		T9	18
valid_sources[0x57]	3587	1			T4	4		T5	19		T10	19
valid_sources[0x58]	2783	1			T5	21		T9	18		T10	16
valid_sources[0x59]	4878	1			T5	6		T10	18		T11	5
valid_sources[0x5a]	3286	1			T5	26		T9	24		T10	4
valid_sources[0x5b]	5265	1			T5	7		T9	7		T10	10
valid_sources[0x5c]	3994	1			T5	11		T9	31		T10	13
valid_sources[0x5d]	4780	1			T4	8		T5	4		T9	52
valid_sources[0x5e]	2802	1			T1	24		T5	3		T9	1
valid_sources[0x5f]	3640	1			T1	1		T5	17		T9	15
valid_sources[0x60]	3017	1			T1	139		T5	13		T9	7
valid_sources[0x61]	3551	1			T5	2		T9	39		T10	9
valid_sources[0x62]	3389	1			T5	30		T9	2		T10	13
valid_sources[0x63]	2813	1			T1	5		T5	16		T9	15
valid_sources[0x64]	3380	1			T1	103		T5	22		T9	16
valid_sources[0x65]	7711	1			T5	24		T9	33		T10	7
valid_sources[0x66]	3883	1			T5	18		T9	4		T10	11
valid_sources[0x67]	3410	1			T5	13		T9	3		T10	12
valid_sources[0x68]	3096	1			T4	7		T5	10		T9	6
valid_sources[0x69]	3461	1			T5	15		T9	16		T10	10
valid_sources[0x6a]	3566	1			T3	7		T5	8		T9	1
valid_sources[0x6b]	3210	1			T1	7		T5	3		T9	20
valid_sources[0x6c]	2577	1			T4	4		T5	13		T10	18
valid_sources[0x6d]	3561	1			T5	21		T9	49		T10	11
valid_sources[0x6e]	3595	1			T5	11		T9	3		T10	8
valid_sources[0x6f]	2860	1			T5	4		T9	26		T10	9
valid_sources[0x70]	6248	1			T5	15		T9	65		T10	13
valid_sources[0x71]	3596	1			T5	12		T9	25		T10	14
valid_sources[0x72]	5094	1			T5	9		T9	21		T10	15
valid_sources[0x73]	4232	1			T5	8		T9	2		T10	10
valid_sources[0x74]	3628	1			T5	6		T9	3		T10	13
valid_sources[0x75]	3247	1			T5	8		T9	21		T10	13
valid_sources[0x76]	3298	1			T1	1		T5	14		T9	11
valid_sources[0x77]	3092	1			T5	27		T10	15		T11	13
valid_sources[0x78]	3499	1			T5	7		T9	26		T10	16
valid_sources[0x79]	2968	1			T5	12		T9	37		T10	18
valid_sources[0x7a]	3176	1			T4	5		T5	16		T10	14
valid_sources[0x7b]	3924	1			T5	8		T10	18		T11	10
valid_sources[0x7c]	2935	1			T5	19		T9	33		T10	11
valid_sources[0x7d]	4309	1			T4	8		T5	7		T9	18
valid_sources[0x7e]	6389	1			T5	7		T9	15		T10	6
valid_sources[0x7f]	3940	1			T1	265		T5	18		T9	6
valid_sources[0x80]	3679	1			T5	17		T9	4		T10	16

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

238390

1

T1

669

T3

560

T4

90

values[0x0]

all_enables

biggest_size

78586

1

T1

188

T3

169

T4

39

values[0x1]

all_enables

biggest_size

42489

1

T1

80

T3

90

T4

18