Module Definition
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Module : pwrmgr_rstmgr_sva_if
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.pwrmgr_rstmgr_sva_if 100.00 100.00 100.00 100.00



Module Instance : tb.dut.pwrmgr_rstmgr_sva_if

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.55 100.00 98.21 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : pwrmgr_rstmgr_sva_if
Line No.TotalCoveredPercent
TOTAL11100.00
ALWAYS3311100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' or '../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
33 1 1


Cond Coverage for Module : pwrmgr_rstmgr_sva_if
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT1,T2,T3

Assert Coverage for Module : pwrmgr_rstmgr_sva_if
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 8 8 100.00 8 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 8 8 100.00 8 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
gen_assertions_per_power_domains[0].LcHandshakeOff_A 10779344 12671 0 0
gen_assertions_per_power_domains[0].LcHandshakeOn_A 10779344 117025 0 0
gen_assertions_per_power_domains[0].SysHandshakeOff_A 10779344 6231621 0 0
gen_assertions_per_power_domains[0].SysHandshakeOn_A 10779344 187160 0 0
gen_assertions_per_power_domains[1].LcHandshakeOff_A 10779344 12671 0 0
gen_assertions_per_power_domains[1].LcHandshakeOn_A 10779344 117025 0 0
gen_assertions_per_power_domains[1].SysHandshakeOff_A 10779344 6231621 0 0
gen_assertions_per_power_domains[1].SysHandshakeOn_A 10779344 187160 0 0


gen_assertions_per_power_domains[0].LcHandshakeOff_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 10779344 12671 0 0
T1 36725 25 0 0
T2 2611 0 0 0
T3 13165 30 0 0
T4 2419 4 0 0
T5 26137 75 0 0
T6 6023 4 0 0
T7 5467 0 0 0
T8 4845 0 0 0
T9 42316 75 0 0
T10 42286 75 0 0
T11 0 75 0 0
T20 0 4 0 0
T21 0 4 0 0

gen_assertions_per_power_domains[0].LcHandshakeOn_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 10779344 117025 0 0
T1 36725 230 0 0
T2 2611 0 0 0
T3 13165 277 0 0
T4 2419 37 0 0
T5 26137 712 0 0
T6 6023 38 0 0
T7 5467 0 0 0
T8 4845 0 0 0
T9 42316 724 0 0
T10 42286 719 0 0
T11 0 718 0 0
T20 0 38 0 0
T21 0 38 0 0

gen_assertions_per_power_domains[0].SysHandshakeOff_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 10779344 6231621 0 0
T1 36725 26403 0 0
T2 2611 981 0 0
T3 13165 6624 0 0
T4 2419 1429 0 0
T5 26137 8732 0 0
T6 6023 5019 0 0
T7 5467 569 0 0
T8 4845 875 0 0
T9 42316 24886 0 0
T10 42286 24973 0 0

gen_assertions_per_power_domains[0].SysHandshakeOn_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 10779344 187160 0 0
T1 36725 384 0 0
T2 2611 0 0 0
T3 13165 429 0 0
T4 2419 58 0 0
T5 26137 1188 0 0
T6 6023 54 0 0
T7 5467 0 0 0
T8 4845 0 0 0
T9 42316 1168 0 0
T10 42286 1068 0 0
T11 0 1162 0 0
T20 0 51 0 0
T21 0 59 0 0

gen_assertions_per_power_domains[1].LcHandshakeOff_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 10779344 12671 0 0
T1 36725 25 0 0
T2 2611 0 0 0
T3 13165 30 0 0
T4 2419 4 0 0
T5 26137 75 0 0
T6 6023 4 0 0
T7 5467 0 0 0
T8 4845 0 0 0
T9 42316 75 0 0
T10 42286 75 0 0
T11 0 75 0 0
T20 0 4 0 0
T21 0 4 0 0

gen_assertions_per_power_domains[1].LcHandshakeOn_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 10779344 117025 0 0
T1 36725 230 0 0
T2 2611 0 0 0
T3 13165 277 0 0
T4 2419 37 0 0
T5 26137 712 0 0
T6 6023 38 0 0
T7 5467 0 0 0
T8 4845 0 0 0
T9 42316 724 0 0
T10 42286 719 0 0
T11 0 718 0 0
T20 0 38 0 0
T21 0 38 0 0

gen_assertions_per_power_domains[1].SysHandshakeOff_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 10779344 6231621 0 0
T1 36725 26403 0 0
T2 2611 981 0 0
T3 13165 6624 0 0
T4 2419 1429 0 0
T5 26137 8732 0 0
T6 6023 5019 0 0
T7 5467 569 0 0
T8 4845 875 0 0
T9 42316 24886 0 0
T10 42286 24973 0 0

gen_assertions_per_power_domains[1].SysHandshakeOn_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 10779344 187160 0 0
T1 36725 384 0 0
T2 2611 0 0 0
T3 13165 429 0 0
T4 2419 58 0 0
T5 26137 1188 0 0
T6 6023 54 0 0
T7 5467 0 0 0
T8 4845 0 0 0
T9 42316 1168 0 0
T10 42286 1068 0 0
T11 0 1162 0 0
T20 0 51 0 0
T21 0 59 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%