Unified Coverage Report :: Module :: rstmgr_cascading_sva_if

Module : rstmgr_cascading_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_cascading_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_cascading_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_cascading_sva_if

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	100	1	1	100.00
ALWAYS	103	1	1	100.00
ALWAYS	107	1	1	100.00
ALWAYS	127	1	1	100.00
ALWAYS	138	1	1	100.00
ALWAYS	141	1	1	100.00
ALWAYS	144	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
100	1	1
103	1	1
107	1	1
127	1	1
138	1	1
141	1	1
144	1	1

---

Cond Coverage for Module : rstmgr_cascading_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       103
 EXPRESSION (((!scanmode)) || scan_rst_ni)
             ------1------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T4
0	1	Covered	T1,T3,T6
1	0	Covered	T1,T3,T74

 LINE       107
 EXPRESSION (por_n_i[rstmgr_pkg::DomainAonSel] && ((!scanmode)))
             ----------------1----------------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T2,T3

---

Assert Coverage for Module : rstmgr_cascading_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	31	31	100.00	31	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	31	31	100.00	31	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CascadeEffAonToRstPorAboveFall_A	50670464	8307	0	0
CascadeEffAonToRstPorAboveRise_A	50670464	8307	0	0
CascadeEffAonToRstPorIoAboveFall_A	48642004	8307	0	0
CascadeEffAonToRstPorIoAboveRise_A	48642004	8307	0	0
CascadeEffAonToRstPorIoDiv2AboveFall_A	24321622	8307	0	0
CascadeEffAonToRstPorIoDiv2AboveRise_A	24321622	8307	0	0
CascadeEffAonToRstPorIoDiv4AboveFall_A	12160605	8307	0	0
CascadeEffAonToRstPorIoDiv4AboveRise_A	12160605	8307	0	0
CascadeEffAonToRstPorUcbAboveFall_A	24322014	8307	0	0
CascadeEffAonToRstPorUcbAboveRise_A	24322014	8307	0	0
CascadeLcToLcAboveFall_A	50670464	20978	0	0
CascadeLcToLcAboveRise_A	50670464	20978	0	0
CascadeLcToLcAonAboveFall_A	1535419	20978	0	0
CascadeLcToLcAonAboveRise_A	1535419	20978	0	0
CascadeLcToLcShadowedAboveFall_A	50670464	20978	0	0
CascadeLcToLcShadowedAboveRise_A	50670464	20978	0	0
CascadePorToAonAboveFall_A	1535419	6701	0	0
CascadeSysToSysAboveFall_A	50670464	20978	0	0
CascadeSysToSysAboveRise_A	50670464	20978	0	0
ScanRstToAonRise_A	1535419	187	0	0
StablePorToAonRise_A	1535419	8307	0	0
g_power_domains[0].CascadeLcToSysAboveFall_A	10779344	20978	0	0
g_power_domains[0].CascadeLcToSysAboveRise_A	10779344	20978	0	0
g_power_domains[0].CascadeLocalRstToLcAboveFall_A	10779344	20978	0	0
g_power_domains[0].CascadeLocalRstToLcAboveRise_A	10779344	20978	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A	12160605	20978	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A	12160605	20978	0	0
g_power_domains[1].CascadeLcToSysAboveFall_A	10779344	20978	0	0
g_power_domains[1].CascadeLcToSysAboveRise_A	10779344	20978	0	0
g_power_domains[1].CascadeLocalRstToLcAboveFall_A	10779344	20978	0	0
g_power_domains[1].CascadeLocalRstToLcAboveRise_A	10779344	20978	0	0

CascadeEffAonToRstPorAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50670464	8307	0	0
T1	169726	21	0	0
T2	11561	2	0	0
T3	70545	15	0	0
T4	11076	2	0	0
T5	122157	27	0	0
T6	25715	2	0	0
T7	24250	8	0	0
T8	20972	2	0	0
T9	189518	27	0	0
T10	188599	27	0	0

CascadeEffAonToRstPorAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50670464	8307	0	0
T1	169726	21	0	0
T2	11561	2	0	0
T3	70545	15	0	0
T4	11076	2	0	0
T5	122157	27	0	0
T6	25715	2	0	0
T7	24250	8	0	0
T8	20972	2	0	0
T9	189518	27	0	0
T10	188599	27	0	0

CascadeEffAonToRstPorIoAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	48642004	8307	0	0
T1	162928	21	0	0
T2	11098	2	0	0
T3	67729	15	0	0
T4	10638	2	0	0
T5	117256	27	0	0
T6	24680	2	0	0
T7	23280	8	0	0
T8	20133	2	0	0
T9	181948	27	0	0
T10	181083	27	0	0

CascadeEffAonToRstPorIoAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	48642004	8307	0	0
T1	162928	21	0	0
T2	11098	2	0	0
T3	67729	15	0	0
T4	10638	2	0	0
T5	117256	27	0	0
T6	24680	2	0	0
T7	23280	8	0	0
T8	20133	2	0	0
T9	181948	27	0	0
T10	181083	27	0	0

CascadeEffAonToRstPorIoDiv2AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24321622	8307	0	0
T1	81465	21	0	0
T2	5548	2	0	0
T3	33873	15	0	0
T4	5320	2	0	0
T5	58655	27	0	0
T6	12342	2	0	0
T7	11640	8	0	0
T8	10067	2	0	0
T9	90966	27	0	0
T10	90536	27	0	0

CascadeEffAonToRstPorIoDiv2AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24321622	8307	0	0
T1	81465	21	0	0
T2	5548	2	0	0
T3	33873	15	0	0
T4	5320	2	0	0
T5	58655	27	0	0
T6	12342	2	0	0
T7	11640	8	0	0
T8	10067	2	0	0
T9	90966	27	0	0
T10	90536	27	0	0

CascadeEffAonToRstPorIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12160605	8307	0	0
T1	40731	21	0	0
T2	2774	2	0	0
T3	16935	15	0	0
T4	2659	2	0	0
T5	29320	27	0	0
T6	6168	2	0	0
T7	5819	8	0	0
T8	5032	2	0	0
T9	45490	27	0	0
T10	45273	27	0	0

CascadeEffAonToRstPorIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12160605	8307	0	0
T1	40731	21	0	0
T2	2774	2	0	0
T3	16935	15	0	0
T4	2659	2	0	0
T5	29320	27	0	0
T6	6168	2	0	0
T7	5819	8	0	0
T8	5032	2	0	0
T9	45490	27	0	0
T10	45273	27	0	0

CascadeEffAonToRstPorUcbAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24322014	8307	0	0
T1	81457	21	0	0
T2	5548	2	0	0
T3	33869	15	0	0
T4	5317	2	0	0
T5	58645	27	0	0
T6	12339	2	0	0
T7	11638	8	0	0
T8	10066	2	0	0
T9	90963	27	0	0
T10	90558	27	0	0

CascadeEffAonToRstPorUcbAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24322014	8307	0	0
T1	81457	21	0	0
T2	5548	2	0	0
T3	33869	15	0	0
T4	5317	2	0	0
T5	58645	27	0	0
T6	12339	2	0	0
T7	11638	8	0	0
T8	10066	2	0	0
T9	90963	27	0	0
T10	90558	27	0	0

CascadeLcToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50670464	20978	0	0
T1	169726	46	0	0
T2	11561	2	0	0
T3	70545	45	0	0
T4	11076	6	0	0
T5	122157	102	0	0
T6	25715	6	0	0
T7	24250	8	0	0
T8	20972	2	0	0
T9	189518	102	0	0
T10	188599	102	0	0

CascadeLcToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50670464	20978	0	0
T1	169726	46	0	0
T2	11561	2	0	0
T3	70545	45	0	0
T4	11076	6	0	0
T5	122157	102	0	0
T6	25715	6	0	0
T7	24250	8	0	0
T8	20972	2	0	0
T9	189518	102	0	0
T10	188599	102	0	0

CascadeLcToLcAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1535419	20978	0	0
T1	5146	46	0	0
T2	345	2	0	0
T3	2191	45	0	0
T4	330	6	0	0
T5	3679	102	0	0
T6	770	6	0	0
T7	729	8	0	0
T8	627	2	0	0
T9	5700	102	0	0
T10	5673	102	0	0

CascadeLcToLcAonAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1535419	20978	0	0
T1	5146	46	0	0
T2	345	2	0	0
T3	2191	45	0	0
T4	330	6	0	0
T5	3679	102	0	0
T6	770	6	0	0
T7	729	8	0	0
T8	627	2	0	0
T9	5700	102	0	0
T10	5673	102	0	0

CascadeLcToLcShadowedAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50670464	20978	0	0
T1	169726	46	0	0
T2	11561	2	0	0
T3	70545	45	0	0
T4	11076	6	0	0
T5	122157	102	0	0
T6	25715	6	0	0
T7	24250	8	0	0
T8	20972	2	0	0
T9	189518	102	0	0
T10	188599	102	0	0

CascadeLcToLcShadowedAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50670464	20978	0	0
T1	169726	46	0	0
T2	11561	2	0	0
T3	70545	45	0	0
T4	11076	6	0	0
T5	122157	102	0	0
T6	25715	6	0	0
T7	24250	8	0	0
T8	20972	2	0	0
T9	189518	102	0	0
T10	188599	102	0	0

CascadePorToAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1535419	6701	0	0
T1	5146	15	0	0
T2	345	5	0	0
T3	2191	7	0	0
T4	330	1	0	0
T5	3679	27	0	0
T6	770	1	0	0
T7	729	8	0	0
T8	627	17	0	0
T9	5700	27	0	0
T10	5673	27	0	0

CascadeSysToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50670464	20978	0	0
T1	169726	46	0	0
T2	11561	2	0	0
T3	70545	45	0	0
T4	11076	6	0	0
T5	122157	102	0	0
T6	25715	6	0	0
T7	24250	8	0	0
T8	20972	2	0	0
T9	189518	102	0	0
T10	188599	102	0	0

CascadeSysToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50670464	20978	0	0
T1	169726	46	0	0
T2	11561	2	0	0
T3	70545	45	0	0
T4	11076	6	0	0
T5	122157	102	0	0
T6	25715	6	0	0
T7	24250	8	0	0
T8	20972	2	0	0
T9	189518	102	0	0
T10	188599	102	0	0

ScanRstToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1535419	187	0	0
T20	334	1	0	0
T21	355	0	0	0
T22	3642	0	0	0
T29	5650	0	0	0
T30	265	0	0	0
T31	180	0	0	0
T32	555	0	0	0
T45	1102	0	0	0
T60	257	0	0	0
T76	729	0	0	0
T77	0	2	0	0
T82	0	7	0	0
T86	0	4	0	0
T87	0	4	0	0
T103	0	2	0	0
T104	0	2	0	0
T115	0	1	0	0
T117	0	1	0	0
T127	0	1	0	0

StablePorToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1535419	8307	0	0
T1	5146	21	0	0
T2	345	2	0	0
T3	2191	15	0	0
T4	330	2	0	0
T5	3679	27	0	0
T6	770	2	0	0
T7	729	8	0	0
T8	627	2	0	0
T9	5700	27	0	0
T10	5673	27	0	0

g_power_domains[0].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10779344	20978	0	0
T1	36725	46	0	0
T2	2611	2	0	0
T3	13165	45	0	0
T4	2419	6	0	0
T5	26137	102	0	0
T6	6023	6	0	0
T7	5467	8	0	0
T8	4845	2	0	0
T9	42316	102	0	0
T10	42286	102	0	0

g_power_domains[0].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10779344	20978	0	0
T1	36725	46	0	0
T2	2611	2	0	0
T3	13165	45	0	0
T4	2419	6	0	0
T5	26137	102	0	0
T6	6023	6	0	0
T7	5467	8	0	0
T8	4845	2	0	0
T9	42316	102	0	0
T10	42286	102	0	0

g_power_domains[0].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10779344	20978	0	0
T1	36725	46	0	0
T2	2611	2	0	0
T3	13165	45	0	0
T4	2419	6	0	0
T5	26137	102	0	0
T6	6023	6	0	0
T7	5467	8	0	0
T8	4845	2	0	0
T9	42316	102	0	0
T10	42286	102	0	0

g_power_domains[0].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10779344	20978	0	0
T1	36725	46	0	0
T2	2611	2	0	0
T3	13165	45	0	0
T4	2419	6	0	0
T5	26137	102	0	0
T6	6023	6	0	0
T7	5467	8	0	0
T8	4845	2	0	0
T9	42316	102	0	0
T10	42286	102	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12160605	20978	0	0
T1	40731	46	0	0
T2	2774	2	0	0
T3	16935	45	0	0
T4	2659	6	0	0
T5	29320	102	0	0
T6	6168	6	0	0
T7	5819	8	0	0
T8	5032	2	0	0
T9	45490	102	0	0
T10	45273	102	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12160605	20978	0	0
T1	40731	46	0	0
T2	2774	2	0	0
T3	16935	45	0	0
T4	2659	6	0	0
T5	29320	102	0	0
T6	6168	6	0	0
T7	5819	8	0	0
T8	5032	2	0	0
T9	45490	102	0	0
T10	45273	102	0	0

g_power_domains[1].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10779344	20978	0	0
T1	36725	46	0	0
T2	2611	2	0	0
T3	13165	45	0	0
T4	2419	6	0	0
T5	26137	102	0	0
T6	6023	6	0	0
T7	5467	8	0	0
T8	4845	2	0	0
T9	42316	102	0	0
T10	42286	102	0	0

g_power_domains[1].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10779344	20978	0	0
T1	36725	46	0	0
T2	2611	2	0	0
T3	13165	45	0	0
T4	2419	6	0	0
T5	26137	102	0	0
T6	6023	6	0	0
T7	5467	8	0	0
T8	4845	2	0	0
T9	42316	102	0	0
T10	42286	102	0	0

g_power_domains[1].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10779344	20978	0	0
T1	36725	46	0	0
T2	2611	2	0	0
T3	13165	45	0	0
T4	2419	6	0	0
T5	26137	102	0	0
T6	6023	6	0	0
T7	5467	8	0	0
T8	4845	2	0	0
T9	42316	102	0	0
T10	42286	102	0	0

g_power_domains[1].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10779344	20978	0	0
T1	36725	46	0	0
T2	2611	2	0	0
T3	13165	45	0	0
T4	2419	6	0	0
T5	26137	102	0	0
T6	6023	6	0	0
T7	5467	8	0	0
T8	4845	2	0	0
T9	42316	102	0	0
T10	42286	102	0	0