Unified Coverage Report :: Module :: rstmgr_sw_rst_sva_if

Module : rstmgr_sw_rst_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_sw_rst_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_sw_rst_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_sw_rst_sva_if

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
21	8	8

---

Cond Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Covered	Percent
Conditions	24	24	100.00
Logical	24	24	100.00
Non-Logical	0	0
Event	0	0

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[0])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T20,T21
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[1])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T30,T45
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[2])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T45,T77,T78
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[3])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T45,T53,T77
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[4])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T20,T45,T77
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[5])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T20,T21
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[6])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T45,T77,T46
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[7])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T45,T77,T46
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions[0].RstEnOff_A	12160605	13625	0	0
gen_assertions[0].RstEnOn_A	12160605	1173	0	0
gen_assertions[0].RstNOff_A	12160605	13625	0	0
gen_assertions[0].RstNOn_A	12160605	1173	0	0
gen_assertions[1].RstEnOff_A	48642004	12456	0	0
gen_assertions[1].RstEnOn_A	48642004	1071	0	0
gen_assertions[1].RstNOff_A	48642004	12456	0	0
gen_assertions[1].RstNOn_A	48642004	1071	0	0
gen_assertions[2].RstEnOff_A	24321622	12503	0	0
gen_assertions[2].RstEnOn_A	24321622	1078	0	0
gen_assertions[2].RstNOff_A	24321622	12503	0	0
gen_assertions[2].RstNOn_A	24321622	1078	0	0
gen_assertions[3].RstEnOff_A	24322014	12576	0	0
gen_assertions[3].RstEnOn_A	24322014	1123	0	0
gen_assertions[3].RstNOff_A	24322014	12576	0	0
gen_assertions[3].RstNOn_A	24322014	1123	0	0
gen_assertions[4].RstEnOff_A	1535419	20963	0	0
gen_assertions[4].RstEnOn_A	1535419	1165	0	0
gen_assertions[4].RstNOff_A	1535419	20963	0	0
gen_assertions[4].RstNOn_A	1535419	1165	0	0
gen_assertions[5].RstEnOff_A	12160605	13831	0	0
gen_assertions[5].RstEnOn_A	12160605	1186	0	0
gen_assertions[5].RstNOff_A	12160605	13831	0	0
gen_assertions[5].RstNOn_A	12160605	1186	0	0
gen_assertions[6].RstEnOff_A	12160605	13902	0	0
gen_assertions[6].RstEnOn_A	12160605	1267	0	0
gen_assertions[6].RstNOff_A	12160605	13902	0	0
gen_assertions[6].RstNOn_A	12160605	1267	0	0
gen_assertions[7].RstEnOff_A	12160605	13948	0	0
gen_assertions[7].RstEnOn_A	12160605	1316	0	0
gen_assertions[7].RstNOff_A	12160605	13948	0	0
gen_assertions[7].RstNOn_A	12160605	1316	0	0

gen_assertions[0].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12160605	13625	0	0
T1	40731	25	0	0
T2	2774	0	0	0
T3	16935	30	0	0
T4	2659	4	0	0
T5	29320	75	0	0
T6	6168	5	0	0
T7	5819	0	0	0
T8	5032	0	0	0
T9	45490	75	0	0
T10	45273	75	0	0
T11	0	75	0	0
T20	0	5	0	0
T21	0	5	0	0

gen_assertions[0].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12160605	1173	0	0
T6	6168	1	0	0
T7	5819	0	0	0
T8	5032	0	0	0
T9	45490	0	0	0
T10	45273	0	0	0
T11	56556	0	0	0
T12	2469	0	0	0
T20	2692	1	0	0
T21	2850	1	0	0
T29	45081	0	0	0
T30	0	1	0	0
T45	0	4	0	0
T52	0	1	0	0
T77	0	18	0	0
T78	0	9	0	0
T79	0	2	0	0
T80	0	2	0	0

gen_assertions[0].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12160605	13625	0	0
T1	40731	25	0	0
T2	2774	0	0	0
T3	16935	30	0	0
T4	2659	4	0	0
T5	29320	75	0	0
T6	6168	5	0	0
T7	5819	0	0	0
T8	5032	0	0	0
T9	45490	75	0	0
T10	45273	75	0	0
T11	0	75	0	0
T20	0	5	0	0
T21	0	5	0	0

gen_assertions[0].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12160605	1173	0	0
T6	6168	1	0	0
T7	5819	0	0	0
T8	5032	0	0	0
T9	45490	0	0	0
T10	45273	0	0	0
T11	56556	0	0	0
T12	2469	0	0	0
T20	2692	1	0	0
T21	2850	1	0	0
T29	45081	0	0	0
T30	0	1	0	0
T45	0	4	0	0
T52	0	1	0	0
T77	0	18	0	0
T78	0	9	0	0
T79	0	2	0	0
T80	0	2	0	0

gen_assertions[1].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	48642004	12456	0	0
T1	162928	25	0	0
T2	11098	0	0	0
T3	67729	27	0	0
T4	10638	4	0	0
T5	117256	71	0	0
T6	24680	4	0	0
T7	23280	0	0	0
T8	20133	0	0	0
T9	181948	70	0	0
T10	181083	64	0	0
T11	0	68	0	0
T20	0	3	0	0
T21	0	4	0	0

gen_assertions[1].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	48642004	1071	0	0
T6	24680	1	0	0
T7	23280	0	0	0
T8	20133	0	0	0
T9	181948	0	0	0
T10	181083	0	0	0
T11	226201	0	0	0
T12	9879	0	0	0
T20	10774	0	0	0
T21	11400	0	0	0
T29	180322	0	0	0
T30	0	3	0	0
T45	0	4	0	0
T46	0	4	0	0
T47	0	3	0	0
T77	0	23	0	0
T78	0	4	0	0
T81	0	1	0	0
T82	0	16	0	0
T83	0	3	0	0

gen_assertions[1].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	48642004	12456	0	0
T1	162928	25	0	0
T2	11098	0	0	0
T3	67729	27	0	0
T4	10638	4	0	0
T5	117256	71	0	0
T6	24680	4	0	0
T7	23280	0	0	0
T8	20133	0	0	0
T9	181948	70	0	0
T10	181083	64	0	0
T11	0	68	0	0
T20	0	3	0	0
T21	0	4	0	0

gen_assertions[1].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	48642004	1071	0	0
T6	24680	1	0	0
T7	23280	0	0	0
T8	20133	0	0	0
T9	181948	0	0	0
T10	181083	0	0	0
T11	226201	0	0	0
T12	9879	0	0	0
T20	10774	0	0	0
T21	11400	0	0	0
T29	180322	0	0	0
T30	0	3	0	0
T45	0	4	0	0
T46	0	4	0	0
T47	0	3	0	0
T77	0	23	0	0
T78	0	4	0	0
T81	0	1	0	0
T82	0	16	0	0
T83	0	3	0	0

gen_assertions[2].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24321622	12503	0	0
T1	81465	25	0	0
T2	5548	0	0	0
T3	33873	27	0	0
T4	5320	4	0	0
T5	58655	71	0	0
T6	12342	3	0	0
T7	11640	0	0	0
T8	10067	0	0	0
T9	90966	70	0	0
T10	90536	64	0	0
T11	0	68	0	0
T20	0	3	0	0
T21	0	4	0	0

gen_assertions[2].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24321622	1078	0	0
T22	58055	0	0	0
T40	11645	0	0	0
T41	11652	0	0	0
T45	17664	4	0	0
T46	0	7	0	0
T47	0	2	0	0
T53	11763	0	0	0
T60	4130	0	0	0
T61	3486	0	0	0
T74	62245	0	0	0
T75	5110	0	0	0
T76	11617	0	0	0
T77	0	20	0	0
T78	0	1	0	0
T80	0	1	0	0
T81	0	1	0	0
T82	0	15	0	0
T83	0	1	0	0
T84	0	4	0	0

gen_assertions[2].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24321622	12503	0	0
T1	81465	25	0	0
T2	5548	0	0	0
T3	33873	27	0	0
T4	5320	4	0	0
T5	58655	71	0	0
T6	12342	3	0	0
T7	11640	0	0	0
T8	10067	0	0	0
T9	90966	70	0	0
T10	90536	64	0	0
T11	0	68	0	0
T20	0	3	0	0
T21	0	4	0	0

gen_assertions[2].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24321622	1078	0	0
T22	58055	0	0	0
T40	11645	0	0	0
T41	11652	0	0	0
T45	17664	4	0	0
T46	0	7	0	0
T47	0	2	0	0
T53	11763	0	0	0
T60	4130	0	0	0
T61	3486	0	0	0
T74	62245	0	0	0
T75	5110	0	0	0
T76	11617	0	0	0
T77	0	20	0	0
T78	0	1	0	0
T80	0	1	0	0
T81	0	1	0	0
T82	0	15	0	0
T83	0	1	0	0
T84	0	4	0	0

gen_assertions[3].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24322014	12576	0	0
T1	81457	25	0	0
T2	5548	0	0	0
T3	33869	27	0	0
T4	5317	4	0	0
T5	58645	71	0	0
T6	12339	3	0	0
T7	11638	0	0	0
T8	10066	0	0	0
T9	90963	70	0	0
T10	90558	64	0	0
T11	0	68	0	0
T20	0	3	0	0
T21	0	4	0	0

gen_assertions[3].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24322014	1123	0	0
T22	58057	0	0	0
T40	11645	0	0	0
T41	11642	0	0	0
T45	17665	7	0	0
T46	0	5	0	0
T47	0	5	0	0
T53	11762	1	0	0
T60	4130	0	0	0
T61	3486	0	0	0
T74	62253	0	0	0
T75	5109	0	0	0
T76	11618	0	0	0
T77	0	25	0	0
T82	0	12	0	0
T84	0	5	0	0
T85	0	5	0	0
T86	0	14	0	0
T87	0	12	0	0

gen_assertions[3].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24322014	12576	0	0
T1	81457	25	0	0
T2	5548	0	0	0
T3	33869	27	0	0
T4	5317	4	0	0
T5	58645	71	0	0
T6	12339	3	0	0
T7	11638	0	0	0
T8	10066	0	0	0
T9	90963	70	0	0
T10	90558	64	0	0
T11	0	68	0	0
T20	0	3	0	0
T21	0	4	0	0

gen_assertions[3].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24322014	1123	0	0
T22	58057	0	0	0
T40	11645	0	0	0
T41	11642	0	0	0
T45	17665	7	0	0
T46	0	5	0	0
T47	0	5	0	0
T53	11762	1	0	0
T60	4130	0	0	0
T61	3486	0	0	0
T74	62253	0	0	0
T75	5109	0	0	0
T76	11618	0	0	0
T77	0	25	0	0
T82	0	12	0	0
T84	0	5	0	0
T85	0	5	0	0
T86	0	14	0	0
T87	0	12	0	0

gen_assertions[4].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1535419	20963	0	0
T1	5146	46	0	0
T2	345	2	0	0
T3	2191	45	0	0
T4	330	6	0	0
T5	3679	74	0	0
T6	770	5	0	0
T7	729	3	0	0
T8	627	2	0	0
T9	5700	90	0	0
T10	5673	90	0	0

gen_assertions[4].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1535419	1165	0	0
T20	334	1	0	0
T21	355	0	0	0
T22	3642	0	0	0
T29	5650	0	0	0
T30	265	0	0	0
T31	180	0	0	0
T32	555	0	0	0
T45	1102	6	0	0
T46	0	9	0	0
T47	0	6	0	0
T60	257	0	0	0
T76	729	0	0	0
T77	0	21	0	0
T82	0	16	0	0
T84	0	6	0	0
T85	0	5	0	0
T86	0	13	0	0
T87	0	9	0	0

gen_assertions[4].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1535419	20963	0	0
T1	5146	46	0	0
T2	345	2	0	0
T3	2191	45	0	0
T4	330	6	0	0
T5	3679	74	0	0
T6	770	5	0	0
T7	729	3	0	0
T8	627	2	0	0
T9	5700	90	0	0
T10	5673	90	0	0

gen_assertions[4].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1535419	1165	0	0
T20	334	1	0	0
T21	355	0	0	0
T22	3642	0	0	0
T29	5650	0	0	0
T30	265	0	0	0
T31	180	0	0	0
T32	555	0	0	0
T45	1102	6	0	0
T46	0	9	0	0
T47	0	6	0	0
T60	257	0	0	0
T76	729	0	0	0
T77	0	21	0	0
T82	0	16	0	0
T84	0	6	0	0
T85	0	5	0	0
T86	0	13	0	0
T87	0	9	0	0

gen_assertions[5].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12160605	13831	0	0
T1	40731	25	0	0
T2	2774	0	0	0
T3	16935	30	0	0
T4	2659	4	0	0
T5	29320	75	0	0
T6	6168	5	0	0
T7	5819	0	0	0
T8	5032	0	0	0
T9	45490	75	0	0
T10	45273	75	0	0
T11	0	75	0	0
T20	0	5	0	0
T21	0	5	0	0

gen_assertions[5].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12160605	1186	0	0
T6	6168	1	0	0
T7	5819	0	0	0
T8	5032	0	0	0
T9	45490	0	0	0
T10	45273	0	0	0
T11	56556	0	0	0
T12	2469	0	0	0
T20	2692	1	0	0
T21	2850	1	0	0
T29	45081	0	0	0
T45	0	9	0	0
T46	0	8	0	0
T47	0	7	0	0
T53	0	1	0	0
T77	0	22	0	0
T81	0	1	0	0
T82	0	17	0	0

gen_assertions[5].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12160605	13831	0	0
T1	40731	25	0	0
T2	2774	0	0	0
T3	16935	30	0	0
T4	2659	4	0	0
T5	29320	75	0	0
T6	6168	5	0	0
T7	5819	0	0	0
T8	5032	0	0	0
T9	45490	75	0	0
T10	45273	75	0	0
T11	0	75	0	0
T20	0	5	0	0
T21	0	5	0	0

gen_assertions[5].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12160605	1186	0	0
T6	6168	1	0	0
T7	5819	0	0	0
T8	5032	0	0	0
T9	45490	0	0	0
T10	45273	0	0	0
T11	56556	0	0	0
T12	2469	0	0	0
T20	2692	1	0	0
T21	2850	1	0	0
T29	45081	0	0	0
T45	0	9	0	0
T46	0	8	0	0
T47	0	7	0	0
T53	0	1	0	0
T77	0	22	0	0
T81	0	1	0	0
T82	0	17	0	0

gen_assertions[6].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12160605	13902	0	0
T1	40731	25	0	0
T2	2774	0	0	0
T3	16935	30	0	0
T4	2659	4	0	0
T5	29320	75	0	0
T6	6168	4	0	0
T7	5819	0	0	0
T8	5032	0	0	0
T9	45490	75	0	0
T10	45273	75	0	0
T11	0	75	0	0
T20	0	4	0	0
T21	0	4	0	0

gen_assertions[6].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12160605	1267	0	0
T22	29024	0	0	0
T40	5816	0	0	0
T41	5822	0	0	0
T45	8831	10	0	0
T46	0	10	0	0
T47	0	8	0	0
T53	5882	0	0	0
T60	2064	0	0	0
T61	1742	0	0	0
T74	31132	0	0	0
T75	2555	0	0	0
T76	5810	0	0	0
T77	0	22	0	0
T82	0	17	0	0
T84	0	8	0	0
T85	0	7	0	0
T86	0	15	0	0
T87	0	10	0	0
T88	0	11	0	0

gen_assertions[6].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12160605	13902	0	0
T1	40731	25	0	0
T2	2774	0	0	0
T3	16935	30	0	0
T4	2659	4	0	0
T5	29320	75	0	0
T6	6168	4	0	0
T7	5819	0	0	0
T8	5032	0	0	0
T9	45490	75	0	0
T10	45273	75	0	0
T11	0	75	0	0
T20	0	4	0	0
T21	0	4	0	0

gen_assertions[6].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12160605	1267	0	0
T22	29024	0	0	0
T40	5816	0	0	0
T41	5822	0	0	0
T45	8831	10	0	0
T46	0	10	0	0
T47	0	8	0	0
T53	5882	0	0	0
T60	2064	0	0	0
T61	1742	0	0	0
T74	31132	0	0	0
T75	2555	0	0	0
T76	5810	0	0	0
T77	0	22	0	0
T82	0	17	0	0
T84	0	8	0	0
T85	0	7	0	0
T86	0	15	0	0
T87	0	10	0	0
T88	0	11	0	0

gen_assertions[7].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12160605	13948	0	0
T1	40731	25	0	0
T2	2774	0	0	0
T3	16935	30	0	0
T4	2659	4	0	0
T5	29320	75	0	0
T6	6168	4	0	0
T7	5819	0	0	0
T8	5032	0	0	0
T9	45490	75	0	0
T10	45273	75	0	0
T11	0	75	0	0
T20	0	4	0	0
T21	0	4	0	0

gen_assertions[7].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12160605	1316	0	0
T22	29024	0	0	0
T40	5816	0	0	0
T41	5822	0	0	0
T45	8831	11	0	0
T46	0	11	0	0
T47	0	8	0	0
T53	5882	0	0	0
T60	2064	0	0	0
T61	1742	0	0	0
T74	31132	0	0	0
T75	2555	0	0	0
T76	5810	0	0	0
T77	0	19	0	0
T82	0	15	0	0
T84	0	8	0	0
T85	0	8	0	0
T86	0	9	0	0
T87	0	12	0	0
T89	0	1	0	0

gen_assertions[7].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12160605	13948	0	0
T1	40731	25	0	0
T2	2774	0	0	0
T3	16935	30	0	0
T4	2659	4	0	0
T5	29320	75	0	0
T6	6168	4	0	0
T7	5819	0	0	0
T8	5032	0	0	0
T9	45490	75	0	0
T10	45273	75	0	0
T11	0	75	0	0
T20	0	4	0	0
T21	0	4	0	0

gen_assertions[7].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12160605	1316	0	0
T22	29024	0	0	0
T40	5816	0	0	0
T41	5822	0	0	0
T45	8831	11	0	0
T46	0	11	0	0
T47	0	8	0	0
T53	5882	0	0	0
T60	2064	0	0	0
T61	1742	0	0	0
T74	31132	0	0	0
T75	2555	0	0	0
T76	5810	0	0	0
T77	0	19	0	0
T82	0	15	0	0
T84	0	8	0	0
T85	0	8	0	0
T86	0	9	0	0
T87	0	12	0	0
T89	0	1	0	0