Unified Coverage Report :: Module :: rstmgr_csr_assert_fpv

Module : rstmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rstmgr_csr_assert_0/rstmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rstmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rstmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	19	19	100.00	19	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	19	19	100.00	19	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	11652890	9069	0	0
alert_regwen_rd_A	11652890	4681	0	0
cpu_regwen_rd_A	11652890	4464	0	0
sw_rst_ctrl_n_0_rd_A	11652890	7725	0	0
sw_rst_ctrl_n_1_rd_A	11652890	7516	0	0
sw_rst_ctrl_n_2_rd_A	11652890	7629	0	0
sw_rst_ctrl_n_3_rd_A	11652890	7773	0	0
sw_rst_ctrl_n_4_rd_A	11652890	7635	0	0
sw_rst_ctrl_n_5_rd_A	11652890	7588	0	0
sw_rst_ctrl_n_6_rd_A	11652890	7783	0	0
sw_rst_ctrl_n_7_rd_A	11652890	7980	0	0
sw_rst_regwen_0_rd_A	11652890	4741	0	0
sw_rst_regwen_1_rd_A	11652890	5151	0	0
sw_rst_regwen_2_rd_A	11652890	4746	0	0
sw_rst_regwen_3_rd_A	11652890	4782	0	0
sw_rst_regwen_4_rd_A	11652890	4781	0	0
sw_rst_regwen_5_rd_A	11652890	5127	0	0
sw_rst_regwen_6_rd_A	11652890	4702	0	0
sw_rst_regwen_7_rd_A	11652890	4674	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11652890	9069	0	0
T48	3389	31	0	0
T49	11637	2	0	0
T54	4216	402	0	0
T55	5424	204	0	0
T62	4734	20	0	0
T93	18214	5	0	0
T94	10653	396	0	0
T95	20063	1	0	0
T97	9785	2	0	0
T102	9136	1	0	0

alert_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11652890	4681	0	0
T1	36725	78	0	0
T2	2611	0	0	0
T3	13165	0	0	0
T4	2419	0	0	0
T5	26137	0	0	0
T6	6023	0	0	0
T7	5467	0	0	0
T8	4845	0	0	0
T9	42316	0	0	0
T10	42286	0	0	0
T73	0	36	0	0
T106	0	42	0	0
T111	0	231	0	0
T135	0	236	0	0
T136	0	495	0	0
T137	0	28	0	0
T138	0	70	0	0
T139	0	51	0	0
T140	0	83	0	0

cpu_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11652890	4464	0	0
T1	36725	81	0	0
T2	2611	0	0	0
T3	13165	0	0	0
T4	2419	0	0	0
T5	26137	0	0	0
T6	6023	0	0	0
T7	5467	0	0	0
T8	4845	0	0	0
T9	42316	0	0	0
T10	42286	0	0	0
T73	0	50	0	0
T106	0	51	0	0
T111	0	226	0	0
T135	0	181	0	0
T136	0	495	0	0
T137	0	42	0	0
T138	0	110	0	0
T139	0	65	0	0
T140	0	92	0	0

sw_rst_ctrl_n_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11652890	7725	0	0
T1	36725	59	0	0
T2	2611	0	0	0
T3	13165	0	0	0
T4	2419	0	0	0
T5	26137	0	0	0
T6	6023	18	0	0
T7	5467	0	0	0
T8	4845	0	0	0
T9	42316	0	0	0
T10	42286	0	0	0
T45	0	104	0	0
T46	0	174	0	0
T47	0	158	0	0
T53	0	5	0	0
T79	0	18	0	0
T106	0	38	0	0
T141	0	11	0	0
T142	0	19	0	0

sw_rst_ctrl_n_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11652890	7516	0	0
T1	36725	66	0	0
T2	2611	0	0	0
T3	13165	0	0	0
T4	2419	0	0	0
T5	26137	0	0	0
T6	6023	18	0	0
T7	5467	0	0	0
T8	4845	0	0	0
T9	42316	0	0	0
T10	42286	0	0	0
T45	0	71	0	0
T46	0	144	0	0
T47	0	148	0	0
T53	0	19	0	0
T79	0	20	0	0
T106	0	41	0	0
T141	0	15	0	0
T143	0	4	0	0

sw_rst_ctrl_n_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11652890	7629	0	0
T1	36725	70	0	0
T2	2611	0	0	0
T3	13165	0	0	0
T4	2419	0	0	0
T5	26137	0	0	0
T6	6023	11	0	0
T7	5467	0	0	0
T8	4845	0	0	0
T9	42316	0	0	0
T10	42286	0	0	0
T45	0	80	0	0
T46	0	166	0	0
T47	0	156	0	0
T53	0	4	0	0
T79	0	21	0	0
T106	0	65	0	0
T141	0	15	0	0
T144	0	4	0	0

sw_rst_ctrl_n_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11652890	7773	0	0
T1	36725	75	0	0
T2	2611	0	0	0
T3	13165	0	0	0
T4	2419	0	0	0
T5	26137	0	0	0
T6	6023	5	0	0
T7	5467	0	0	0
T8	4845	0	0	0
T9	42316	0	0	0
T10	42286	0	0	0
T45	0	96	0	0
T46	0	197	0	0
T47	0	151	0	0
T53	0	15	0	0
T79	0	21	0	0
T106	0	27	0	0
T143	0	8	0	0
T144	0	9	0	0

sw_rst_ctrl_n_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11652890	7635	0	0
T1	36725	74	0	0
T2	2611	0	0	0
T3	13165	0	0	0
T4	2419	0	0	0
T5	26137	0	0	0
T6	6023	13	0	0
T7	5467	0	0	0
T8	4845	0	0	0
T9	42316	0	0	0
T10	42286	0	0	0
T45	0	86	0	0
T46	0	203	0	0
T47	0	130	0	0
T53	0	16	0	0
T79	0	15	0	0
T106	0	58	0	0
T141	0	13	0	0
T144	0	2	0	0

sw_rst_ctrl_n_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11652890	7588	0	0
T1	36725	64	0	0
T2	2611	0	0	0
T3	13165	0	0	0
T4	2419	0	0	0
T5	26137	0	0	0
T6	6023	21	0	0
T7	5467	0	0	0
T8	4845	0	0	0
T9	42316	0	0	0
T10	42286	0	0	0
T45	0	116	0	0
T46	0	183	0	0
T47	0	114	0	0
T53	0	20	0	0
T79	0	18	0	0
T106	0	63	0	0
T143	0	2	0	0
T144	0	4	0	0

sw_rst_ctrl_n_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11652890	7783	0	0
T1	36725	74	0	0
T2	2611	0	0	0
T3	13165	0	0	0
T4	2419	0	0	0
T5	26137	0	0	0
T6	6023	13	0	0
T7	5467	0	0	0
T8	4845	0	0	0
T9	42316	0	0	0
T10	42286	0	0	0
T45	0	77	0	0
T46	0	173	0	0
T47	0	126	0	0
T53	0	18	0	0
T79	0	25	0	0
T106	0	49	0	0
T143	0	7	0	0
T144	0	7	0	0

sw_rst_ctrl_n_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11652890	7980	0	0
T1	36725	58	0	0
T2	2611	0	0	0
T3	13165	0	0	0
T4	2419	0	0	0
T5	26137	0	0	0
T6	6023	11	0	0
T7	5467	0	0	0
T8	4845	0	0	0
T9	42316	0	0	0
T10	42286	0	0	0
T45	0	92	0	0
T46	0	206	0	0
T47	0	135	0	0
T53	0	9	0	0
T79	0	17	0	0
T106	0	39	0	0
T141	0	12	0	0
T144	0	2	0	0

sw_rst_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11652890	4741	0	0
T1	36725	78	0	0
T2	2611	0	0	0
T3	13165	0	0	0
T4	2419	0	0	0
T5	26137	0	0	0
T6	6023	5	0	0
T7	5467	0	0	0
T8	4845	0	0	0
T9	42316	0	0	0
T10	42286	0	0	0
T45	0	22	0	0
T46	0	36	0	0
T47	0	35	0	0
T53	0	14	0	0
T106	0	60	0	0
T141	0	10	0	0
T142	0	8	0	0
T145	0	26	0	0

sw_rst_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11652890	5151	0	0
T1	36725	54	0	0
T2	2611	0	0	0
T3	13165	0	0	0
T4	2419	0	0	0
T5	26137	0	0	0
T6	6023	0	0	0
T7	5467	0	0	0
T8	4845	0	0	0
T9	42316	0	0	0
T10	42286	0	0	0
T45	0	35	0	0
T46	0	21	0	0
T47	0	51	0	0
T53	0	5	0	0
T106	0	60	0	0
T111	0	252	0	0
T141	0	10	0	0
T145	0	38	0	0
T146	0	9	0	0

sw_rst_regwen_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11652890	4746	0	0
T1	36725	56	0	0
T2	2611	0	0	0
T3	13165	0	0	0
T4	2419	0	0	0
T5	26137	0	0	0
T6	6023	8	0	0
T7	5467	0	0	0
T8	4845	0	0	0
T9	42316	0	0	0
T10	42286	0	0	0
T45	0	21	0	0
T46	0	53	0	0
T47	0	31	0	0
T53	0	10	0	0
T106	0	58	0	0
T141	0	6	0	0
T145	0	18	0	0
T146	0	1	0	0

sw_rst_regwen_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11652890	4782	0	0
T1	36725	87	0	0
T2	2611	0	0	0
T3	13165	0	0	0
T4	2419	0	0	0
T5	26137	0	0	0
T6	6023	5	0	0
T7	5467	0	0	0
T8	4845	0	0	0
T9	42316	0	0	0
T10	42286	0	0	0
T45	0	13	0	0
T46	0	31	0	0
T47	0	24	0	0
T53	0	11	0	0
T106	0	51	0	0
T141	0	12	0	0
T142	0	3	0	0
T145	0	38	0	0

sw_rst_regwen_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11652890	4781	0	0
T1	36725	54	0	0
T2	2611	0	0	0
T3	13165	0	0	0
T4	2419	0	0	0
T5	26137	0	0	0
T6	6023	11	0	0
T7	5467	0	0	0
T8	4845	0	0	0
T9	42316	0	0	0
T10	42286	0	0	0
T45	0	11	0	0
T46	0	37	0	0
T47	0	29	0	0
T53	0	2	0	0
T106	0	28	0	0
T141	0	4	0	0
T145	0	25	0	0
T146	0	8	0	0

sw_rst_regwen_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11652890	5127	0	0
T1	36725	82	0	0
T2	2611	0	0	0
T3	13165	0	0	0
T4	2419	0	0	0
T5	26137	0	0	0
T6	6023	6	0	0
T7	5467	0	0	0
T8	4845	0	0	0
T9	42316	0	0	0
T10	42286	0	0	0
T45	0	26	0	0
T46	0	29	0	0
T47	0	36	0	0
T53	0	14	0	0
T106	0	53	0	0
T141	0	7	0	0
T142	0	5	0	0
T145	0	25	0	0

sw_rst_regwen_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11652890	4702	0	0
T1	36725	85	0	0
T2	2611	0	0	0
T3	13165	0	0	0
T4	2419	0	0	0
T5	26137	0	0	0
T6	6023	8	0	0
T7	5467	0	0	0
T8	4845	0	0	0
T9	42316	0	0	0
T10	42286	0	0	0
T45	0	31	0	0
T46	0	30	0	0
T47	0	43	0	0
T53	0	16	0	0
T106	0	57	0	0
T141	0	12	0	0
T142	0	6	0	0
T145	0	24	0	0

sw_rst_regwen_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11652890	4674	0	0
T1	36725	84	0	0
T2	2611	0	0	0
T3	13165	0	0	0
T4	2419	0	0	0
T5	26137	0	0	0
T6	6023	10	0	0
T7	5467	0	0	0
T8	4845	0	0	0
T9	42316	0	0	0
T10	42286	0	0	0
T45	0	25	0	0
T46	0	42	0	0
T47	0	32	0	0
T53	0	10	0	0
T106	0	63	0	0
T141	0	2	0	0
T145	0	36	0	0
T146	0	8	0	0