Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	607800	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

364605

1

T1

150

T2

69

T3

1056

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	519128	1			T1	184		T2	87		T3	1640
values[0x0]	225998	1			T1	88		T2	42		T3	656
values[0x1]	227279	1			T1	110		T2	51		T3	652

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	510064	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

462341

1

T1

194

T2

83

T3

1383

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	3354	1			T3	1		T10	74		T12	7
valid_sources[0x01]	6229	1			T1	3		T3	10		T10	86
valid_sources[0x02]	3576	1			T1	2		T3	25		T10	61
valid_sources[0x03]	3471	1			T1	1		T3	13		T10	73
valid_sources[0x04]	3574	1			T1	3		T3	17		T10	77
valid_sources[0x05]	3354	1			T3	10		T10	63		T12	15
valid_sources[0x06]	3688	1			T3	26		T6	1		T10	77
valid_sources[0x07]	4977	1			T1	4		T3	23		T10	67
valid_sources[0x08]	3761	1			T1	1		T3	10		T10	68
valid_sources[0x09]	3206	1			T1	5		T3	12		T5	4
valid_sources[0x0a]	3589	1			T1	2		T2	8		T3	7
valid_sources[0x0b]	3550	1			T3	5		T5	2		T7	1
valid_sources[0x0c]	3018	1			T1	1		T3	14		T10	68
valid_sources[0x0d]	3234	1			T1	1		T3	32		T10	69
valid_sources[0x0e]	3807	1			T1	1		T3	19		T10	68
valid_sources[0x0f]	3793	1			T3	13		T10	75		T11	1
valid_sources[0x10]	3116	1			T1	2		T3	6		T10	69
valid_sources[0x11]	8153	1			T1	1		T3	10		T7	3
valid_sources[0x12]	3253	1			T3	15		T10	70		T12	9
valid_sources[0x13]	3325	1			T3	21		T10	60		T12	21
valid_sources[0x14]	4126	1			T1	1		T3	16		T10	64
valid_sources[0x15]	3584	1			T1	3		T3	24		T10	71
valid_sources[0x16]	3847	1			T3	9		T10	70		T11	3
valid_sources[0x17]	3076	1			T1	3		T10	75		T12	9
valid_sources[0x18]	4026	1			T3	7		T10	70		T11	2
valid_sources[0x19]	3824	1			T1	2		T3	2		T10	82
valid_sources[0x1a]	3439	1			T1	1		T3	22		T10	70
valid_sources[0x1b]	4288	1			T1	3		T3	8		T10	66
valid_sources[0x1c]	3281	1			T3	11		T10	69		T11	3
valid_sources[0x1d]	2854	1			T1	4		T3	5		T10	51
valid_sources[0x1e]	3404	1			T1	1		T3	6		T10	65
valid_sources[0x1f]	3962	1			T1	1		T2	6		T3	8
valid_sources[0x20]	3802	1			T1	6		T3	3		T10	78
valid_sources[0x21]	4144	1			T1	1		T3	25		T10	89
valid_sources[0x22]	4881	1			T3	10		T5	1		T10	64
valid_sources[0x23]	2824	1			T1	5		T3	9		T10	70
valid_sources[0x24]	3101	1			T1	1		T3	15		T10	67
valid_sources[0x25]	3673	1			T1	3		T3	2		T10	66
valid_sources[0x26]	4439	1			T1	2		T3	11		T10	64
valid_sources[0x27]	3415	1			T3	29		T10	80		T11	1
valid_sources[0x28]	3623	1			T1	7		T3	8		T7	1
valid_sources[0x29]	4149	1			T1	3		T3	19		T10	66
valid_sources[0x2a]	4207	1			T1	5		T3	5		T10	82
valid_sources[0x2b]	4107	1			T1	1		T2	9		T3	2
valid_sources[0x2c]	3345	1			T1	2		T3	18		T10	55
valid_sources[0x2d]	4752	1			T3	8		T10	61		T12	10
valid_sources[0x2e]	3475	1			T1	1		T3	9		T10	64
valid_sources[0x2f]	5580	1			T1	4		T3	16		T10	68
valid_sources[0x30]	3351	1			T1	3		T3	6		T10	81
valid_sources[0x31]	3308	1			T1	2		T3	9		T10	92
valid_sources[0x32]	4635	1			T1	1		T3	3		T10	78
valid_sources[0x33]	3959	1			T3	13		T10	61		T11	1
valid_sources[0x34]	3335	1			T1	1		T3	9		T10	65
valid_sources[0x35]	3674	1			T1	1		T3	5		T10	53
valid_sources[0x36]	3278	1			T1	1		T3	9		T10	71
valid_sources[0x37]	3495	1			T1	1		T3	15		T10	72
valid_sources[0x38]	4272	1			T2	4		T3	10		T10	73
valid_sources[0x39]	3265	1			T3	8		T10	87		T12	16
valid_sources[0x3a]	5117	1			T1	4		T3	6		T10	66
valid_sources[0x3b]	3438	1			T3	4		T10	61		T12	13
valid_sources[0x3c]	4221	1			T3	15		T10	74		T12	15
valid_sources[0x3d]	3576	1			T1	1		T3	6		T10	73
valid_sources[0x3e]	3836	1			T1	3		T3	12		T10	63
valid_sources[0x3f]	3245	1			T1	2		T3	15		T10	76
valid_sources[0x40]	3302	1			T2	7		T3	10		T10	88
valid_sources[0x41]	3088	1			T1	1		T3	6		T10	87
valid_sources[0x42]	3793	1			T1	1		T3	14		T10	68
valid_sources[0x43]	4036	1			T1	2		T3	16		T10	91
valid_sources[0x44]	3091	1			T1	1		T3	11		T10	56
valid_sources[0x45]	3279	1			T1	1		T3	5		T10	71
valid_sources[0x46]	4030	1			T3	12		T10	86		T11	3
valid_sources[0x47]	3001	1			T1	2		T2	13		T3	12
valid_sources[0x48]	4365	1			T1	1		T3	16		T10	76
valid_sources[0x49]	3882	1			T3	15		T10	53		T12	10
valid_sources[0x4a]	3351	1			T1	2		T3	17		T10	95
valid_sources[0x4b]	3355	1			T3	26		T10	65		T12	17
valid_sources[0x4c]	3516	1			T3	14		T10	69		T11	2
valid_sources[0x4d]	4035	1			T1	4		T3	11		T10	75
valid_sources[0x4e]	4792	1			T1	3		T3	7		T10	78
valid_sources[0x4f]	7706	1			T3	5		T5	4		T10	82
valid_sources[0x50]	4648	1			T1	1		T2	16		T3	15
valid_sources[0x51]	4384	1			T3	13		T10	66		T12	11
valid_sources[0x52]	6889	1			T1	1		T3	10		T10	74
valid_sources[0x53]	3397	1			T1	2		T3	7		T10	64
valid_sources[0x54]	4110	1			T1	3		T3	19		T10	71
valid_sources[0x55]	4090	1			T1	2		T3	5		T10	71
valid_sources[0x56]	4724	1			T1	2		T3	10		T10	80
valid_sources[0x57]	7723	1			T1	2		T3	15		T10	68
valid_sources[0x58]	3294	1			T1	1		T3	12		T10	77
valid_sources[0x59]	4447	1			T1	2		T3	3		T10	68
valid_sources[0x5a]	3763	1			T1	1		T3	6		T10	72
valid_sources[0x5b]	3148	1			T1	1		T3	2		T10	76
valid_sources[0x5c]	2757	1			T3	12		T10	72		T12	17
valid_sources[0x5d]	3772	1			T1	2		T3	24		T10	69
valid_sources[0x5e]	3431	1			T1	1		T3	13		T10	89
valid_sources[0x5f]	3293	1			T1	2		T3	9		T10	68
valid_sources[0x60]	4518	1			T1	3		T3	8		T10	64
valid_sources[0x61]	3411	1			T1	3		T3	14		T10	71
valid_sources[0x62]	2919	1			T3	11		T10	64		T12	8
valid_sources[0x63]	4007	1			T1	4		T3	5		T10	53
valid_sources[0x64]	3502	1			T1	5		T3	5		T10	71
valid_sources[0x65]	4518	1			T3	11		T10	84		T12	17
valid_sources[0x66]	3219	1			T3	13		T10	72		T12	9
valid_sources[0x67]	3905	1			T1	2		T3	8		T10	79
valid_sources[0x68]	3072	1			T3	12		T10	86		T12	11
valid_sources[0x69]	3420	1			T3	7		T10	72		T11	2
valid_sources[0x6a]	3259	1			T1	1		T2	11		T3	12
valid_sources[0x6b]	3392	1			T1	2		T3	36		T10	58
valid_sources[0x6c]	4487	1			T3	2		T10	70		T11	1
valid_sources[0x6d]	3348	1			T1	1		T3	13		T10	67
valid_sources[0x6e]	3224	1			T1	3		T3	11		T10	74
valid_sources[0x6f]	3717	1			T1	3		T3	6		T5	1
valid_sources[0x70]	3912	1			T3	14		T7	1		T10	60
valid_sources[0x71]	3802	1			T1	1		T3	10		T10	57
valid_sources[0x72]	3240	1			T1	5		T3	9		T10	46
valid_sources[0x73]	3258	1			T1	3		T3	22		T10	77
valid_sources[0x74]	3164	1			T1	1		T3	13		T10	74
valid_sources[0x75]	4700	1			T1	1		T3	17		T10	78
valid_sources[0x76]	3090	1			T1	1		T3	9		T10	75
valid_sources[0x77]	3237	1			T1	4		T3	10		T7	2
valid_sources[0x78]	3518	1			T3	16		T10	71		T24	2
valid_sources[0x79]	3178	1			T1	1		T10	81		T12	12
valid_sources[0x7a]	3312	1			T1	1		T3	19		T10	99
valid_sources[0x7b]	3633	1			T1	1		T3	9		T5	8
valid_sources[0x7c]	4687	1			T3	11		T10	73		T12	6
valid_sources[0x7d]	3425	1			T1	1		T3	4		T10	79
valid_sources[0x7e]	3706	1			T1	1		T3	7		T10	61
valid_sources[0x7f]	3373	1			T3	4		T10	69		T12	23
valid_sources[0x80]	4414	1			T1	1		T3	10		T10	74

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

243294

1

T1

102

T2

48

T3

741

values[0x0]

all_enables

biggest_size

78858

1

T1

30

T2

12

T3

217

values[0x1]

all_enables

biggest_size

42453

1

T1

18

T2

9

T3

98