Unified Coverage Report :: Module :: rstmgr_cascading_sva_if

Module : rstmgr_cascading_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_cascading_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_cascading_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_cascading_sva_if

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	100	1	1	100.00
ALWAYS	103	1	1	100.00
ALWAYS	107	1	1	100.00
ALWAYS	127	1	1	100.00
ALWAYS	138	1	1	100.00
ALWAYS	141	1	1	100.00
ALWAYS	144	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
100	1	1
103	1	1
107	1	1
127	1	1
138	1	1
141	1	1
144	1	1

---

Cond Coverage for Module : rstmgr_cascading_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       103
 EXPRESSION (((!scanmode)) || scan_rst_ni)
             ------1------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T3,T4,T10
0	1	Covered	T3,T10,T25
1	0	Covered	T3,T10,T25

 LINE       107
 EXPRESSION (por_n_i[rstmgr_pkg::DomainAonSel] && ((!scanmode)))
             ----------------1----------------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T3,T6,T7
1	0	Covered	T3,T4,T10
1	1	Covered	T1,T2,T3

---

Assert Coverage for Module : rstmgr_cascading_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	31	31	100.00	31	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	31	31	100.00	31	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CascadeEffAonToRstPorAboveFall_A	56130697	9363	0	0
CascadeEffAonToRstPorAboveRise_A	56130697	9363	0	0
CascadeEffAonToRstPorIoAboveFall_A	53883122	9363	0	0
CascadeEffAonToRstPorIoAboveRise_A	53883122	9363	0	0
CascadeEffAonToRstPorIoDiv2AboveFall_A	26942970	9363	0	0
CascadeEffAonToRstPorIoDiv2AboveRise_A	26942970	9363	0	0
CascadeEffAonToRstPorIoDiv4AboveFall_A	13471045	9363	0	0
CascadeEffAonToRstPorIoDiv4AboveRise_A	13471045	9363	0	0
CascadeEffAonToRstPorUcbAboveFall_A	26943129	9363	0	0
CascadeEffAonToRstPorUcbAboveRise_A	26943129	9363	0	0
CascadeLcToLcAboveFall_A	56130697	22435	0	0
CascadeLcToLcAboveRise_A	56130697	22435	0	0
CascadeLcToLcAonAboveFall_A	1700981	22435	0	0
CascadeLcToLcAonAboveRise_A	1700981	22435	0	0
CascadeLcToLcShadowedAboveFall_A	56130697	22435	0	0
CascadeLcToLcShadowedAboveRise_A	56130697	22435	0	0
CascadePorToAonAboveFall_A	1700981	7579	0	0
CascadeSysToSysAboveFall_A	56130697	22435	0	0
CascadeSysToSysAboveRise_A	56130697	22435	0	0
ScanRstToAonRise_A	1700981	220	0	0
StablePorToAonRise_A	1700981	9363	0	0
g_power_domains[0].CascadeLcToSysAboveFall_A	11932361	22435	0	0
g_power_domains[0].CascadeLcToSysAboveRise_A	11932361	22435	0	0
g_power_domains[0].CascadeLocalRstToLcAboveFall_A	11932361	22435	0	0
g_power_domains[0].CascadeLocalRstToLcAboveRise_A	11932361	22435	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A	13471045	22435	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A	13471045	22435	0	0
g_power_domains[1].CascadeLcToSysAboveFall_A	11932361	22435	0	0
g_power_domains[1].CascadeLcToSysAboveRise_A	11932361	22435	0	0
g_power_domains[1].CascadeLocalRstToLcAboveFall_A	11932361	22435	0	0
g_power_domains[1].CascadeLocalRstToLcAboveRise_A	11932361	22435	0	0

CascadeEffAonToRstPorAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	56130697	9363	0	0
T1	15509	1	0	0
T2	11252	1	0	0
T3	93162	19	0	0
T4	14198	2	0	0
T5	7888	1	0	0
T6	14438	2	0	0
T7	164553	541	0	0
T8	121988	27	0	0
T9	24253	8	0	0
T10	574652	113	0	0

CascadeEffAonToRstPorAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	56130697	9363	0	0
T1	15509	1	0	0
T2	11252	1	0	0
T3	93162	19	0	0
T4	14198	2	0	0
T5	7888	1	0	0
T6	14438	2	0	0
T7	164553	541	0	0
T8	121988	27	0	0
T9	24253	8	0	0
T10	574652	113	0	0

CascadeEffAonToRstPorIoAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53883122	9363	0	0
T1	14889	1	0	0
T2	10802	1	0	0
T3	89455	19	0	0
T4	13628	2	0	0
T5	7571	1	0	0
T6	13859	2	0	0
T7	157980	541	0	0
T8	117057	27	0	0
T9	23281	8	0	0
T10	551630	113	0	0

CascadeEffAonToRstPorIoAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53883122	9363	0	0
T1	14889	1	0	0
T2	10802	1	0	0
T3	89455	19	0	0
T4	13628	2	0	0
T5	7571	1	0	0
T6	13859	2	0	0
T7	157980	541	0	0
T8	117057	27	0	0
T9	23281	8	0	0
T10	551630	113	0	0

CascadeEffAonToRstPorIoDiv2AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26942970	9363	0	0
T1	7443	1	0	0
T2	5401	1	0	0
T3	44726	19	0	0
T4	6815	2	0	0
T5	3785	1	0	0
T6	6930	2	0	0
T7	789912	541	0	0
T8	58559	27	0	0
T9	11637	8	0	0
T10	275843	113	0	0

CascadeEffAonToRstPorIoDiv2AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26942970	9363	0	0
T1	7443	1	0	0
T2	5401	1	0	0
T3	44726	19	0	0
T4	6815	2	0	0
T5	3785	1	0	0
T6	6930	2	0	0
T7	789912	541	0	0
T8	58559	27	0	0
T9	11637	8	0	0
T10	275843	113	0	0

CascadeEffAonToRstPorIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13471045	9363	0	0
T1	3721	1	0	0
T2	2700	1	0	0
T3	22366	19	0	0
T4	3407	2	0	0
T5	1892	1	0	0
T6	3463	2	0	0
T7	394901	541	0	0
T8	29287	27	0	0
T9	5816	8	0	0
T10	137924	113	0	0

CascadeEffAonToRstPorIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13471045	9363	0	0
T1	3721	1	0	0
T2	2700	1	0	0
T3	22366	19	0	0
T4	3407	2	0	0
T5	1892	1	0	0
T6	3463	2	0	0
T7	394901	541	0	0
T8	29287	27	0	0
T9	5816	8	0	0
T10	137924	113	0	0

CascadeEffAonToRstPorUcbAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26943129	9363	0	0
T1	7443	1	0	0
T2	5401	1	0	0
T3	44733	19	0	0
T4	6816	2	0	0
T5	3785	1	0	0
T6	6930	2	0	0
T7	789873	541	0	0
T8	58569	27	0	0
T9	11642	8	0	0
T10	275852	113	0	0

CascadeEffAonToRstPorUcbAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26943129	9363	0	0
T1	7443	1	0	0
T2	5401	1	0	0
T3	44733	19	0	0
T4	6816	2	0	0
T5	3785	1	0	0
T6	6930	2	0	0
T7	789873	541	0	0
T8	58569	27	0	0
T9	11642	8	0	0
T10	275852	113	0	0

CascadeLcToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	56130697	22435	0	0
T1	15509	20	0	0
T2	11252	10	0	0
T3	93162	59	0	0
T4	14198	6	0	0
T5	7888	1	0	0
T6	14438	2	0	0
T7	164553	541	0	0
T8	121988	102	0	0
T9	24253	8	0	0
T10	574652	322	0	0

CascadeLcToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	56130697	22435	0	0
T1	15509	20	0	0
T2	11252	10	0	0
T3	93162	59	0	0
T4	14198	6	0	0
T5	7888	1	0	0
T6	14438	2	0	0
T7	164553	541	0	0
T8	121988	102	0	0
T9	24253	8	0	0
T10	574652	322	0	0

CascadeLcToLcAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1700981	22435	0	0
T1	464	20	0	0
T2	337	10	0	0
T3	2885	59	0	0
T4	425	6	0	0
T5	236	1	0	0
T6	431	2	0	0
T7	49612	541	0	0
T8	3674	102	0	0
T9	730	8	0	0
T10	17598	322	0	0

CascadeLcToLcAonAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1700981	22435	0	0
T1	464	20	0	0
T2	337	10	0	0
T3	2885	59	0	0
T4	425	6	0	0
T5	236	1	0	0
T6	431	2	0	0
T7	49612	541	0	0
T8	3674	102	0	0
T9	730	8	0	0
T10	17598	322	0	0

CascadeLcToLcShadowedAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	56130697	22435	0	0
T1	15509	20	0	0
T2	11252	10	0	0
T3	93162	59	0	0
T4	14198	6	0	0
T5	7888	1	0	0
T6	14438	2	0	0
T7	164553	541	0	0
T8	121988	102	0	0
T9	24253	8	0	0
T10	574652	322	0	0

CascadeLcToLcShadowedAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	56130697	22435	0	0
T1	15509	20	0	0
T2	11252	10	0	0
T3	93162	59	0	0
T4	14198	6	0	0
T5	7888	1	0	0
T6	14438	2	0	0
T7	164553	541	0	0
T8	121988	102	0	0
T9	24253	8	0	0
T10	574652	322	0	0

CascadePorToAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1700981	7579	0	0
T1	464	1	0	0
T2	337	1	0	0
T3	2885	13	0	0
T4	425	1	0	0
T5	236	1	0	0
T6	431	9	0	0
T7	49612	541	0	0
T8	3674	27	0	0
T9	730	8	0	0
T10	17598	61	0	0

CascadeSysToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	56130697	22435	0	0
T1	15509	20	0	0
T2	11252	10	0	0
T3	93162	59	0	0
T4	14198	6	0	0
T5	7888	1	0	0
T6	14438	2	0	0
T7	164553	541	0	0
T8	121988	102	0	0
T9	24253	8	0	0
T10	574652	322	0	0

CascadeSysToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	56130697	22435	0	0
T1	15509	20	0	0
T2	11252	10	0	0
T3	93162	59	0	0
T4	14198	6	0	0
T5	7888	1	0	0
T6	14438	2	0	0
T7	164553	541	0	0
T8	121988	102	0	0
T9	24253	8	0	0
T10	574652	322	0	0

ScanRstToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1700981	220	0	0
T10	17598	4	0	0
T11	318	0	0	0
T12	3676	0	0	0
T13	319	0	0	0
T23	49665	0	0	0
T24	198	0	0	0
T25	5177	1	0	0
T35	1575	0	0	0
T37	322	0	0	0
T38	728	0	0	0
T40	0	6	0	0
T70	0	7	0	0
T81	0	1	0	0
T82	0	1	0	0
T83	0	1	0	0
T87	0	7	0	0
T91	0	1	0	0
T126	0	1	0	0

StablePorToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1700981	9363	0	0
T1	464	1	0	0
T2	337	1	0	0
T3	2885	19	0	0
T4	425	2	0	0
T5	236	1	0	0
T6	431	2	0	0
T7	49612	541	0	0
T8	3674	27	0	0
T9	730	8	0	0
T10	17598	113	0	0

g_power_domains[0].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11932361	22435	0	0
T1	2503	20	0	0
T2	2084	10	0	0
T3	18035	59	0	0
T4	3164	6	0	0
T5	1801	1	0	0
T6	3350	2	0	0
T7	344981	541	0	0
T8	26007	102	0	0
T9	5082	8	0	0
T10	109102	322	0	0

g_power_domains[0].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11932361	22435	0	0
T1	2503	20	0	0
T2	2084	10	0	0
T3	18035	59	0	0
T4	3164	6	0	0
T5	1801	1	0	0
T6	3350	2	0	0
T7	344981	541	0	0
T8	26007	102	0	0
T9	5082	8	0	0
T10	109102	322	0	0

g_power_domains[0].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11932361	22435	0	0
T1	2503	20	0	0
T2	2084	10	0	0
T3	18035	59	0	0
T4	3164	6	0	0
T5	1801	1	0	0
T6	3350	2	0	0
T7	344981	541	0	0
T8	26007	102	0	0
T9	5082	8	0	0
T10	109102	322	0	0

g_power_domains[0].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11932361	22435	0	0
T1	2503	20	0	0
T2	2084	10	0	0
T3	18035	59	0	0
T4	3164	6	0	0
T5	1801	1	0	0
T6	3350	2	0	0
T7	344981	541	0	0
T8	26007	102	0	0
T9	5082	8	0	0
T10	109102	322	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13471045	22435	0	0
T1	3721	20	0	0
T2	2700	10	0	0
T3	22366	59	0	0
T4	3407	6	0	0
T5	1892	1	0	0
T6	3463	2	0	0
T7	394901	541	0	0
T8	29287	102	0	0
T9	5816	8	0	0
T10	137924	322	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13471045	22435	0	0
T1	3721	20	0	0
T2	2700	10	0	0
T3	22366	59	0	0
T4	3407	6	0	0
T5	1892	1	0	0
T6	3463	2	0	0
T7	394901	541	0	0
T8	29287	102	0	0
T9	5816	8	0	0
T10	137924	322	0	0

g_power_domains[1].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11932361	22435	0	0
T1	2503	20	0	0
T2	2084	10	0	0
T3	18035	59	0	0
T4	3164	6	0	0
T5	1801	1	0	0
T6	3350	2	0	0
T7	344981	541	0	0
T8	26007	102	0	0
T9	5082	8	0	0
T10	109102	322	0	0

g_power_domains[1].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11932361	22435	0	0
T1	2503	20	0	0
T2	2084	10	0	0
T3	18035	59	0	0
T4	3164	6	0	0
T5	1801	1	0	0
T6	3350	2	0	0
T7	344981	541	0	0
T8	26007	102	0	0
T9	5082	8	0	0
T10	109102	322	0	0

g_power_domains[1].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11932361	22435	0	0
T1	2503	20	0	0
T2	2084	10	0	0
T3	18035	59	0	0
T4	3164	6	0	0
T5	1801	1	0	0
T6	3350	2	0	0
T7	344981	541	0	0
T8	26007	102	0	0
T9	5082	8	0	0
T10	109102	322	0	0

g_power_domains[1].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11932361	22435	0	0
T1	2503	20	0	0
T2	2084	10	0	0
T3	18035	59	0	0
T4	3164	6	0	0
T5	1801	1	0	0
T6	3350	2	0	0
T7	344981	541	0	0
T8	26007	102	0	0
T9	5082	8	0	0
T10	109102	322	0	0