| | | | | | | |
tb.dut.u_lc_src.u_aon_rst.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_lc_src.u_aon_rst.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_lc_src.gen_rst_pd_n[0].u_pd_rst.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_lc_src.gen_rst_pd_n[0].u_pd_rst.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_sys_src.u_aon_rst.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_sys_src.u_aon_rst.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_sys_src.gen_rst_pd_n[0].u_pd_rst.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_sys_src.gen_rst_pd_n[0].u_pd_rst.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_daon_por.u_rst_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_daon_por.u_rst_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_daon_por.u_prim_mubi4_sender.gen_flops.u_prim_flop.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_daon_por.gen_rst_chk.u_prim_rst_sync.u_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_daon_por.gen_rst_chk.u_prim_rst_sync.u_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_daon_por_io.u_rst_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_daon_por_io.u_rst_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_daon_por_io.u_prim_mubi4_sender.gen_flops.u_prim_flop.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_daon_por_io.gen_rst_chk.u_prim_rst_sync.u_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_daon_por_io.gen_rst_chk.u_prim_rst_sync.u_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_daon_por_io_div2.u_rst_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_daon_por_io_div2.u_rst_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_daon_por_io_div2.u_prim_mubi4_sender.gen_flops.u_prim_flop.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_daon_por_io_div2.gen_rst_chk.u_prim_rst_sync.u_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_daon_por_io_div2.gen_rst_chk.u_prim_rst_sync.u_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_daon_por_io_div4.u_rst_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_daon_por_io_div4.u_rst_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_daon_por_io_div4.u_prim_mubi4_sender.gen_flops.u_prim_flop.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_daon_por_io_div4.gen_rst_chk.u_prim_rst_sync.u_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_daon_por_io_div4.gen_rst_chk.u_prim_rst_sync.u_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_daon_por_usb.u_rst_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_daon_por_usb.u_rst_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_daon_por_usb.u_prim_mubi4_sender.gen_flops.u_prim_flop.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_daon_por_usb.gen_rst_chk.u_prim_rst_sync.u_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_daon_por_usb.gen_rst_chk.u_prim_rst_sync.u_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_daon_lc.u_rst_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_daon_lc.u_rst_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_daon_lc.u_prim_mubi4_sender.gen_flops.u_prim_flop.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_daon_lc.gen_rst_chk.u_prim_rst_sync.u_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_daon_lc.gen_rst_chk.u_prim_rst_sync.u_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_d0_lc.u_rst_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_d0_lc.u_rst_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_d0_lc.u_prim_mubi4_sender.gen_flops.u_prim_flop.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_d0_lc.gen_rst_chk.u_prim_rst_sync.u_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_d0_lc.gen_rst_chk.u_prim_rst_sync.u_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_daon_lc_shadowed.u_rst_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_daon_lc_shadowed.u_rst_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_daon_lc_shadowed.u_prim_mubi4_sender.gen_flops.u_prim_flop.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_daon_lc_shadowed.gen_rst_chk.u_prim_rst_sync.u_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_daon_lc_shadowed.gen_rst_chk.u_prim_rst_sync.u_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_d0_lc_shadowed.u_rst_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_d0_lc_shadowed.u_rst_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_d0_lc_shadowed.u_prim_mubi4_sender.gen_flops.u_prim_flop.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_d0_lc_shadowed.gen_rst_chk.u_prim_rst_sync.u_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_d0_lc_shadowed.gen_rst_chk.u_prim_rst_sync.u_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_daon_lc_aon.u_rst_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_daon_lc_aon.u_rst_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_daon_lc_aon.u_prim_mubi4_sender.gen_flops.u_prim_flop.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_daon_lc_aon.gen_rst_chk.u_prim_rst_sync.u_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_daon_lc_aon.gen_rst_chk.u_prim_rst_sync.u_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_daon_lc_io.u_rst_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_daon_lc_io.u_rst_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_daon_lc_io.u_prim_mubi4_sender.gen_flops.u_prim_flop.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_daon_lc_io.gen_rst_chk.u_prim_rst_sync.u_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_daon_lc_io.gen_rst_chk.u_prim_rst_sync.u_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_d0_lc_io.u_rst_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_d0_lc_io.u_rst_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_d0_lc_io.u_prim_mubi4_sender.gen_flops.u_prim_flop.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_d0_lc_io.gen_rst_chk.u_prim_rst_sync.u_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_d0_lc_io.gen_rst_chk.u_prim_rst_sync.u_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_daon_lc_io_div2.u_rst_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_daon_lc_io_div2.u_rst_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_daon_lc_io_div2.u_prim_mubi4_sender.gen_flops.u_prim_flop.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_daon_lc_io_div2.gen_rst_chk.u_prim_rst_sync.u_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_daon_lc_io_div2.gen_rst_chk.u_prim_rst_sync.u_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_d0_lc_io_div2.u_rst_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_d0_lc_io_div2.u_rst_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_d0_lc_io_div2.u_prim_mubi4_sender.gen_flops.u_prim_flop.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_d0_lc_io_div2.gen_rst_chk.u_prim_rst_sync.u_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_d0_lc_io_div2.gen_rst_chk.u_prim_rst_sync.u_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_daon_lc_io_div4.u_rst_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_daon_lc_io_div4.u_rst_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_daon_lc_io_div4.u_prim_mubi4_sender.gen_flops.u_prim_flop.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_d0_lc_io_div4.u_rst_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_d0_lc_io_div4.u_rst_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_d0_lc_io_div4.u_prim_mubi4_sender.gen_flops.u_prim_flop.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_daon_lc_io_div4_shadowed.u_rst_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_daon_lc_io_div4_shadowed.u_rst_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_daon_lc_io_div4_shadowed.u_prim_mubi4_sender.gen_flops.u_prim_flop.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_d0_lc_io_div4_shadowed.u_rst_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_d0_lc_io_div4_shadowed.u_rst_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_d0_lc_io_div4_shadowed.u_prim_mubi4_sender.gen_flops.u_prim_flop.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_daon_lc_usb.u_rst_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_daon_lc_usb.u_rst_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_daon_lc_usb.u_prim_mubi4_sender.gen_flops.u_prim_flop.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_daon_lc_usb.gen_rst_chk.u_prim_rst_sync.u_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_daon_lc_usb.gen_rst_chk.u_prim_rst_sync.u_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_d0_lc_usb.u_rst_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_d0_lc_usb.u_rst_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_d0_lc_usb.u_prim_mubi4_sender.gen_flops.u_prim_flop.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_d0_lc_usb.gen_rst_chk.u_prim_rst_sync.u_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_d0_lc_usb.gen_rst_chk.u_prim_rst_sync.u_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_d0_sys.u_rst_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_d0_sys.u_rst_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_d0_sys.u_prim_mubi4_sender.gen_flops.u_prim_flop.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_d0_sys.gen_rst_chk.u_prim_rst_sync.u_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_d0_sys.gen_rst_chk.u_prim_rst_sync.u_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_daon_sys_io_div4.u_rst_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_daon_sys_io_div4.u_rst_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_daon_sys_io_div4.u_prim_mubi4_sender.gen_flops.u_prim_flop.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_daon_sys_io_div4.gen_rst_chk.u_prim_rst_sync.u_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_daon_sys_io_div4.gen_rst_chk.u_prim_rst_sync.u_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_d0_spi_device.u_rst_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_d0_spi_device.u_rst_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_d0_spi_device.u_prim_mubi4_sender.gen_flops.u_prim_flop.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_d0_spi_device.gen_rst_chk.u_prim_rst_sync.u_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_d0_spi_device.gen_rst_chk.u_prim_rst_sync.u_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_d0_spi_host0.u_rst_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_d0_spi_host0.u_rst_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_d0_spi_host0.u_prim_mubi4_sender.gen_flops.u_prim_flop.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_d0_spi_host0.gen_rst_chk.u_prim_rst_sync.u_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_d0_spi_host0.gen_rst_chk.u_prim_rst_sync.u_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_d0_spi_host1.u_rst_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_d0_spi_host1.u_rst_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_d0_spi_host1.u_prim_mubi4_sender.gen_flops.u_prim_flop.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_d0_spi_host1.gen_rst_chk.u_prim_rst_sync.u_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_d0_spi_host1.gen_rst_chk.u_prim_rst_sync.u_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_d0_usb.u_rst_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_d0_usb.u_rst_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_d0_usb.u_prim_mubi4_sender.gen_flops.u_prim_flop.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_d0_usb.gen_rst_chk.u_prim_rst_sync.u_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_d0_usb.gen_rst_chk.u_prim_rst_sync.u_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_d0_usb_aon.u_rst_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_d0_usb_aon.u_rst_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_d0_usb_aon.u_prim_mubi4_sender.gen_flops.u_prim_flop.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_d0_usb_aon.gen_rst_chk.u_prim_rst_sync.u_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_d0_usb_aon.gen_rst_chk.u_prim_rst_sync.u_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_d0_i2c0.u_rst_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_d0_i2c0.u_rst_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_d0_i2c0.u_prim_mubi4_sender.gen_flops.u_prim_flop.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_d0_i2c0.gen_rst_chk.u_prim_rst_sync.u_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_d0_i2c0.gen_rst_chk.u_prim_rst_sync.u_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_d0_i2c1.u_rst_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_d0_i2c1.u_rst_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_d0_i2c1.u_prim_mubi4_sender.gen_flops.u_prim_flop.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_d0_i2c1.gen_rst_chk.u_prim_rst_sync.u_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_d0_i2c1.gen_rst_chk.u_prim_rst_sync.u_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_d0_i2c2.u_rst_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_d0_i2c2.u_rst_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_d0_i2c2.u_prim_mubi4_sender.gen_flops.u_prim_flop.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_d0_i2c2.gen_rst_chk.u_prim_rst_sync.u_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.u_d0_i2c2.gen_rst_chk.u_prim_rst_sync.u_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_rst_por_aon.u_rst_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_rst_por_aon.u_rst_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_rst_por_aon.u_rst_flop.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_prim_mubi4_sender.gen_flops.u_prim_flop.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.gen_rst_por_aon[1].gen_rst_por_domain.u_por_domain_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.gen_rst_por_aon[1].gen_rst_por_domain.u_por_domain_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
tb.dut.gen_rst_por_aon[1].gen_rst_por_domain.u_prim_mubi4_sender.gen_flops.u_prim_flop.gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|