Unified Coverage Report :: Module :: rstmgr_sw_rst_sva_if

Module : rstmgr_sw_rst_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_sw_rst_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_sw_rst_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_sw_rst_sva_if

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
21	8	8

---

Cond Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Covered	Percent
Conditions	24	24	100.00
Logical	24	24	100.00
Non-Logical	0	0
Event	0	0

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[0])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T10
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[1])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T10
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[2])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T35,T39
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[3])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T35,T39
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[4])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T35,T39
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[5])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T35,T39
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[6])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T35,T39
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[7])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T35,T39
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions[0].RstEnOff_A	13471045	13882	0	0
gen_assertions[0].RstEnOn_A	13471045	981	0	0
gen_assertions[0].RstNOff_A	13471045	13882	0	0
gen_assertions[0].RstNOn_A	13471045	981	0	0
gen_assertions[1].RstEnOff_A	53883122	12591	0	0
gen_assertions[1].RstEnOn_A	53883122	893	0	0
gen_assertions[1].RstNOff_A	53883122	12591	0	0
gen_assertions[1].RstNOn_A	53883122	893	0	0
gen_assertions[2].RstEnOff_A	26942970	12637	0	0
gen_assertions[2].RstEnOn_A	26942970	912	0	0
gen_assertions[2].RstNOff_A	26942970	12637	0	0
gen_assertions[2].RstNOn_A	26942970	912	0	0
gen_assertions[3].RstEnOff_A	26943129	12702	0	0
gen_assertions[3].RstEnOn_A	26943129	974	0	0
gen_assertions[3].RstNOff_A	26943129	12702	0	0
gen_assertions[3].RstNOn_A	26943129	974	0	0
gen_assertions[4].RstEnOff_A	1700981	22112	0	0
gen_assertions[4].RstEnOn_A	1700981	1008	0	0
gen_assertions[4].RstNOff_A	1700981	22112	0	0
gen_assertions[4].RstNOn_A	1700981	1008	0	0
gen_assertions[5].RstEnOff_A	13471045	14110	0	0
gen_assertions[5].RstEnOn_A	13471045	1063	0	0
gen_assertions[5].RstNOff_A	13471045	14110	0	0
gen_assertions[5].RstNOn_A	13471045	1063	0	0
gen_assertions[6].RstEnOff_A	13471045	14172	0	0
gen_assertions[6].RstEnOn_A	13471045	1121	0	0
gen_assertions[6].RstNOff_A	13471045	14172	0	0
gen_assertions[6].RstNOn_A	13471045	1121	0	0
gen_assertions[7].RstEnOff_A	13471045	14193	0	0
gen_assertions[7].RstEnOn_A	13471045	1148	0	0
gen_assertions[7].RstNOff_A	13471045	14193	0	0
gen_assertions[7].RstNOn_A	13471045	1148	0	0

gen_assertions[0].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13471045	13882	0	0
T1	3721	19	0	0
T2	2700	9	0	0
T3	22366	40	0	0
T4	3407	4	0	0
T5	1892	0	0	0
T6	3463	0	0	0
T7	394901	0	0	0
T8	29287	75	0	0
T9	5816	0	0	0
T10	137924	247	0	0
T11	0	4	0	0
T12	0	75	0	0
T13	0	4	0	0
T35	0	5	0	0

gen_assertions[0].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13471045	981	0	0
T1	3721	6	0	0
T2	2700	2	0	0
T3	22366	0	0	0
T4	3407	0	0	0
T5	1892	0	0	0
T6	3463	0	0	0
T7	394901	0	0	0
T8	29287	0	0	0
T9	5816	0	0	0
T10	137924	41	0	0
T35	0	5	0	0
T39	0	8	0	0
T40	0	21	0	0
T55	0	6	0	0
T69	0	2	0	0
T70	0	2	0	0
T71	0	6	0	0

gen_assertions[0].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13471045	13882	0	0
T1	3721	19	0	0
T2	2700	9	0	0
T3	22366	40	0	0
T4	3407	4	0	0
T5	1892	0	0	0
T6	3463	0	0	0
T7	394901	0	0	0
T8	29287	75	0	0
T9	5816	0	0	0
T10	137924	247	0	0
T11	0	4	0	0
T12	0	75	0	0
T13	0	4	0	0
T35	0	5	0	0

gen_assertions[0].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13471045	981	0	0
T1	3721	6	0	0
T2	2700	2	0	0
T3	22366	0	0	0
T4	3407	0	0	0
T5	1892	0	0	0
T6	3463	0	0	0
T7	394901	0	0	0
T8	29287	0	0	0
T9	5816	0	0	0
T10	137924	41	0	0
T35	0	5	0	0
T39	0	8	0	0
T40	0	21	0	0
T55	0	6	0	0
T69	0	2	0	0
T70	0	2	0	0
T71	0	6	0	0

gen_assertions[1].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53883122	12591	0	0
T1	14889	19	0	0
T2	10802	6	0	0
T3	89455	38	0	0
T4	13628	3	0	0
T5	7571	0	0	0
T6	13859	0	0	0
T7	157980	0	0	0
T8	117057	68	0	0
T9	23281	0	0	0
T10	551630	219	0	0
T11	0	4	0	0
T12	0	63	0	0
T13	0	4	0	0
T35	0	7	0	0

gen_assertions[1].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53883122	893	0	0
T1	14889	4	0	0
T2	10802	1	0	0
T3	89455	0	0	0
T4	13628	0	0	0
T5	7571	0	0	0
T6	13859	0	0	0
T7	157980	0	0	0
T8	117057	0	0	0
T9	23281	0	0	0
T10	551630	39	0	0
T35	0	7	0	0
T39	0	4	0	0
T40	0	17	0	0
T55	0	5	0	0
T59	0	1	0	0
T70	0	2	0	0
T71	0	3	0	0

gen_assertions[1].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53883122	12591	0	0
T1	14889	19	0	0
T2	10802	6	0	0
T3	89455	38	0	0
T4	13628	3	0	0
T5	7571	0	0	0
T6	13859	0	0	0
T7	157980	0	0	0
T8	117057	68	0	0
T9	23281	0	0	0
T10	551630	219	0	0
T11	0	4	0	0
T12	0	63	0	0
T13	0	4	0	0
T35	0	7	0	0

gen_assertions[1].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53883122	893	0	0
T1	14889	4	0	0
T2	10802	1	0	0
T3	89455	0	0	0
T4	13628	0	0	0
T5	7571	0	0	0
T6	13859	0	0	0
T7	157980	0	0	0
T8	117057	0	0	0
T9	23281	0	0	0
T10	551630	39	0	0
T35	0	7	0	0
T39	0	4	0	0
T40	0	17	0	0
T55	0	5	0	0
T59	0	1	0	0
T70	0	2	0	0
T71	0	3	0	0

gen_assertions[2].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26942970	12637	0	0
T1	7443	19	0	0
T2	5401	6	0	0
T3	44726	38	0	0
T4	6815	3	0	0
T5	3785	0	0	0
T6	6930	0	0	0
T7	789912	0	0	0
T8	58559	68	0	0
T9	11637	0	0	0
T10	275843	216	0	0
T11	0	4	0	0
T12	0	63	0	0
T13	0	4	0	0
T35	0	8	0	0

gen_assertions[2].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26942970	912	0	0
T10	275843	36	0	0
T11	5117	0	0	0
T12	58585	0	0	0
T13	5130	0	0	0
T23	790728	0	0	0
T24	3172	0	0	0
T25	81399	0	0	0
T35	25221	8	0	0
T37	5167	0	0	0
T38	11634	0	0	0
T39	0	8	0	0
T40	0	14	0	0
T47	0	5	0	0
T52	0	9	0	0
T55	0	6	0	0
T70	0	2	0	0
T72	0	3	0	0
T73	0	13	0	0

gen_assertions[2].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26942970	12637	0	0
T1	7443	19	0	0
T2	5401	6	0	0
T3	44726	38	0	0
T4	6815	3	0	0
T5	3785	0	0	0
T6	6930	0	0	0
T7	789912	0	0	0
T8	58559	68	0	0
T9	11637	0	0	0
T10	275843	216	0	0
T11	0	4	0	0
T12	0	63	0	0
T13	0	4	0	0
T35	0	8	0	0

gen_assertions[2].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26942970	912	0	0
T10	275843	36	0	0
T11	5117	0	0	0
T12	58585	0	0	0
T13	5130	0	0	0
T23	790728	0	0	0
T24	3172	0	0	0
T25	81399	0	0	0
T35	25221	8	0	0
T37	5167	0	0	0
T38	11634	0	0	0
T39	0	8	0	0
T40	0	14	0	0
T47	0	5	0	0
T52	0	9	0	0
T55	0	6	0	0
T70	0	2	0	0
T72	0	3	0	0
T73	0	13	0	0

gen_assertions[3].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26943129	12702	0	0
T1	7443	19	0	0
T2	5401	6	0	0
T3	44733	38	0	0
T4	6816	3	0	0
T5	3785	0	0	0
T6	6930	0	0	0
T7	789873	0	0	0
T8	58569	68	0	0
T9	11642	0	0	0
T10	275852	219	0	0
T11	0	4	0	0
T12	0	63	0	0
T13	0	4	0	0
T35	0	10	0	0

gen_assertions[3].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26943129	974	0	0
T10	275852	41	0	0
T11	5116	0	0	0
T12	58614	0	0	0
T13	5129	0	0	0
T23	790749	0	0	0
T24	3172	0	0	0
T25	81402	0	0	0
T35	25221	10	0	0
T37	5167	0	0	0
T38	11635	0	0	0
T39	0	5	0	0
T40	0	15	0	0
T47	0	5	0	0
T52	0	6	0	0
T55	0	9	0	0
T59	0	1	0	0
T70	0	2	0	0
T72	0	4	0	0

gen_assertions[3].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26943129	12702	0	0
T1	7443	19	0	0
T2	5401	6	0	0
T3	44733	38	0	0
T4	6816	3	0	0
T5	3785	0	0	0
T6	6930	0	0	0
T7	789873	0	0	0
T8	58569	68	0	0
T9	11642	0	0	0
T10	275852	219	0	0
T11	0	4	0	0
T12	0	63	0	0
T13	0	4	0	0
T35	0	10	0	0

gen_assertions[3].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26943129	974	0	0
T10	275852	41	0	0
T11	5116	0	0	0
T12	58614	0	0	0
T13	5129	0	0	0
T23	790749	0	0	0
T24	3172	0	0	0
T25	81402	0	0	0
T35	25221	10	0	0
T37	5167	0	0	0
T38	11635	0	0	0
T39	0	5	0	0
T40	0	15	0	0
T47	0	5	0	0
T52	0	6	0	0
T55	0	9	0	0
T59	0	1	0	0
T70	0	2	0	0
T72	0	4	0	0

gen_assertions[4].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1700981	22112	0	0
T1	464	20	0	0
T2	337	9	0	0
T3	2885	59	0	0
T4	425	4	0	0
T5	236	1	0	0
T6	431	2	0	0
T7	49612	541	0	0
T8	3674	76	0	0
T9	730	3	0	0
T10	17598	355	0	0

gen_assertions[4].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1700981	1008	0	0
T10	17598	38	0	0
T11	318	0	0	0
T12	3676	0	0	0
T13	319	0	0	0
T23	49665	0	0	0
T24	198	0	0	0
T25	5177	0	0	0
T35	1575	11	0	0
T37	322	0	0	0
T38	728	0	0	0
T39	0	7	0	0
T40	0	17	0	0
T47	0	7	0	0
T52	0	11	0	0
T55	0	12	0	0
T70	0	3	0	0
T72	0	6	0	0
T74	0	1	0	0

gen_assertions[4].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1700981	22112	0	0
T1	464	20	0	0
T2	337	9	0	0
T3	2885	59	0	0
T4	425	4	0	0
T5	236	1	0	0
T6	431	2	0	0
T7	49612	541	0	0
T8	3674	76	0	0
T9	730	3	0	0
T10	17598	355	0	0

gen_assertions[4].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1700981	1008	0	0
T10	17598	38	0	0
T11	318	0	0	0
T12	3676	0	0	0
T13	319	0	0	0
T23	49665	0	0	0
T24	198	0	0	0
T25	5177	0	0	0
T35	1575	11	0	0
T37	322	0	0	0
T38	728	0	0	0
T39	0	7	0	0
T40	0	17	0	0
T47	0	7	0	0
T52	0	11	0	0
T55	0	12	0	0
T70	0	3	0	0
T72	0	6	0	0
T74	0	1	0	0

gen_assertions[5].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13471045	14110	0	0
T1	3721	19	0	0
T2	2700	9	0	0
T3	22366	40	0	0
T4	3407	4	0	0
T5	1892	0	0	0
T6	3463	0	0	0
T7	394901	0	0	0
T8	29287	75	0	0
T9	5816	0	0	0
T10	137924	242	0	0
T11	0	4	0	0
T12	0	75	0	0
T13	0	4	0	0
T35	0	14	0	0

gen_assertions[5].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13471045	1063	0	0
T10	137924	35	0	0
T11	2558	0	0	0
T12	29300	0	0	0
T13	2564	0	0	0
T23	395318	0	0	0
T24	1584	0	0	0
T25	40705	0	0	0
T35	12609	14	0	0
T37	2582	0	0	0
T38	5815	0	0	0
T39	0	5	0	0
T40	0	19	0	0
T47	0	6	0	0
T49	0	1	0	0
T52	0	12	0	0
T55	0	9	0	0
T70	0	2	0	0
T72	0	6	0	0

gen_assertions[5].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13471045	14110	0	0
T1	3721	19	0	0
T2	2700	9	0	0
T3	22366	40	0	0
T4	3407	4	0	0
T5	1892	0	0	0
T6	3463	0	0	0
T7	394901	0	0	0
T8	29287	75	0	0
T9	5816	0	0	0
T10	137924	242	0	0
T11	0	4	0	0
T12	0	75	0	0
T13	0	4	0	0
T35	0	14	0	0

gen_assertions[5].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13471045	1063	0	0
T10	137924	35	0	0
T11	2558	0	0	0
T12	29300	0	0	0
T13	2564	0	0	0
T23	395318	0	0	0
T24	1584	0	0	0
T25	40705	0	0	0
T35	12609	14	0	0
T37	2582	0	0	0
T38	5815	0	0	0
T39	0	5	0	0
T40	0	19	0	0
T47	0	6	0	0
T49	0	1	0	0
T52	0	12	0	0
T55	0	9	0	0
T70	0	2	0	0
T72	0	6	0	0

gen_assertions[6].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13471045	14172	0	0
T1	3721	19	0	0
T2	2700	9	0	0
T3	22366	40	0	0
T4	3407	4	0	0
T5	1892	0	0	0
T6	3463	0	0	0
T7	394901	0	0	0
T8	29287	75	0	0
T9	5816	0	0	0
T10	137924	243	0	0
T11	0	4	0	0
T12	0	75	0	0
T13	0	4	0	0
T35	0	12	0	0

gen_assertions[6].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13471045	1121	0	0
T10	137924	35	0	0
T11	2558	0	0	0
T12	29300	0	0	0
T13	2564	0	0	0
T23	395318	0	0	0
T24	1584	0	0	0
T25	40705	0	0	0
T35	12609	12	0	0
T37	2582	0	0	0
T38	5815	0	0	0
T39	0	5	0	0
T40	0	18	0	0
T47	0	9	0	0
T49	0	1	0	0
T52	0	12	0	0
T54	0	1	0	0
T55	0	11	0	0
T70	0	2	0	0

gen_assertions[6].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13471045	14172	0	0
T1	3721	19	0	0
T2	2700	9	0	0
T3	22366	40	0	0
T4	3407	4	0	0
T5	1892	0	0	0
T6	3463	0	0	0
T7	394901	0	0	0
T8	29287	75	0	0
T9	5816	0	0	0
T10	137924	243	0	0
T11	0	4	0	0
T12	0	75	0	0
T13	0	4	0	0
T35	0	12	0	0

gen_assertions[6].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13471045	1121	0	0
T10	137924	35	0	0
T11	2558	0	0	0
T12	29300	0	0	0
T13	2564	0	0	0
T23	395318	0	0	0
T24	1584	0	0	0
T25	40705	0	0	0
T35	12609	12	0	0
T37	2582	0	0	0
T38	5815	0	0	0
T39	0	5	0	0
T40	0	18	0	0
T47	0	9	0	0
T49	0	1	0	0
T52	0	12	0	0
T54	0	1	0	0
T55	0	11	0	0
T70	0	2	0	0

gen_assertions[7].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13471045	14193	0	0
T1	3721	19	0	0
T2	2700	9	0	0
T3	22366	40	0	0
T4	3407	4	0	0
T5	1892	0	0	0
T6	3463	0	0	0
T7	394901	0	0	0
T8	29287	75	0	0
T9	5816	0	0	0
T10	137924	244	0	0
T11	0	4	0	0
T12	0	75	0	0
T13	0	4	0	0
T35	0	13	0	0

gen_assertions[7].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13471045	1148	0	0
T10	137924	36	0	0
T11	2558	0	0	0
T12	29300	0	0	0
T13	2564	0	0	0
T23	395318	0	0	0
T24	1584	0	0	0
T25	40705	0	0	0
T35	12609	13	0	0
T37	2582	0	0	0
T38	5815	0	0	0
T39	0	6	0	0
T40	0	15	0	0
T47	0	8	0	0
T49	0	1	0	0
T52	0	15	0	0
T55	0	12	0	0
T70	0	2	0	0
T72	0	8	0	0

gen_assertions[7].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13471045	14193	0	0
T1	3721	19	0	0
T2	2700	9	0	0
T3	22366	40	0	0
T4	3407	4	0	0
T5	1892	0	0	0
T6	3463	0	0	0
T7	394901	0	0	0
T8	29287	75	0	0
T9	5816	0	0	0
T10	137924	244	0	0
T11	0	4	0	0
T12	0	75	0	0
T13	0	4	0	0
T35	0	13	0	0

gen_assertions[7].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13471045	1148	0	0
T10	137924	36	0	0
T11	2558	0	0	0
T12	29300	0	0	0
T13	2564	0	0	0
T23	395318	0	0	0
T24	1584	0	0	0
T25	40705	0	0	0
T35	12609	13	0	0
T37	2582	0	0	0
T38	5815	0	0	0
T39	0	6	0	0
T40	0	15	0	0
T47	0	8	0	0
T49	0	1	0	0
T52	0	15	0	0
T55	0	12	0	0
T70	0	2	0	0
T72	0	8	0	0