Unified Coverage Report :: Module :: rstmgr_csr_assert_fpv

Module : rstmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rstmgr_csr_assert_0/rstmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rstmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rstmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	19	19	100.00	19	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	19	19	100.00	19	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	12741584	8049	0	0
alert_regwen_rd_A	12741584	5829	0	0
cpu_regwen_rd_A	12741584	5951	0	0
sw_rst_ctrl_n_0_rd_A	12741584	11466	0	0
sw_rst_ctrl_n_1_rd_A	12741584	11272	0	0
sw_rst_ctrl_n_2_rd_A	12741584	11402	0	0
sw_rst_ctrl_n_3_rd_A	12741584	11265	0	0
sw_rst_ctrl_n_4_rd_A	12741584	11425	0	0
sw_rst_ctrl_n_5_rd_A	12741584	11648	0	0
sw_rst_ctrl_n_6_rd_A	12741584	11601	0	0
sw_rst_ctrl_n_7_rd_A	12741584	11035	0	0
sw_rst_regwen_0_rd_A	12741584	6563	0	0
sw_rst_regwen_1_rd_A	12741584	6627	0	0
sw_rst_regwen_2_rd_A	12741584	6706	0	0
sw_rst_regwen_3_rd_A	12741584	6417	0	0
sw_rst_regwen_4_rd_A	12741584	6657	0	0
sw_rst_regwen_5_rd_A	12741584	6422	0	0
sw_rst_regwen_6_rd_A	12741584	6471	0	0
sw_rst_regwen_7_rd_A	12741584	6566	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12741584	8049	0	0
T57	9028	1	0	0
T58	11426	1	0	0
T60	4740	12	0	0
T61	2781	14	0	0
T62	4907	28	0	0
T63	17286	2	0	0
T64	11478	1	0	0
T75	4522	199	0	0
T76	4478	18	0	0
T77	17953	4	0	0

alert_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12741584	5829	0	0
T15	4699	0	0	0
T26	26103	0	0	0
T65	1528	0	0	0
T71	1947	0	0	0
T81	33670	47	0	0
T82	16315	0	0	0
T83	26723	0	0	0
T85	0	28	0	0
T88	0	124	0	0
T89	0	288	0	0
T90	0	72	0	0
T117	0	53	0	0
T118	0	43	0	0
T119	0	386	0	0
T120	0	73	0	0
T121	0	169	0	0
T122	5471	0	0	0
T123	2027	0	0	0
T124	5289	0	0	0

cpu_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12741584	5951	0	0
T15	4699	0	0	0
T26	26103	0	0	0
T65	1528	0	0	0
T71	1947	0	0	0
T81	33670	44	0	0
T82	16315	0	0	0
T83	26723	0	0	0
T85	0	81	0	0
T88	0	146	0	0
T89	0	233	0	0
T90	0	74	0	0
T117	0	69	0	0
T118	0	47	0	0
T119	0	387	0	0
T120	0	45	0	0
T121	0	215	0	0
T122	5471	0	0	0
T123	2027	0	0	0
T124	5289	0	0	0

sw_rst_ctrl_n_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12741584	11466	0	0
T13	2243	15	0	0
T25	35652	0	0	0
T35	12519	206	0	0
T37	2436	0	0	0
T38	5271	0	0	0
T39	6554	85	0	0
T40	164135	0	0	0
T41	29508	0	0	0
T42	4151	0	0	0
T47	0	135	0	0
T49	0	13	0	0
T54	4662	0	0	0
T59	0	9	0	0
T69	0	45	0	0
T74	0	20	0	0
T81	0	42	0	0
T85	0	50	0	0

sw_rst_ctrl_n_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12741584	11272	0	0
T13	2243	19	0	0
T25	35652	0	0	0
T35	12519	200	0	0
T37	2436	0	0	0
T38	5271	0	0	0
T39	6554	98	0	0
T40	164135	0	0	0
T41	29508	0	0	0
T42	4151	0	0	0
T47	0	123	0	0
T49	0	9	0	0
T54	4662	0	0	0
T59	0	6	0	0
T69	0	40	0	0
T74	0	21	0	0
T81	0	53	0	0
T85	0	51	0	0

sw_rst_ctrl_n_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12741584	11402	0	0
T13	2243	18	0	0
T25	35652	0	0	0
T35	12519	220	0	0
T37	2436	0	0	0
T38	5271	0	0	0
T39	6554	99	0	0
T40	164135	0	0	0
T41	29508	0	0	0
T42	4151	0	0	0
T47	0	141	0	0
T49	0	19	0	0
T54	4662	0	0	0
T59	0	12	0	0
T69	0	27	0	0
T74	0	16	0	0
T81	0	47	0	0
T85	0	56	0	0

sw_rst_ctrl_n_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12741584	11265	0	0
T13	2243	19	0	0
T25	35652	0	0	0
T35	12519	175	0	0
T37	2436	0	0	0
T38	5271	0	0	0
T39	6554	102	0	0
T40	164135	0	0	0
T41	29508	0	0	0
T42	4151	0	0	0
T47	0	142	0	0
T49	0	11	0	0
T54	4662	0	0	0
T59	0	11	0	0
T69	0	48	0	0
T74	0	18	0	0
T81	0	29	0	0
T85	0	39	0	0

sw_rst_ctrl_n_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12741584	11425	0	0
T13	2243	16	0	0
T25	35652	0	0	0
T35	12519	190	0	0
T37	2436	0	0	0
T38	5271	0	0	0
T39	6554	87	0	0
T40	164135	0	0	0
T41	29508	0	0	0
T42	4151	0	0	0
T47	0	194	0	0
T49	0	16	0	0
T54	4662	0	0	0
T59	0	17	0	0
T69	0	46	0	0
T74	0	15	0	0
T81	0	34	0	0
T85	0	39	0	0

sw_rst_ctrl_n_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12741584	11648	0	0
T13	2243	8	0	0
T25	35652	0	0	0
T35	12519	230	0	0
T37	2436	0	0	0
T38	5271	0	0	0
T39	6554	75	0	0
T40	164135	0	0	0
T41	29508	0	0	0
T42	4151	0	0	0
T47	0	134	0	0
T49	0	17	0	0
T54	4662	0	0	0
T59	0	19	0	0
T69	0	14	0	0
T74	0	7	0	0
T81	0	51	0	0
T85	0	34	0	0

sw_rst_ctrl_n_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12741584	11601	0	0
T13	2243	16	0	0
T25	35652	0	0	0
T35	12519	194	0	0
T37	2436	0	0	0
T38	5271	0	0	0
T39	6554	100	0	0
T40	164135	0	0	0
T41	29508	0	0	0
T42	4151	0	0	0
T47	0	150	0	0
T49	0	6	0	0
T54	4662	0	0	0
T59	0	17	0	0
T69	0	36	0	0
T74	0	8	0	0
T81	0	51	0	0
T85	0	35	0	0

sw_rst_ctrl_n_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12741584	11035	0	0
T13	2243	9	0	0
T25	35652	0	0	0
T35	12519	244	0	0
T37	2436	0	0	0
T38	5271	0	0	0
T39	6554	77	0	0
T40	164135	0	0	0
T41	29508	0	0	0
T42	4151	0	0	0
T47	0	114	0	0
T49	0	11	0	0
T54	4662	0	0	0
T59	0	16	0	0
T69	0	44	0	0
T74	0	11	0	0
T81	0	36	0	0
T85	0	25	0	0

sw_rst_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12741584	6563	0	0
T25	35652	0	0	0
T35	12519	19	0	0
T37	2436	0	0	0
T38	5271	0	0	0
T39	6554	0	0	0
T40	164135	0	0	0
T41	29508	0	0	0
T42	4151	0	0	0
T47	0	20	0	0
T49	0	3	0	0
T54	4662	0	0	0
T59	0	5	0	0
T69	3542	0	0	0
T74	0	8	0	0
T81	0	55	0	0
T85	0	26	0	0
T88	0	113	0	0
T117	0	83	0	0
T125	0	2	0	0

sw_rst_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12741584	6627	0	0
T25	35652	0	0	0
T35	12519	27	0	0
T37	2436	0	0	0
T38	5271	0	0	0
T39	6554	0	0	0
T40	164135	0	0	0
T41	29508	0	0	0
T42	4151	0	0	0
T47	0	24	0	0
T49	0	4	0	0
T54	4662	0	0	0
T59	0	4	0	0
T69	3542	0	0	0
T74	0	6	0	0
T81	0	66	0	0
T85	0	67	0	0
T88	0	135	0	0
T117	0	75	0	0
T125	0	3	0	0

sw_rst_regwen_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12741584	6706	0	0
T25	35652	0	0	0
T35	12519	42	0	0
T37	2436	0	0	0
T38	5271	0	0	0
T39	6554	0	0	0
T40	164135	0	0	0
T41	29508	0	0	0
T42	4151	0	0	0
T47	0	19	0	0
T49	0	7	0	0
T54	4662	0	0	0
T59	0	10	0	0
T69	3542	0	0	0
T74	0	14	0	0
T81	0	40	0	0
T85	0	32	0	0
T88	0	109	0	0
T89	0	248	0	0
T117	0	77	0	0

sw_rst_regwen_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12741584	6417	0	0
T25	35652	0	0	0
T35	12519	26	0	0
T37	2436	0	0	0
T38	5271	0	0	0
T39	6554	0	0	0
T40	164135	0	0	0
T41	29508	0	0	0
T42	4151	0	0	0
T47	0	27	0	0
T49	0	2	0	0
T54	4662	0	0	0
T59	0	9	0	0
T69	3542	0	0	0
T74	0	5	0	0
T81	0	41	0	0
T85	0	57	0	0
T88	0	111	0	0
T89	0	223	0	0
T117	0	53	0	0

sw_rst_regwen_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12741584	6657	0	0
T25	35652	0	0	0
T35	12519	35	0	0
T37	2436	0	0	0
T38	5271	0	0	0
T39	6554	0	0	0
T40	164135	0	0	0
T41	29508	0	0	0
T42	4151	0	0	0
T47	0	28	0	0
T49	0	9	0	0
T54	4662	0	0	0
T59	0	14	0	0
T69	3542	0	0	0
T74	0	16	0	0
T81	0	41	0	0
T85	0	34	0	0
T88	0	101	0	0
T89	0	253	0	0
T117	0	85	0	0

sw_rst_regwen_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12741584	6422	0	0
T25	35652	0	0	0
T35	12519	32	0	0
T37	2436	0	0	0
T38	5271	0	0	0
T39	6554	0	0	0
T40	164135	0	0	0
T41	29508	0	0	0
T42	4151	0	0	0
T47	0	29	0	0
T49	0	9	0	0
T54	4662	0	0	0
T59	0	4	0	0
T69	3542	0	0	0
T74	0	6	0	0
T81	0	44	0	0
T85	0	46	0	0
T88	0	123	0	0
T117	0	70	0	0
T125	0	6	0	0

sw_rst_regwen_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12741584	6471	0	0
T25	35652	0	0	0
T35	12519	38	0	0
T37	2436	0	0	0
T38	5271	0	0	0
T39	6554	0	0	0
T40	164135	0	0	0
T41	29508	0	0	0
T42	4151	0	0	0
T47	0	26	0	0
T49	0	5	0	0
T54	4662	0	0	0
T59	0	11	0	0
T69	3542	0	0	0
T74	0	6	0	0
T81	0	38	0	0
T85	0	44	0	0
T88	0	121	0	0
T117	0	66	0	0
T125	0	2	0	0

sw_rst_regwen_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12741584	6566	0	0
T25	35652	0	0	0
T35	12519	26	0	0
T37	2436	0	0	0
T38	5271	0	0	0
T39	6554	0	0	0
T40	164135	0	0	0
T41	29508	0	0	0
T42	4151	0	0	0
T47	0	39	0	0
T49	0	1	0	0
T54	4662	0	0	0
T59	0	6	0	0
T69	3542	0	0	0
T74	0	2	0	0
T81	0	46	0	0
T85	0	30	0	0
T88	0	128	0	0
T89	0	256	0	0
T117	0	62	0	0