Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	627297	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

374960

1

T1

392

T2

1111

T3

120

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	536247	1			T1	571		T2	1500		T3	186
values[0x0]	232543	1			T1	272		T2	857		T3	94
values[0x1]	233467	1			T1	253		T2	843		T3	99

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	526767	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

475490

1

T1

471

T2

1474

T3

160

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	3305	1			T1	8		T2	9		T4	4
valid_sources[0x01]	3827	1			T1	5		T2	17		T4	3
valid_sources[0x02]	4799	1			T1	2		T2	8		T7	65
valid_sources[0x03]	3277	1			T1	1		T2	15		T7	29
valid_sources[0x04]	3980	1			T1	5		T2	18		T7	49
valid_sources[0x05]	3030	1			T1	10		T2	13		T7	49
valid_sources[0x06]	3810	1			T1	2		T2	10		T4	3
valid_sources[0x07]	3368	1			T1	10		T2	13		T7	45
valid_sources[0x08]	4039	1			T1	7		T2	8		T4	4
valid_sources[0x09]	3395	1			T1	7		T2	13		T4	1
valid_sources[0x0a]	3980	1			T1	10		T2	15		T7	32
valid_sources[0x0b]	6656	1			T2	13		T7	32		T10	10
valid_sources[0x0c]	3215	1			T1	4		T2	18		T4	3
valid_sources[0x0d]	5453	1			T2	12		T4	3		T7	52
valid_sources[0x0e]	5018	1			T1	3		T2	20		T4	1
valid_sources[0x0f]	4353	1			T1	8		T2	8		T4	1
valid_sources[0x10]	4442	1			T2	22		T7	54		T10	11
valid_sources[0x11]	2910	1			T1	11		T2	4		T4	2
valid_sources[0x12]	4224	1			T1	6		T2	11		T4	2
valid_sources[0x13]	4765	1			T2	18		T4	2		T7	31
valid_sources[0x14]	3251	1			T2	7		T7	49		T10	4
valid_sources[0x15]	3922	1			T2	18		T7	51		T10	11
valid_sources[0x16]	3281	1			T2	18		T7	37		T10	15
valid_sources[0x17]	4663	1			T1	4		T2	10		T7	59
valid_sources[0x18]	3349	1			T1	1		T2	13		T4	3
valid_sources[0x19]	4288	1			T1	3		T2	2		T7	49
valid_sources[0x1a]	3195	1			T1	8		T2	10		T7	35
valid_sources[0x1b]	3861	1			T1	7		T2	13		T4	1
valid_sources[0x1c]	3895	1			T1	2		T2	14		T7	30
valid_sources[0x1d]	3673	1			T1	7		T2	7		T4	5
valid_sources[0x1e]	3638	1			T2	12		T7	28		T9	4
valid_sources[0x1f]	3622	1			T1	1		T2	22		T7	42
valid_sources[0x20]	3525	1			T1	2		T2	15		T4	5
valid_sources[0x21]	2914	1			T1	2		T2	14		T4	1
valid_sources[0x22]	3424	1			T1	2		T2	9		T7	35
valid_sources[0x23]	4200	1			T1	3		T2	13		T4	1
valid_sources[0x24]	4092	1			T1	15		T2	14		T4	1
valid_sources[0x25]	3423	1			T2	14		T4	2		T7	48
valid_sources[0x26]	3125	1			T1	6		T2	9		T7	28
valid_sources[0x27]	3893	1			T1	1		T2	17		T4	1
valid_sources[0x28]	3056	1			T2	21		T4	2		T7	20
valid_sources[0x29]	3340	1			T1	1		T2	11		T4	5
valid_sources[0x2a]	3390	1			T1	2		T2	16		T4	2
valid_sources[0x2b]	2990	1			T1	15		T2	14		T4	1
valid_sources[0x2c]	4272	1			T1	13		T2	14		T7	36
valid_sources[0x2d]	3601	1			T1	2		T2	18		T4	3
valid_sources[0x2e]	5041	1			T1	3		T2	11		T7	28
valid_sources[0x2f]	2981	1			T1	5		T2	21		T4	1
valid_sources[0x30]	5221	1			T1	8		T2	12		T4	3
valid_sources[0x31]	3893	1			T1	16		T2	8		T4	1
valid_sources[0x32]	3985	1			T1	7		T2	17		T4	1
valid_sources[0x33]	3497	1			T1	1		T2	12		T4	2
valid_sources[0x34]	3256	1			T1	6		T2	9		T4	2
valid_sources[0x35]	3731	1			T1	14		T2	11		T7	30
valid_sources[0x36]	3181	1			T2	10		T4	3		T7	28
valid_sources[0x37]	3072	1			T1	5		T2	16		T4	1
valid_sources[0x38]	4507	1			T1	4		T2	11		T4	1
valid_sources[0x39]	4495	1			T1	7		T2	22		T4	5
valid_sources[0x3a]	4859	1			T1	15		T2	6		T4	1
valid_sources[0x3b]	3148	1			T1	8		T2	13		T4	2
valid_sources[0x3c]	3473	1			T1	6		T2	4		T7	33
valid_sources[0x3d]	3968	1			T1	3		T2	12		T4	1
valid_sources[0x3e]	3633	1			T1	3		T2	17		T4	1
valid_sources[0x3f]	3641	1			T1	5		T2	11		T4	3
valid_sources[0x40]	3578	1			T1	1		T2	13		T4	3
valid_sources[0x41]	2986	1			T1	2		T2	13		T4	4
valid_sources[0x42]	3645	1			T1	4		T2	21		T7	35
valid_sources[0x43]	3493	1			T1	1		T2	17		T4	1
valid_sources[0x44]	3584	1			T1	5		T2	6		T4	1
valid_sources[0x45]	4090	1			T2	15		T4	2		T7	50
valid_sources[0x46]	3441	1			T2	13		T4	1		T7	23
valid_sources[0x47]	3561	1			T1	8		T2	9		T4	1
valid_sources[0x48]	3282	1			T1	1		T2	9		T4	2
valid_sources[0x49]	3815	1			T1	2		T2	8		T4	1
valid_sources[0x4a]	2762	1			T1	12		T2	10		T7	34
valid_sources[0x4b]	3530	1			T1	1		T2	8		T4	1
valid_sources[0x4c]	3164	1			T1	6		T2	17		T4	1
valid_sources[0x4d]	3788	1			T1	4		T2	18		T4	2
valid_sources[0x4e]	4625	1			T2	19		T4	2		T7	36
valid_sources[0x4f]	3771	1			T1	1		T2	11		T4	3
valid_sources[0x50]	6133	1			T1	4		T2	11		T4	3
valid_sources[0x51]	3488	1			T1	6		T2	14		T4	1
valid_sources[0x52]	3277	1			T1	13		T2	19		T4	2
valid_sources[0x53]	3469	1			T1	9		T2	12		T7	42
valid_sources[0x54]	3189	1			T1	3		T2	16		T6	1
valid_sources[0x55]	3931	1			T1	4		T2	12		T4	1
valid_sources[0x56]	3763	1			T2	9		T4	5		T7	40
valid_sources[0x57]	4132	1			T1	4		T2	18		T4	1
valid_sources[0x58]	3895	1			T2	14		T4	2		T7	57
valid_sources[0x59]	3558	1			T1	9		T2	6		T4	1
valid_sources[0x5a]	4097	1			T1	7		T2	10		T4	1
valid_sources[0x5b]	4380	1			T1	6		T2	3		T4	5
valid_sources[0x5c]	4185	1			T2	20		T4	2		T7	51
valid_sources[0x5d]	3908	1			T1	4		T2	12		T4	5
valid_sources[0x5e]	3914	1			T2	9		T7	41		T9	1
valid_sources[0x5f]	4588	1			T1	5		T2	11		T4	3
valid_sources[0x60]	3281	1			T1	4		T2	11		T4	5
valid_sources[0x61]	3489	1			T1	2		T2	16		T4	2
valid_sources[0x62]	3749	1			T1	1		T2	12		T7	46
valid_sources[0x63]	3571	1			T1	14		T2	12		T4	1
valid_sources[0x64]	4179	1			T1	7		T2	12		T7	42
valid_sources[0x65]	3063	1			T1	3		T2	5		T4	1
valid_sources[0x66]	3436	1			T1	2		T2	9		T7	46
valid_sources[0x67]	3038	1			T1	6		T2	17		T7	39
valid_sources[0x68]	3049	1			T1	12		T2	20		T4	2
valid_sources[0x69]	3246	1			T2	9		T7	48		T9	1
valid_sources[0x6a]	3500	1			T1	1		T2	8		T4	1
valid_sources[0x6b]	3685	1			T1	3		T2	8		T4	4
valid_sources[0x6c]	4421	1			T1	3		T2	9		T4	1
valid_sources[0x6d]	7357	1			T1	7		T2	16		T4	1
valid_sources[0x6e]	3156	1			T2	10		T4	3		T7	61
valid_sources[0x6f]	3551	1			T1	8		T2	15		T4	2
valid_sources[0x70]	3152	1			T1	6		T2	9		T4	9
valid_sources[0x71]	2866	1			T1	8		T2	14		T4	1
valid_sources[0x72]	3590	1			T1	14		T2	15		T7	33
valid_sources[0x73]	3735	1			T1	10		T2	13		T7	55
valid_sources[0x74]	3838	1			T1	1		T2	21		T7	36
valid_sources[0x75]	3773	1			T1	4		T2	11		T4	1
valid_sources[0x76]	3698	1			T1	10		T2	14		T4	3
valid_sources[0x77]	4014	1			T1	8		T2	11		T7	26
valid_sources[0x78]	6181	1			T1	4		T2	9		T4	1
valid_sources[0x79]	3736	1			T1	2		T2	11		T7	43
valid_sources[0x7a]	6679	1			T1	6		T2	12		T7	44
valid_sources[0x7b]	3959	1			T1	2		T2	8		T4	2
valid_sources[0x7c]	5041	1			T2	6		T7	38		T9	3
valid_sources[0x7d]	3944	1			T2	10		T7	58		T10	13
valid_sources[0x7e]	4188	1			T1	11		T2	16		T4	2
valid_sources[0x7f]	7589	1			T1	1		T2	10		T4	7
valid_sources[0x80]	3094	1			T1	1		T2	7		T4	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

251523

1

T1

268

T2

664

T3

73

values[0x0]

all_enables

biggest_size

80698

1

T1

86

T2

304

T3

30

values[0x1]

all_enables

biggest_size

42739

1

T1

38

T2

143

T3

17