Unified Coverage Report :: Module :: rstmgr_cascading_sva_if

Module : rstmgr_cascading_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_cascading_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_cascading_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_cascading_sva_if

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	100	1	1	100.00
ALWAYS	103	1	1	100.00
ALWAYS	107	1	1	100.00
ALWAYS	127	1	1	100.00
ALWAYS	138	1	1	100.00
ALWAYS	141	1	1	100.00
ALWAYS	144	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
100	1	1
103	1	1
107	1	1
127	1	1
138	1	1
141	1	1
144	1	1

---

Cond Coverage for Module : rstmgr_cascading_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       103
 EXPRESSION (((!scanmode)) || scan_rst_ni)
             ------1------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T3,T4,T5
0	1	Covered	T3,T4,T7
1	0	Covered	T7,T10,T22

 LINE       107
 EXPRESSION (por_n_i[rstmgr_pkg::DomainAonSel] && ((!scanmode)))
             ----------------1----------------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T2,T6,T7
1	0	Covered	T3,T4,T5
1	1	Covered	T1,T2,T3

---

Assert Coverage for Module : rstmgr_cascading_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	31	31	100.00	31	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	31	31	100.00	31	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CascadeEffAonToRstPorAboveFall_A	55541352	8696	0	0
CascadeEffAonToRstPorAboveRise_A	55541352	8696	0	0
CascadeEffAonToRstPorIoAboveFall_A	53317754	8696	0	0
CascadeEffAonToRstPorIoAboveRise_A	53317754	8696	0	0
CascadeEffAonToRstPorIoDiv2AboveFall_A	26659536	8696	0	0
CascadeEffAonToRstPorIoDiv2AboveRise_A	26659536	8696	0	0
CascadeEffAonToRstPorIoDiv4AboveFall_A	13329756	8696	0	0
CascadeEffAonToRstPorIoDiv4AboveRise_A	13329756	8696	0	0
CascadeEffAonToRstPorUcbAboveFall_A	26659681	8696	0	0
CascadeEffAonToRstPorUcbAboveRise_A	26659681	8696	0	0
CascadeLcToLcAboveFall_A	55541352	22000	0	0
CascadeLcToLcAboveRise_A	55541352	22000	0	0
CascadeLcToLcAonAboveFall_A	1683086	22000	0	0
CascadeLcToLcAonAboveRise_A	1683086	22000	0	0
CascadeLcToLcShadowedAboveFall_A	55541352	22000	0	0
CascadeLcToLcShadowedAboveRise_A	55541352	22000	0	0
CascadePorToAonAboveFall_A	1683086	6820	0	0
CascadeSysToSysAboveFall_A	55541352	22000	0	0
CascadeSysToSysAboveRise_A	55541352	22000	0	0
ScanRstToAonRise_A	1683086	210	0	0
StablePorToAonRise_A	1683086	8696	0	0
g_power_domains[0].CascadeLcToSysAboveFall_A	11834250	22000	0	0
g_power_domains[0].CascadeLcToSysAboveRise_A	11834250	22000	0	0
g_power_domains[0].CascadeLocalRstToLcAboveFall_A	11834250	22000	0	0
g_power_domains[0].CascadeLocalRstToLcAboveRise_A	11834250	22000	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A	13329756	22000	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A	13329756	22000	0	0
g_power_domains[1].CascadeLcToSysAboveFall_A	11834250	22000	0	0
g_power_domains[1].CascadeLcToSysAboveRise_A	11834250	22000	0	0
g_power_domains[1].CascadeLocalRstToLcAboveFall_A	11834250	22000	0	0
g_power_domains[1].CascadeLocalRstToLcAboveRise_A	11834250	22000	0	0

CascadeEffAonToRstPorAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55541352	8696	0	0
T1	15034	1	0	0
T2	236099	27	0	0
T3	12062	2	0	0
T4	20435	2	0	0
T5	15671	2	0	0
T6	7641	2	0	0
T7	732145	68	0	0
T8	17849	2	0	0
T9	10585	2	0	0
T10	185632	21	0	0

CascadeEffAonToRstPorAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55541352	8696	0	0
T1	15034	1	0	0
T2	236099	27	0	0
T3	12062	2	0	0
T4	20435	2	0	0
T5	15671	2	0	0
T6	7641	2	0	0
T7	732145	68	0	0
T8	17849	2	0	0
T9	10585	2	0	0
T10	185632	21	0	0

CascadeEffAonToRstPorIoAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53317754	8696	0	0
T1	14433	1	0	0
T2	226641	27	0	0
T3	11586	2	0	0
T4	19614	2	0	0
T5	15043	2	0	0
T6	7335	2	0	0
T7	702874	68	0	0
T8	17134	2	0	0
T9	10158	2	0	0
T10	178209	21	0	0

CascadeEffAonToRstPorIoAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53317754	8696	0	0
T1	14433	1	0	0
T2	226641	27	0	0
T3	11586	2	0	0
T4	19614	2	0	0
T5	15043	2	0	0
T6	7335	2	0	0
T7	702874	68	0	0
T8	17134	2	0	0
T9	10158	2	0	0
T10	178209	21	0	0

CascadeEffAonToRstPorIoDiv2AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26659536	8696	0	0
T1	7216	1	0	0
T2	113315	27	0	0
T3	5791	2	0	0
T4	9808	2	0	0
T5	7519	2	0	0
T6	3667	2	0	0
T7	351445	68	0	0
T8	8567	2	0	0
T9	5079	2	0	0
T10	89115	21	0	0

CascadeEffAonToRstPorIoDiv2AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26659536	8696	0	0
T1	7216	1	0	0
T2	113315	27	0	0
T3	5791	2	0	0
T4	9808	2	0	0
T5	7519	2	0	0
T6	3667	2	0	0
T7	351445	68	0	0
T8	8567	2	0	0
T9	5079	2	0	0
T10	89115	21	0	0

CascadeEffAonToRstPorIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13329756	8696	0	0
T1	3606	1	0	0
T2	56663	27	0	0
T3	2894	2	0	0
T4	4903	2	0	0
T5	3761	2	0	0
T6	1833	2	0	0
T7	175724	68	0	0
T8	4282	2	0	0
T9	2540	2	0	0
T10	44553	21	0	0

CascadeEffAonToRstPorIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13329756	8696	0	0
T1	3606	1	0	0
T2	56663	27	0	0
T3	2894	2	0	0
T4	4903	2	0	0
T5	3761	2	0	0
T6	1833	2	0	0
T7	175724	68	0	0
T8	4282	2	0	0
T9	2540	2	0	0
T10	44553	21	0	0

CascadeEffAonToRstPorUcbAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26659681	8696	0	0
T1	7216	1	0	0
T2	113311	27	0	0
T3	5790	2	0	0
T4	9807	2	0	0
T5	7521	2	0	0
T6	3667	2	0	0
T7	351444	68	0	0
T8	8567	2	0	0
T9	5079	2	0	0
T10	89108	21	0	0

CascadeEffAonToRstPorUcbAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26659681	8696	0	0
T1	7216	1	0	0
T2	113311	27	0	0
T3	5790	2	0	0
T4	9807	2	0	0
T5	7521	2	0	0
T6	3667	2	0	0
T7	351444	68	0	0
T8	8567	2	0	0
T9	5079	2	0	0
T10	89108	21	0	0

CascadeLcToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55541352	22000	0	0
T1	15034	1	0	0
T2	236099	102	0	0
T3	12062	6	0	0
T4	20435	6	0	0
T5	15671	6	0	0
T6	7641	2	0	0
T7	732145	215	0	0
T8	17849	2	0	0
T9	10585	6	0	0
T10	185632	54	0	0

CascadeLcToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55541352	22000	0	0
T1	15034	1	0	0
T2	236099	102	0	0
T3	12062	6	0	0
T4	20435	6	0	0
T5	15671	6	0	0
T6	7641	2	0	0
T7	732145	215	0	0
T8	17849	2	0	0
T9	10585	6	0	0
T10	185632	54	0	0

CascadeLcToLcAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1683086	22000	0	0
T1	450	1	0	0
T2	7097	102	0	0
T3	361	6	0	0
T4	611	6	0	0
T5	470	6	0	0
T6	228	2	0	0
T7	22193	215	0	0
T8	534	2	0	0
T9	316	6	0	0
T10	5615	54	0	0

CascadeLcToLcAonAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1683086	22000	0	0
T1	450	1	0	0
T2	7097	102	0	0
T3	361	6	0	0
T4	611	6	0	0
T5	470	6	0	0
T6	228	2	0	0
T7	22193	215	0	0
T8	534	2	0	0
T9	316	6	0	0
T10	5615	54	0	0

CascadeLcToLcShadowedAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55541352	22000	0	0
T1	15034	1	0	0
T2	236099	102	0	0
T3	12062	6	0	0
T4	20435	6	0	0
T5	15671	6	0	0
T6	7641	2	0	0
T7	732145	215	0	0
T8	17849	2	0	0
T9	10585	6	0	0
T10	185632	54	0	0

CascadeLcToLcShadowedAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55541352	22000	0	0
T1	15034	1	0	0
T2	236099	102	0	0
T3	12062	6	0	0
T4	20435	6	0	0
T5	15671	6	0	0
T6	7641	2	0	0
T7	732145	215	0	0
T8	17849	2	0	0
T9	10585	6	0	0
T10	185632	54	0	0

CascadePorToAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1683086	6820	0	0
T1	450	1	0	0
T2	7097	27	0	0
T3	361	1	0	0
T4	611	1	0	0
T5	470	1	0	0
T6	228	3	0	0
T7	22193	33	0	0
T8	534	13	0	0
T9	316	1	0	0
T10	5615	9	0	0

CascadeSysToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55541352	22000	0	0
T1	15034	1	0	0
T2	236099	102	0	0
T3	12062	6	0	0
T4	20435	6	0	0
T5	15671	6	0	0
T6	7641	2	0	0
T7	732145	215	0	0
T8	17849	2	0	0
T9	10585	6	0	0
T10	185632	54	0	0

CascadeSysToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55541352	22000	0	0
T1	15034	1	0	0
T2	236099	102	0	0
T3	12062	6	0	0
T4	20435	6	0	0
T5	15671	6	0	0
T6	7641	2	0	0
T7	732145	215	0	0
T8	17849	2	0	0
T9	10585	6	0	0
T10	185632	54	0	0

ScanRstToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1683086	210	0	0
T7	22193	3	0	0
T8	534	0	0	0
T9	316	1	0	0
T10	5615	0	0	0
T11	350	0	0	0
T20	1043	0	0	0
T21	210	0	0	0
T22	22528	9	0	0
T23	732	0	0	0
T24	738	0	0	0
T38	0	1	0	0
T40	0	1	0	0
T47	0	2	0	0
T48	0	8	0	0
T60	0	4	0	0
T106	0	2	0	0
T107	0	2	0	0

StablePorToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1683086	8696	0	0
T1	450	1	0	0
T2	7097	27	0	0
T3	361	2	0	0
T4	611	2	0	0
T5	470	2	0	0
T6	228	2	0	0
T7	22193	68	0	0
T8	534	2	0	0
T9	316	2	0	0
T10	5615	21	0	0

g_power_domains[0].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11834250	22000	0	0
T1	3517	1	0	0
T2	53205	102	0	0
T3	2799	6	0	0
T4	4615	6	0	0
T5	3569	6	0	0
T6	1645	2	0	0
T7	159347	215	0	0
T8	4192	2	0	0
T9	2346	6	0	0
T10	38577	54	0	0

g_power_domains[0].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11834250	22000	0	0
T1	3517	1	0	0
T2	53205	102	0	0
T3	2799	6	0	0
T4	4615	6	0	0
T5	3569	6	0	0
T6	1645	2	0	0
T7	159347	215	0	0
T8	4192	2	0	0
T9	2346	6	0	0
T10	38577	54	0	0

g_power_domains[0].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11834250	22000	0	0
T1	3517	1	0	0
T2	53205	102	0	0
T3	2799	6	0	0
T4	4615	6	0	0
T5	3569	6	0	0
T6	1645	2	0	0
T7	159347	215	0	0
T8	4192	2	0	0
T9	2346	6	0	0
T10	38577	54	0	0

g_power_domains[0].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11834250	22000	0	0
T1	3517	1	0	0
T2	53205	102	0	0
T3	2799	6	0	0
T4	4615	6	0	0
T5	3569	6	0	0
T6	1645	2	0	0
T7	159347	215	0	0
T8	4192	2	0	0
T9	2346	6	0	0
T10	38577	54	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13329756	22000	0	0
T1	3606	1	0	0
T2	56663	102	0	0
T3	2894	6	0	0
T4	4903	6	0	0
T5	3761	6	0	0
T6	1833	2	0	0
T7	175724	215	0	0
T8	4282	2	0	0
T9	2540	6	0	0
T10	44553	54	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13329756	22000	0	0
T1	3606	1	0	0
T2	56663	102	0	0
T3	2894	6	0	0
T4	4903	6	0	0
T5	3761	6	0	0
T6	1833	2	0	0
T7	175724	215	0	0
T8	4282	2	0	0
T9	2540	6	0	0
T10	44553	54	0	0

g_power_domains[1].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11834250	22000	0	0
T1	3517	1	0	0
T2	53205	102	0	0
T3	2799	6	0	0
T4	4615	6	0	0
T5	3569	6	0	0
T6	1645	2	0	0
T7	159347	215	0	0
T8	4192	2	0	0
T9	2346	6	0	0
T10	38577	54	0	0

g_power_domains[1].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11834250	22000	0	0
T1	3517	1	0	0
T2	53205	102	0	0
T3	2799	6	0	0
T4	4615	6	0	0
T5	3569	6	0	0
T6	1645	2	0	0
T7	159347	215	0	0
T8	4192	2	0	0
T9	2346	6	0	0
T10	38577	54	0	0

g_power_domains[1].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11834250	22000	0	0
T1	3517	1	0	0
T2	53205	102	0	0
T3	2799	6	0	0
T4	4615	6	0	0
T5	3569	6	0	0
T6	1645	2	0	0
T7	159347	215	0	0
T8	4192	2	0	0
T9	2346	6	0	0
T10	38577	54	0	0

g_power_domains[1].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11834250	22000	0	0
T1	3517	1	0	0
T2	53205	102	0	0
T3	2799	6	0	0
T4	4615	6	0	0
T5	3569	6	0	0
T6	1645	2	0	0
T7	159347	215	0	0
T8	4192	2	0	0
T9	2346	6	0	0
T10	38577	54	0	0