Unified Coverage Report :: Module :: rstmgr_sw_rst_sva_if

Module : rstmgr_sw_rst_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_sw_rst_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_sw_rst_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_sw_rst_sva_if

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
21	8	8

---

Cond Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Covered	Percent
Conditions	24	24	100.00
Logical	24	24	100.00
Non-Logical	0	0
Event	0	0

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[0])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T7
1	0	Covered	T2,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[1])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T4,T7
1	0	Covered	T2,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[2])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T7,T20
1	0	Covered	T2,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[3])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T7
1	0	Covered	T2,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[4])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T4,T7
1	0	Covered	T2,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[5])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T7,T20
1	0	Covered	T2,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[6])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T7,T20
1	0	Covered	T2,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[7])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T7,T20
1	0	Covered	T2,T3,T4

---

Assert Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions[0].RstEnOff_A	13329756	14145	0	0
gen_assertions[0].RstEnOn_A	13329756	1029	0	0
gen_assertions[0].RstNOff_A	13329756	14145	0	0
gen_assertions[0].RstNOn_A	13329756	1029	0	0
gen_assertions[1].RstEnOff_A	53317754	12879	0	0
gen_assertions[1].RstEnOn_A	53317754	996	0	0
gen_assertions[1].RstNOff_A	53317754	12879	0	0
gen_assertions[1].RstNOn_A	53317754	996	0	0
gen_assertions[2].RstEnOff_A	26659536	12917	0	0
gen_assertions[2].RstEnOn_A	26659536	983	0	0
gen_assertions[2].RstNOff_A	26659536	12917	0	0
gen_assertions[2].RstNOn_A	26659536	983	0	0
gen_assertions[3].RstEnOff_A	26659681	12980	0	0
gen_assertions[3].RstEnOn_A	26659681	1037	0	0
gen_assertions[3].RstNOff_A	26659681	12980	0	0
gen_assertions[3].RstNOn_A	26659681	1037	0	0
gen_assertions[4].RstEnOff_A	1683086	21720	0	0
gen_assertions[4].RstEnOn_A	1683086	1051	0	0
gen_assertions[4].RstNOff_A	1683086	21720	0	0
gen_assertions[4].RstNOn_A	1683086	1051	0	0
gen_assertions[5].RstEnOff_A	13329756	14397	0	0
gen_assertions[5].RstEnOn_A	13329756	1121	0	0
gen_assertions[5].RstNOff_A	13329756	14397	0	0
gen_assertions[5].RstNOn_A	13329756	1121	0	0
gen_assertions[6].RstEnOff_A	13329756	14434	0	0
gen_assertions[6].RstEnOn_A	13329756	1161	0	0
gen_assertions[6].RstNOff_A	13329756	14434	0	0
gen_assertions[6].RstNOn_A	13329756	1161	0	0
gen_assertions[7].RstEnOff_A	13329756	14511	0	0
gen_assertions[7].RstEnOn_A	13329756	1232	0	0
gen_assertions[7].RstNOff_A	13329756	14511	0	0
gen_assertions[7].RstNOn_A	13329756	1232	0	0

gen_assertions[0].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13329756	14145	0	0
T1	3606	5	0	0
T2	56663	75	0	0
T3	2894	5	0	0
T4	4903	4	0	0
T5	3761	4	0	0
T6	1833	0	0	0
T7	175724	165	0	0
T8	4282	0	0	0
T9	2540	4	0	0
T10	44553	33	0	0
T11	0	10	0	0
T20	0	8	0	0

gen_assertions[0].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13329756	1029	0	0
T1	3606	5	0	0
T2	56663	0	0	0
T3	2894	1	0	0
T4	4903	0	0	0
T5	3761	0	0	0
T6	1833	0	0	0
T7	175724	20	0	0
T8	4282	0	0	0
T9	2540	0	0	0
T10	44553	0	0	0
T11	0	7	0	0
T20	0	8	0	0
T22	0	29	0	0
T46	0	1	0	0
T48	0	23	0	0
T55	0	1	0	0
T66	0	1	0	0

gen_assertions[0].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13329756	14145	0	0
T1	3606	5	0	0
T2	56663	75	0	0
T3	2894	5	0	0
T4	4903	4	0	0
T5	3761	4	0	0
T6	1833	0	0	0
T7	175724	165	0	0
T8	4282	0	0	0
T9	2540	4	0	0
T10	44553	33	0	0
T11	0	10	0	0
T20	0	8	0	0

gen_assertions[0].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13329756	1029	0	0
T1	3606	5	0	0
T2	56663	0	0	0
T3	2894	1	0	0
T4	4903	0	0	0
T5	3761	0	0	0
T6	1833	0	0	0
T7	175724	20	0	0
T8	4282	0	0	0
T9	2540	0	0	0
T10	44553	0	0	0
T11	0	7	0	0
T20	0	8	0	0
T22	0	29	0	0
T46	0	1	0	0
T48	0	23	0	0
T55	0	1	0	0
T66	0	1	0	0

gen_assertions[1].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53317754	12879	0	0
T1	14433	10	0	0
T2	226641	70	0	0
T3	11586	4	0	0
T4	19614	5	0	0
T5	15043	3	0	0
T6	7335	0	0	0
T7	702874	147	0	0
T8	17134	0	0	0
T9	10158	4	0	0
T10	178209	24	0	0
T11	0	9	0	0
T20	0	5	0	0

gen_assertions[1].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53317754	996	0	0
T1	14433	10	0	0
T2	226641	0	0	0
T3	11586	0	0	0
T4	19614	1	0	0
T5	15043	0	0	0
T6	7335	0	0	0
T7	702874	13	0	0
T8	17134	0	0	0
T9	10158	0	0	0
T10	178209	0	0	0
T11	0	2	0	0
T20	0	5	0	0
T22	0	28	0	0
T39	0	1	0	0
T46	0	1	0	0
T48	0	21	0	0
T60	0	29	0	0

gen_assertions[1].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53317754	12879	0	0
T1	14433	10	0	0
T2	226641	70	0	0
T3	11586	4	0	0
T4	19614	5	0	0
T5	15043	3	0	0
T6	7335	0	0	0
T7	702874	147	0	0
T8	17134	0	0	0
T9	10158	4	0	0
T10	178209	24	0	0
T11	0	9	0	0
T20	0	5	0	0

gen_assertions[1].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53317754	996	0	0
T1	14433	10	0	0
T2	226641	0	0	0
T3	11586	0	0	0
T4	19614	1	0	0
T5	15043	0	0	0
T6	7335	0	0	0
T7	702874	13	0	0
T8	17134	0	0	0
T9	10158	0	0	0
T10	178209	0	0	0
T11	0	2	0	0
T20	0	5	0	0
T22	0	28	0	0
T39	0	1	0	0
T46	0	1	0	0
T48	0	21	0	0
T60	0	29	0	0

gen_assertions[2].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26659536	12917	0	0
T1	7216	8	0	0
T2	113315	70	0	0
T3	5791	4	0	0
T4	9808	4	0	0
T5	7519	3	0	0
T6	3667	0	0	0
T7	351445	151	0	0
T8	8567	0	0	0
T9	5079	4	0	0
T10	89115	24	0	0
T11	0	9	0	0
T20	0	7	0	0

gen_assertions[2].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26659536	983	0	0
T1	7216	8	0	0
T2	113315	0	0	0
T3	5791	0	0	0
T4	9808	0	0	0
T5	7519	0	0	0
T6	3667	0	0	0
T7	351445	20	0	0
T8	8567	0	0	0
T9	5079	0	0	0
T10	89115	0	0	0
T20	0	7	0	0
T22	0	25	0	0
T41	0	3	0	0
T48	0	26	0	0
T60	0	29	0	0
T90	0	3	0	0
T91	0	9	0	0
T92	0	22	0	0

gen_assertions[2].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26659536	12917	0	0
T1	7216	8	0	0
T2	113315	70	0	0
T3	5791	4	0	0
T4	9808	4	0	0
T5	7519	3	0	0
T6	3667	0	0	0
T7	351445	151	0	0
T8	8567	0	0	0
T9	5079	4	0	0
T10	89115	24	0	0
T11	0	9	0	0
T20	0	7	0	0

gen_assertions[2].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26659536	983	0	0
T1	7216	8	0	0
T2	113315	0	0	0
T3	5791	0	0	0
T4	9808	0	0	0
T5	7519	0	0	0
T6	3667	0	0	0
T7	351445	20	0	0
T8	8567	0	0	0
T9	5079	0	0	0
T10	89115	0	0	0
T20	0	7	0	0
T22	0	25	0	0
T41	0	3	0	0
T48	0	26	0	0
T60	0	29	0	0
T90	0	3	0	0
T91	0	9	0	0
T92	0	22	0	0

gen_assertions[3].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26659681	12980	0	0
T1	7216	12	0	0
T2	113311	70	0	0
T3	5790	5	0	0
T4	9807	4	0	0
T5	7521	3	0	0
T6	3667	0	0	0
T7	351444	149	0	0
T8	8567	0	0	0
T9	5079	4	0	0
T10	89108	24	0	0
T11	0	9	0	0
T20	0	10	0	0

gen_assertions[3].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26659681	1037	0	0
T1	7216	12	0	0
T2	113311	0	0	0
T3	5790	1	0	0
T4	9807	0	0	0
T5	7521	0	0	0
T6	3667	0	0	0
T7	351444	16	0	0
T8	8567	0	0	0
T9	5079	0	0	0
T10	89108	0	0	0
T20	0	10	0	0
T22	0	26	0	0
T48	0	24	0	0
T60	0	31	0	0
T66	0	1	0	0
T67	0	1	0	0
T93	0	1	0	0

gen_assertions[3].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26659681	12980	0	0
T1	7216	12	0	0
T2	113311	70	0	0
T3	5790	5	0	0
T4	9807	4	0	0
T5	7521	3	0	0
T6	3667	0	0	0
T7	351444	149	0	0
T8	8567	0	0	0
T9	5079	4	0	0
T10	89108	24	0	0
T11	0	9	0	0
T20	0	10	0	0

gen_assertions[3].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26659681	1037	0	0
T1	7216	12	0	0
T2	113311	0	0	0
T3	5790	1	0	0
T4	9807	0	0	0
T5	7521	0	0	0
T6	3667	0	0	0
T7	351444	16	0	0
T8	8567	0	0	0
T9	5079	0	0	0
T10	89108	0	0	0
T20	0	10	0	0
T22	0	26	0	0
T48	0	24	0	0
T60	0	31	0	0
T66	0	1	0	0
T67	0	1	0	0
T93	0	1	0	0

gen_assertions[4].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1683086	21720	0	0
T1	450	15	0	0
T2	7097	99	0	0
T3	361	6	0	0
T4	611	7	0	0
T5	470	6	0	0
T6	228	2	0	0
T7	22193	229	0	0
T8	534	2	0	0
T9	316	6	0	0
T10	5615	53	0	0

gen_assertions[4].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1683086	1051	0	0
T1	450	14	0	0
T2	7097	0	0	0
T3	361	0	0	0
T4	611	1	0	0
T5	470	0	0	0
T6	228	0	0	0
T7	22193	18	0	0
T8	534	0	0	0
T9	316	0	0	0
T10	5615	0	0	0
T20	0	10	0	0
T22	0	24	0	0
T41	0	4	0	0
T48	0	25	0	0
T60	0	30	0	0
T91	0	10	0	0
T94	0	1	0	0

gen_assertions[4].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1683086	21720	0	0
T1	450	15	0	0
T2	7097	99	0	0
T3	361	6	0	0
T4	611	7	0	0
T5	470	6	0	0
T6	228	2	0	0
T7	22193	229	0	0
T8	534	2	0	0
T9	316	6	0	0
T10	5615	53	0	0

gen_assertions[4].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1683086	1051	0	0
T1	450	14	0	0
T2	7097	0	0	0
T3	361	0	0	0
T4	611	1	0	0
T5	470	0	0	0
T6	228	0	0	0
T7	22193	18	0	0
T8	534	0	0	0
T9	316	0	0	0
T10	5615	0	0	0
T20	0	10	0	0
T22	0	24	0	0
T41	0	4	0	0
T48	0	25	0	0
T60	0	30	0	0
T91	0	10	0	0
T94	0	1	0	0

gen_assertions[5].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13329756	14397	0	0
T1	3606	13	0	0
T2	56663	75	0	0
T3	2894	4	0	0
T4	4903	4	0	0
T5	3761	4	0	0
T6	1833	0	0	0
T7	175724	163	0	0
T8	4282	0	0	0
T9	2540	4	0	0
T10	44553	33	0	0
T11	0	10	0	0
T20	0	12	0	0

gen_assertions[5].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13329756	1121	0	0
T1	3606	13	0	0
T2	56663	0	0	0
T3	2894	0	0	0
T4	4903	0	0	0
T5	3761	0	0	0
T6	1833	0	0	0
T7	175724	18	0	0
T8	4282	0	0	0
T9	2540	0	0	0
T10	44553	0	0	0
T20	0	12	0	0
T22	0	29	0	0
T41	0	6	0	0
T48	0	23	0	0
T60	0	34	0	0
T66	0	1	0	0
T91	0	8	0	0
T95	0	1	0	0

gen_assertions[5].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13329756	14397	0	0
T1	3606	13	0	0
T2	56663	75	0	0
T3	2894	4	0	0
T4	4903	4	0	0
T5	3761	4	0	0
T6	1833	0	0	0
T7	175724	163	0	0
T8	4282	0	0	0
T9	2540	4	0	0
T10	44553	33	0	0
T11	0	10	0	0
T20	0	12	0	0

gen_assertions[5].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13329756	1121	0	0
T1	3606	13	0	0
T2	56663	0	0	0
T3	2894	0	0	0
T4	4903	0	0	0
T5	3761	0	0	0
T6	1833	0	0	0
T7	175724	18	0	0
T8	4282	0	0	0
T9	2540	0	0	0
T10	44553	0	0	0
T20	0	12	0	0
T22	0	29	0	0
T41	0	6	0	0
T48	0	23	0	0
T60	0	34	0	0
T66	0	1	0	0
T91	0	8	0	0
T95	0	1	0	0

gen_assertions[6].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13329756	14434	0	0
T1	3606	13	0	0
T2	56663	75	0	0
T3	2894	4	0	0
T4	4903	4	0	0
T5	3761	4	0	0
T6	1833	0	0	0
T7	175724	163	0	0
T8	4282	0	0	0
T9	2540	4	0	0
T10	44553	33	0	0
T11	0	10	0	0
T20	0	11	0	0

gen_assertions[6].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13329756	1161	0	0
T1	3606	13	0	0
T2	56663	0	0	0
T3	2894	0	0	0
T4	4903	0	0	0
T5	3761	0	0	0
T6	1833	0	0	0
T7	175724	16	0	0
T8	4282	0	0	0
T9	2540	0	0	0
T10	44553	0	0	0
T20	0	11	0	0
T22	0	25	0	0
T41	0	7	0	0
T48	0	21	0	0
T56	0	1	0	0
T60	0	27	0	0
T93	0	1	0	0
T95	0	1	0	0

gen_assertions[6].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13329756	14434	0	0
T1	3606	13	0	0
T2	56663	75	0	0
T3	2894	4	0	0
T4	4903	4	0	0
T5	3761	4	0	0
T6	1833	0	0	0
T7	175724	163	0	0
T8	4282	0	0	0
T9	2540	4	0	0
T10	44553	33	0	0
T11	0	10	0	0
T20	0	11	0	0

gen_assertions[6].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13329756	1161	0	0
T1	3606	13	0	0
T2	56663	0	0	0
T3	2894	0	0	0
T4	4903	0	0	0
T5	3761	0	0	0
T6	1833	0	0	0
T7	175724	16	0	0
T8	4282	0	0	0
T9	2540	0	0	0
T10	44553	0	0	0
T20	0	11	0	0
T22	0	25	0	0
T41	0	7	0	0
T48	0	21	0	0
T56	0	1	0	0
T60	0	27	0	0
T93	0	1	0	0
T95	0	1	0	0

gen_assertions[7].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13329756	14511	0	0
T1	3606	16	0	0
T2	56663	75	0	0
T3	2894	4	0	0
T4	4903	4	0	0
T5	3761	4	0	0
T6	1833	0	0	0
T7	175724	163	0	0
T8	4282	0	0	0
T9	2540	4	0	0
T10	44553	33	0	0
T11	0	10	0	0
T20	0	15	0	0

gen_assertions[7].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13329756	1232	0	0
T1	3606	16	0	0
T2	56663	0	0	0
T3	2894	0	0	0
T4	4903	0	0	0
T5	3761	0	0	0
T6	1833	0	0	0
T7	175724	18	0	0
T8	4282	0	0	0
T9	2540	0	0	0
T10	44553	0	0	0
T20	0	15	0	0
T22	0	32	0	0
T41	0	8	0	0
T48	0	21	0	0
T60	0	34	0	0
T66	0	1	0	0
T91	0	13	0	0
T94	0	1	0	0

gen_assertions[7].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13329756	14511	0	0
T1	3606	16	0	0
T2	56663	75	0	0
T3	2894	4	0	0
T4	4903	4	0	0
T5	3761	4	0	0
T6	1833	0	0	0
T7	175724	163	0	0
T8	4282	0	0	0
T9	2540	4	0	0
T10	44553	33	0	0
T11	0	10	0	0
T20	0	15	0	0

gen_assertions[7].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13329756	1232	0	0
T1	3606	16	0	0
T2	56663	0	0	0
T3	2894	0	0	0
T4	4903	0	0	0
T5	3761	0	0	0
T6	1833	0	0	0
T7	175724	18	0	0
T8	4282	0	0	0
T9	2540	0	0	0
T10	44553	0	0	0
T20	0	15	0	0
T22	0	32	0	0
T41	0	8	0	0
T48	0	21	0	0
T60	0	34	0	0
T66	0	1	0	0
T91	0	13	0	0
T94	0	1	0	0