Unified Coverage Report :: Module :: rstmgr_csr_assert_fpv

Module : rstmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rstmgr_csr_assert_0/rstmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rstmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rstmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	19	19	100.00	19	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	19	19	100.00	19	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	12544345	7404	0	0
alert_regwen_rd_A	12544345	5508	0	0
cpu_regwen_rd_A	12544345	5838	0	0
sw_rst_ctrl_n_0_rd_A	12544345	10652	0	0
sw_rst_ctrl_n_1_rd_A	12544345	10734	0	0
sw_rst_ctrl_n_2_rd_A	12544345	10632	0	0
sw_rst_ctrl_n_3_rd_A	12544345	10514	0	0
sw_rst_ctrl_n_4_rd_A	12544345	10554	0	0
sw_rst_ctrl_n_5_rd_A	12544345	10997	0	0
sw_rst_ctrl_n_6_rd_A	12544345	10609	0	0
sw_rst_ctrl_n_7_rd_A	12544345	10548	0	0
sw_rst_regwen_0_rd_A	12544345	6126	0	0
sw_rst_regwen_1_rd_A	12544345	6165	0	0
sw_rst_regwen_2_rd_A	12544345	6160	0	0
sw_rst_regwen_3_rd_A	12544345	6550	0	0
sw_rst_regwen_4_rd_A	12544345	6296	0	0
sw_rst_regwen_5_rd_A	12544345	6356	0	0
sw_rst_regwen_6_rd_A	12544345	6150	0	0
sw_rst_regwen_7_rd_A	12544345	6277	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12544345	7404	0	0
T64	2591	6	0	0
T68	4305	19	0	0
T69	20525	3	0	0
T70	2496	30	0	0
T71	13069	2	0	0
T72	11096	602	0	0
T96	11013	4	0	0
T97	17824	1	0	0
T98	20122	4	0	0
T102	20927	2	0	0

alert_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12544345	5508	0	0
T7	159347	190	0	0
T8	4192	0	0	0
T9	2346	0	0	0
T10	38577	66	0	0
T11	2021	0	0	0
T20	8313	0	0	0
T21	1609	0	0	0
T22	136574	0	0	0
T23	5296	0	0	0
T24	4774	0	0	0
T40	0	35	0	0
T57	0	34	0	0
T85	0	46	0	0
T92	0	86	0	0
T107	0	33	0	0
T111	0	66	0	0
T133	0	28	0	0
T134	0	63	0	0

cpu_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12544345	5838	0	0
T7	159347	194	0	0
T8	4192	0	0	0
T9	2346	0	0	0
T10	38577	49	0	0
T11	2021	0	0	0
T20	8313	0	0	0
T21	1609	0	0	0
T22	136574	0	0	0
T23	5296	0	0	0
T24	4774	0	0	0
T40	0	18	0	0
T57	0	72	0	0
T85	0	46	0	0
T92	0	50	0	0
T107	0	32	0	0
T111	0	122	0	0
T133	0	23	0	0
T134	0	55	0	0

sw_rst_ctrl_n_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12544345	10652	0	0
T7	159347	452	0	0
T8	4192	0	0	0
T9	2346	0	0	0
T10	38577	66	0	0
T11	2021	0	0	0
T20	8313	0	0	0
T21	1609	0	0	0
T22	136574	0	0	0
T23	5296	0	0	0
T24	4774	35	0	0
T35	0	3	0	0
T40	0	42	0	0
T57	0	47	0	0
T66	0	11	0	0
T92	0	229	0	0
T94	0	15	0	0
T107	0	23	0	0

sw_rst_ctrl_n_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12544345	10734	0	0
T7	159347	448	0	0
T8	4192	0	0	0
T9	2346	0	0	0
T10	38577	72	0	0
T11	2021	0	0	0
T20	8313	0	0	0
T21	1609	0	0	0
T22	136574	0	0	0
T23	5296	0	0	0
T24	4774	28	0	0
T35	0	7	0	0
T40	0	38	0	0
T57	0	64	0	0
T66	0	9	0	0
T92	0	291	0	0
T94	0	12	0	0
T107	0	48	0	0

sw_rst_ctrl_n_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12544345	10632	0	0
T7	159347	449	0	0
T8	4192	0	0	0
T9	2346	0	0	0
T10	38577	63	0	0
T11	2021	0	0	0
T20	8313	0	0	0
T21	1609	0	0	0
T22	136574	0	0	0
T23	5296	0	0	0
T24	4774	40	0	0
T35	0	18	0	0
T40	0	41	0	0
T57	0	49	0	0
T66	0	13	0	0
T92	0	266	0	0
T94	0	11	0	0
T107	0	40	0	0

sw_rst_ctrl_n_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12544345	10514	0	0
T7	159347	414	0	0
T8	4192	0	0	0
T9	2346	0	0	0
T10	38577	65	0	0
T11	2021	0	0	0
T20	8313	0	0	0
T21	1609	0	0	0
T22	136574	0	0	0
T23	5296	0	0	0
T24	4774	41	0	0
T40	0	24	0	0
T57	0	49	0	0
T66	0	10	0	0
T92	0	252	0	0
T94	0	6	0	0
T107	0	20	0	0
T135	0	22	0	0

sw_rst_ctrl_n_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12544345	10554	0	0
T7	159347	423	0	0
T8	4192	0	0	0
T9	2346	0	0	0
T10	38577	56	0	0
T11	2021	0	0	0
T20	8313	0	0	0
T21	1609	0	0	0
T22	136574	0	0	0
T23	5296	0	0	0
T24	4774	34	0	0
T35	0	11	0	0
T40	0	19	0	0
T57	0	42	0	0
T66	0	8	0	0
T92	0	291	0	0
T94	0	10	0	0
T107	0	30	0	0

sw_rst_ctrl_n_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12544345	10997	0	0
T7	159347	401	0	0
T8	4192	0	0	0
T9	2346	0	0	0
T10	38577	92	0	0
T11	2021	0	0	0
T20	8313	0	0	0
T21	1609	0	0	0
T22	136574	0	0	0
T23	5296	0	0	0
T24	4774	52	0	0
T35	0	2	0	0
T40	0	32	0	0
T57	0	34	0	0
T66	0	12	0	0
T92	0	228	0	0
T94	0	27	0	0
T107	0	41	0	0

sw_rst_ctrl_n_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12544345	10609	0	0
T7	159347	422	0	0
T8	4192	0	0	0
T9	2346	0	0	0
T10	38577	91	0	0
T11	2021	0	0	0
T20	8313	0	0	0
T21	1609	0	0	0
T22	136574	0	0	0
T23	5296	0	0	0
T24	4774	43	0	0
T35	0	16	0	0
T40	0	20	0	0
T57	0	69	0	0
T66	0	15	0	0
T92	0	235	0	0
T94	0	2	0	0
T107	0	30	0	0

sw_rst_ctrl_n_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12544345	10548	0	0
T7	159347	400	0	0
T8	4192	0	0	0
T9	2346	0	0	0
T10	38577	71	0	0
T11	2021	0	0	0
T20	8313	0	0	0
T21	1609	0	0	0
T22	136574	0	0	0
T23	5296	0	0	0
T24	4774	36	0	0
T35	0	5	0	0
T40	0	23	0	0
T57	0	50	0	0
T66	0	12	0	0
T92	0	254	0	0
T94	0	5	0	0
T107	0	41	0	0

sw_rst_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12544345	6126	0	0
T7	159347	220	0	0
T8	4192	0	0	0
T9	2346	0	0	0
T10	38577	73	0	0
T11	2021	0	0	0
T20	8313	0	0	0
T21	1609	0	0	0
T22	136574	0	0	0
T23	5296	0	0	0
T24	4774	0	0	0
T40	0	39	0	0
T57	0	56	0	0
T66	0	7	0	0
T85	0	71	0	0
T92	0	79	0	0
T94	0	14	0	0
T107	0	33	0	0
T135	0	5	0	0

sw_rst_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12544345	6165	0	0
T7	159347	159	0	0
T8	4192	0	0	0
T9	2346	0	0	0
T10	38577	87	0	0
T11	2021	0	0	0
T20	8313	0	0	0
T21	1609	0	0	0
T22	136574	0	0	0
T23	5296	0	0	0
T24	4774	0	0	0
T40	0	31	0	0
T57	0	30	0	0
T66	0	9	0	0
T85	0	74	0	0
T92	0	83	0	0
T94	0	1	0	0
T107	0	30	0	0
T135	0	1	0	0

sw_rst_regwen_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12544345	6160	0	0
T7	159347	191	0	0
T8	4192	0	0	0
T9	2346	0	0	0
T10	38577	68	0	0
T11	2021	0	0	0
T20	8313	0	0	0
T21	1609	0	0	0
T22	136574	0	0	0
T23	5296	0	0	0
T24	4774	0	0	0
T40	0	46	0	0
T57	0	60	0	0
T66	0	7	0	0
T85	0	67	0	0
T92	0	72	0	0
T107	0	32	0	0
T111	0	97	0	0
T135	0	8	0	0

sw_rst_regwen_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12544345	6550	0	0
T7	159347	194	0	0
T8	4192	0	0	0
T9	2346	0	0	0
T10	38577	65	0	0
T11	2021	0	0	0
T20	8313	0	0	0
T21	1609	0	0	0
T22	136574	0	0	0
T23	5296	0	0	0
T24	4774	0	0	0
T40	0	29	0	0
T57	0	42	0	0
T66	0	7	0	0
T85	0	82	0	0
T92	0	80	0	0
T107	0	34	0	0
T111	0	90	0	0
T135	0	3	0	0

sw_rst_regwen_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12544345	6296	0	0
T7	159347	179	0	0
T8	4192	0	0	0
T9	2346	0	0	0
T10	38577	59	0	0
T11	2021	0	0	0
T20	8313	0	0	0
T21	1609	0	0	0
T22	136574	0	0	0
T23	5296	0	0	0
T24	4774	0	0	0
T40	0	49	0	0
T57	0	60	0	0
T66	0	9	0	0
T85	0	51	0	0
T92	0	110	0	0
T94	0	1	0	0
T107	0	32	0	0
T135	0	8	0	0

sw_rst_regwen_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12544345	6356	0	0
T7	159347	164	0	0
T8	4192	0	0	0
T9	2346	0	0	0
T10	38577	95	0	0
T11	2021	0	0	0
T20	8313	0	0	0
T21	1609	0	0	0
T22	136574	0	0	0
T23	5296	0	0	0
T24	4774	0	0	0
T40	0	25	0	0
T57	0	42	0	0
T66	0	9	0	0
T85	0	67	0	0
T92	0	86	0	0
T94	0	2	0	0
T107	0	32	0	0
T135	0	10	0	0

sw_rst_regwen_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12544345	6150	0	0
T7	159347	188	0	0
T8	4192	0	0	0
T9	2346	0	0	0
T10	38577	78	0	0
T11	2021	0	0	0
T20	8313	0	0	0
T21	1609	0	0	0
T22	136574	0	0	0
T23	5296	0	0	0
T24	4774	0	0	0
T40	0	64	0	0
T57	0	52	0	0
T66	0	7	0	0
T85	0	64	0	0
T92	0	90	0	0
T107	0	37	0	0
T111	0	135	0	0
T135	0	2	0	0

sw_rst_regwen_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12544345	6277	0	0
T7	159347	192	0	0
T8	4192	0	0	0
T9	2346	0	0	0
T10	38577	64	0	0
T11	2021	0	0	0
T20	8313	0	0	0
T21	1609	0	0	0
T22	136574	0	0	0
T23	5296	0	0	0
T24	4774	0	0	0
T40	0	65	0	0
T57	0	53	0	0
T66	0	6	0	0
T85	0	49	0	0
T92	0	64	0	0
T94	0	6	0	0
T107	0	36	0	0
T135	0	6	0	0