Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	620445	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

374017

1

T1

75

T3

367

T4

7

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	529727	1			T1	90		T2	1		T3	491
values[0x0]	232547	1			T1	61		T3	224		T4	8
values[0x1]	232188	1			T1	35		T3	221		T4	4

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	520703	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

473759

1

T1

90

T3

437

T4

12

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	6403	1			T3	4		T4	1		T6	12
valid_sources[0x01]	3896	1			T3	11		T6	9		T7	1
valid_sources[0x02]	3550	1			T3	3		T6	29		T7	4
valid_sources[0x03]	3151	1			T3	1		T6	17		T7	8
valid_sources[0x04]	4062	1			T3	6		T6	33		T7	7
valid_sources[0x05]	3464	1			T3	2		T6	23		T7	19
valid_sources[0x06]	4083	1			T3	3		T6	8		T7	37
valid_sources[0x07]	3881	1			T3	1		T6	10		T7	10
valid_sources[0x08]	3315	1			T3	4		T6	18		T7	4
valid_sources[0x09]	3212	1			T3	6		T6	14		T8	1
valid_sources[0x0a]	3416	1			T3	5		T6	12		T7	1
valid_sources[0x0b]	3537	1			T3	8		T6	11		T7	7
valid_sources[0x0c]	3484	1			T3	2		T6	12		T7	9
valid_sources[0x0d]	3777	1			T3	2		T6	12		T8	3
valid_sources[0x0e]	3847	1			T3	4		T6	16		T7	8
valid_sources[0x0f]	3320	1			T3	1		T6	4		T7	1
valid_sources[0x10]	3198	1			T3	4		T6	9		T7	12
valid_sources[0x11]	3869	1			T3	2		T6	21		T7	19
valid_sources[0x12]	3516	1			T3	3		T6	11		T7	8
valid_sources[0x13]	4182	1			T3	3		T6	8		T7	8
valid_sources[0x14]	4024	1			T3	3		T6	9		T7	26
valid_sources[0x15]	3940	1			T3	4		T6	25		T7	2
valid_sources[0x16]	3776	1			T3	1		T4	1		T6	24
valid_sources[0x17]	5400	1			T3	4		T6	20		T7	22
valid_sources[0x18]	3863	1			T3	2		T6	17		T7	4
valid_sources[0x19]	3776	1			T3	5		T6	21		T7	12
valid_sources[0x1a]	3752	1			T3	2		T6	22		T8	1
valid_sources[0x1b]	3551	1			T3	6		T6	13		T7	6
valid_sources[0x1c]	4061	1			T3	3		T4	1		T6	13
valid_sources[0x1d]	3959	1			T3	4		T6	23		T7	10
valid_sources[0x1e]	3761	1			T3	6		T6	22		T7	15
valid_sources[0x1f]	3232	1			T3	4		T6	12		T7	3
valid_sources[0x20]	3868	1			T3	1		T6	15		T7	8
valid_sources[0x21]	3752	1			T1	5		T3	3		T6	10
valid_sources[0x22]	4152	1			T1	6		T3	4		T6	23
valid_sources[0x23]	3658	1			T3	3		T6	22		T7	36
valid_sources[0x24]	3335	1			T3	3		T6	11		T7	5
valid_sources[0x25]	3431	1			T6	20		T7	17		T12	53
valid_sources[0x26]	3874	1			T3	3		T6	11		T7	14
valid_sources[0x27]	3489	1			T1	2		T3	1		T6	7
valid_sources[0x28]	3979	1			T3	2		T6	32		T7	2
valid_sources[0x29]	3419	1			T3	5		T6	15		T7	37
valid_sources[0x2a]	3669	1			T3	6		T4	1		T6	15
valid_sources[0x2b]	3965	1			T3	4		T6	10		T12	37
valid_sources[0x2c]	3615	1			T3	4		T6	13		T7	31
valid_sources[0x2d]	4683	1			T1	6		T6	11		T7	2
valid_sources[0x2e]	4075	1			T3	4		T6	17		T7	31
valid_sources[0x2f]	7333	1			T3	2		T6	10		T7	24
valid_sources[0x30]	3565	1			T3	7		T6	20		T7	31
valid_sources[0x31]	3732	1			T3	7		T6	20		T12	36
valid_sources[0x32]	7069	1			T3	5		T6	18		T7	16
valid_sources[0x33]	3397	1			T3	2		T6	19		T7	12
valid_sources[0x34]	3523	1			T3	8		T6	16		T7	15
valid_sources[0x35]	3575	1			T1	44		T3	1		T6	7
valid_sources[0x36]	5181	1			T3	5		T6	20		T7	11
valid_sources[0x37]	3926	1			T3	8		T6	9		T7	25
valid_sources[0x38]	3483	1			T3	5		T6	8		T7	13
valid_sources[0x39]	4147	1			T3	3		T6	9		T7	33
valid_sources[0x3a]	3483	1			T3	4		T6	14		T7	23
valid_sources[0x3b]	4003	1			T3	2		T6	8		T7	4
valid_sources[0x3c]	3523	1			T3	1		T6	6		T7	14
valid_sources[0x3d]	3808	1			T3	2		T6	18		T7	25
valid_sources[0x3e]	4225	1			T3	4		T6	6		T7	44
valid_sources[0x3f]	3661	1			T3	8		T6	27		T7	3
valid_sources[0x40]	3346	1			T6	5		T7	5		T12	74
valid_sources[0x41]	4005	1			T3	4		T6	28		T7	1
valid_sources[0x42]	3721	1			T3	6		T6	12		T7	7
valid_sources[0x43]	3266	1			T3	3		T6	19		T7	7
valid_sources[0x44]	4717	1			T1	1		T3	3		T6	12
valid_sources[0x45]	3965	1			T3	3		T6	6		T7	23
valid_sources[0x46]	4093	1			T3	1		T6	23		T8	3
valid_sources[0x47]	4235	1			T3	5		T6	7		T7	9
valid_sources[0x48]	4925	1			T3	4		T4	2		T6	11
valid_sources[0x49]	3718	1			T3	4		T6	7		T12	54
valid_sources[0x4a]	3587	1			T3	3		T6	13		T7	8
valid_sources[0x4b]	6393	1			T3	5		T6	13		T7	1
valid_sources[0x4c]	3333	1			T3	6		T6	21		T7	19
valid_sources[0x4d]	3403	1			T6	12		T8	4		T12	81
valid_sources[0x4e]	4040	1			T3	2		T4	1		T6	12
valid_sources[0x4f]	3564	1			T3	2		T6	16		T7	7
valid_sources[0x50]	3682	1			T3	10		T6	12		T8	2
valid_sources[0x51]	4693	1			T6	11		T7	5		T8	3
valid_sources[0x52]	3142	1			T3	9		T6	17		T8	1
valid_sources[0x53]	3974	1			T3	2		T6	9		T8	3
valid_sources[0x54]	3522	1			T3	4		T6	13		T7	4
valid_sources[0x55]	5606	1			T3	2		T4	1		T6	21
valid_sources[0x56]	3543	1			T3	3		T6	17		T7	5
valid_sources[0x57]	4039	1			T3	5		T6	15		T7	15
valid_sources[0x58]	3775	1			T3	3		T6	7		T7	7
valid_sources[0x59]	3526	1			T3	6		T6	21		T7	19
valid_sources[0x5a]	3844	1			T3	4		T6	21		T7	1
valid_sources[0x5b]	6958	1			T1	19		T3	4		T6	22
valid_sources[0x5c]	3814	1			T1	17		T3	5		T6	18
valid_sources[0x5d]	3519	1			T3	1		T6	23		T7	7
valid_sources[0x5e]	3861	1			T3	3		T6	16		T7	10
valid_sources[0x5f]	3753	1			T3	3		T6	30		T7	16
valid_sources[0x60]	3976	1			T3	4		T6	21		T8	1
valid_sources[0x61]	3774	1			T3	1		T4	1		T6	11
valid_sources[0x62]	3633	1			T3	6		T6	18		T7	28
valid_sources[0x63]	3975	1			T3	4		T6	8		T7	13
valid_sources[0x64]	3876	1			T3	3		T6	21		T7	16
valid_sources[0x65]	3776	1			T3	4		T6	17		T7	14
valid_sources[0x66]	3393	1			T3	4		T6	12		T7	18
valid_sources[0x67]	3988	1			T3	3		T4	1		T6	9
valid_sources[0x68]	4400	1			T3	3		T6	34		T7	14
valid_sources[0x69]	3881	1			T3	6		T6	10		T7	6
valid_sources[0x6a]	3685	1			T3	3		T6	9		T7	17
valid_sources[0x6b]	5183	1			T3	3		T6	11		T7	2
valid_sources[0x6c]	3357	1			T3	3		T6	20		T12	102
valid_sources[0x6d]	3512	1			T3	6		T6	5		T7	26
valid_sources[0x6e]	4113	1			T3	5		T6	18		T7	7
valid_sources[0x6f]	3733	1			T3	2		T6	22		T7	14
valid_sources[0x70]	3892	1			T3	5		T4	1		T6	18
valid_sources[0x71]	3443	1			T4	1		T6	11		T7	36
valid_sources[0x72]	6754	1			T3	5		T6	13		T7	12
valid_sources[0x73]	3601	1			T3	4		T6	12		T7	14
valid_sources[0x74]	5524	1			T3	4		T6	14		T7	5
valid_sources[0x75]	3700	1			T3	4		T6	18		T7	12
valid_sources[0x76]	3384	1			T3	2		T6	11		T7	8
valid_sources[0x77]	3319	1			T3	7		T6	14		T7	18
valid_sources[0x78]	3604	1			T3	1		T6	15		T7	2
valid_sources[0x79]	3340	1			T3	3		T4	1		T6	15
valid_sources[0x7a]	3181	1			T3	3		T6	20		T7	21
valid_sources[0x7b]	3650	1			T3	6		T6	11		T7	11
valid_sources[0x7c]	3469	1			T3	3		T6	14		T7	18
valid_sources[0x7d]	3559	1			T3	4		T6	19		T7	23
valid_sources[0x7e]	3951	1			T3	3		T4	1		T6	23
valid_sources[0x7f]	3636	1			T3	6		T6	10		T7	5
valid_sources[0x80]	3790	1			T3	5		T6	17		T7	11

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

248741

1

T1

41

T3

250

T4

2

values[0x0]

all_enables

biggest_size

81758

1

T1

25

T3

82

T4

5

values[0x1]

all_enables

biggest_size

43518

1

T1

9

T3

35

T6

156