Unified Coverage Report :: Module :: rstmgr_cascading_sva_if

Module : rstmgr_cascading_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_cascading_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_cascading_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_cascading_sva_if

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	100	1	1	100.00
ALWAYS	103	1	1	100.00
ALWAYS	107	1	1	100.00
ALWAYS	127	1	1	100.00
ALWAYS	138	1	1	100.00
ALWAYS	141	1	1	100.00
ALWAYS	144	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
100	1	1
103	1	1
107	1	1
127	1	1
138	1	1
141	1	1
144	1	1

---

Cond Coverage for Module : rstmgr_cascading_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       103
 EXPRESSION (((!scanmode)) || scan_rst_ni)
             ------1------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T9
0	1	Covered	T6,T7,T9
1	0	Covered	T6,T7,T9

 LINE       107
 EXPRESSION (por_n_i[rstmgr_pkg::DomainAonSel] && ((!scanmode)))
             ----------------1----------------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T6
1	0	Covered	T6,T7,T9
1	1	Covered	T1,T2,T3

---

Assert Coverage for Module : rstmgr_cascading_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	31	31	100.00	31	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	31	31	100.00	31	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CascadeEffAonToRstPorAboveFall_A	54685509	8882	0	0
CascadeEffAonToRstPorAboveRise_A	54685509	8882	0	0
CascadeEffAonToRstPorIoAboveFall_A	52496300	8882	0	0
CascadeEffAonToRstPorIoAboveRise_A	52496300	8882	0	0
CascadeEffAonToRstPorIoDiv2AboveFall_A	26248819	8882	0	0
CascadeEffAonToRstPorIoDiv2AboveRise_A	26248819	8882	0	0
CascadeEffAonToRstPorIoDiv4AboveFall_A	13124236	8882	0	0
CascadeEffAonToRstPorIoDiv4AboveRise_A	13124236	8882	0	0
CascadeEffAonToRstPorUcbAboveFall_A	26249152	8882	0	0
CascadeEffAonToRstPorUcbAboveRise_A	26249152	8882	0	0
CascadeLcToLcAboveFall_A	54685509	22048	0	0
CascadeLcToLcAboveRise_A	54685509	22048	0	0
CascadeLcToLcAonAboveFall_A	1657574	22048	0	0
CascadeLcToLcAonAboveRise_A	1657574	22048	0	0
CascadeLcToLcShadowedAboveFall_A	54685509	22048	0	0
CascadeLcToLcShadowedAboveRise_A	54685509	22048	0	0
CascadePorToAonAboveFall_A	1657574	7044	0	0
CascadeSysToSysAboveFall_A	54685509	22048	0	0
CascadeSysToSysAboveRise_A	54685509	22048	0	0
ScanRstToAonRise_A	1657574	224	0	0
StablePorToAonRise_A	1657574	8882	0	0
g_power_domains[0].CascadeLcToSysAboveFall_A	11645620	22048	0	0
g_power_domains[0].CascadeLcToSysAboveRise_A	11645620	22048	0	0
g_power_domains[0].CascadeLocalRstToLcAboveFall_A	11645620	22048	0	0
g_power_domains[0].CascadeLocalRstToLcAboveRise_A	11645620	22048	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A	13124236	22048	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A	13124236	22048	0	0
g_power_domains[1].CascadeLcToSysAboveFall_A	11645620	22048	0	0
g_power_domains[1].CascadeLcToSysAboveRise_A	11645620	22048	0	0
g_power_domains[1].CascadeLocalRstToLcAboveFall_A	11645620	22048	0	0
g_power_domains[1].CascadeLocalRstToLcAboveRise_A	11645620	22048	0	0

CascadeEffAonToRstPorAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54685509	8882	0	0
T1	15830	1	0	0
T2	15265	2	0	0
T3	46603	1	0	0
T4	6033	1	0	0
T5	24314	8	0	0
T6	128322	25	0	0
T7	97820	21	0	0
T8	23930	1	0	0
T9	84759	18	0	0
T10	18520	2	0	0

CascadeEffAonToRstPorAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54685509	8882	0	0
T1	15830	1	0	0
T2	15265	2	0	0
T3	46603	1	0	0
T4	6033	1	0	0
T5	24314	8	0	0
T6	128322	25	0	0
T7	97820	21	0	0
T8	23930	1	0	0
T9	84759	18	0	0
T10	18520	2	0	0

CascadeEffAonToRstPorIoAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52496300	8882	0	0
T1	15197	1	0	0
T2	14654	2	0	0
T3	44739	1	0	0
T4	5791	1	0	0
T5	23337	8	0	0
T6	123167	25	0	0
T7	93910	21	0	0
T8	22973	1	0	0
T9	81368	18	0	0
T10	17776	2	0	0

CascadeEffAonToRstPorIoAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52496300	8882	0	0
T1	15197	1	0	0
T2	14654	2	0	0
T3	44739	1	0	0
T4	5791	1	0	0
T5	23337	8	0	0
T6	123167	25	0	0
T7	93910	21	0	0
T8	22973	1	0	0
T9	81368	18	0	0
T10	17776	2	0	0

CascadeEffAonToRstPorIoDiv2AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26248819	8882	0	0
T1	7599	1	0	0
T2	7326	2	0	0
T3	22369	1	0	0
T4	2896	1	0	0
T5	11672	8	0	0
T6	61587	25	0	0
T7	46938	21	0	0
T8	11485	1	0	0
T9	40686	18	0	0
T10	8888	2	0	0

CascadeEffAonToRstPorIoDiv2AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26248819	8882	0	0
T1	7599	1	0	0
T2	7326	2	0	0
T3	22369	1	0	0
T4	2896	1	0	0
T5	11672	8	0	0
T6	61587	25	0	0
T7	46938	21	0	0
T8	11485	1	0	0
T9	40686	18	0	0
T10	8888	2	0	0

CascadeEffAonToRstPorIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13124236	8882	0	0
T1	3799	1	0	0
T2	3662	2	0	0
T3	11183	1	0	0
T4	1448	1	0	0
T5	5832	8	0	0
T6	30788	25	0	0
T7	23472	21	0	0
T8	5742	1	0	0
T9	20343	18	0	0
T10	4444	2	0	0

CascadeEffAonToRstPorIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13124236	8882	0	0
T1	3799	1	0	0
T2	3662	2	0	0
T3	11183	1	0	0
T4	1448	1	0	0
T5	5832	8	0	0
T6	30788	25	0	0
T7	23472	21	0	0
T8	5742	1	0	0
T9	20343	18	0	0
T10	4444	2	0	0

CascadeEffAonToRstPorUcbAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26249152	8882	0	0
T1	7599	1	0	0
T2	7326	2	0	0
T3	22370	1	0	0
T4	2895	1	0	0
T5	11665	8	0	0
T6	61590	25	0	0
T7	46954	21	0	0
T8	11486	1	0	0
T9	40681	18	0	0
T10	8887	2	0	0

CascadeEffAonToRstPorUcbAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26249152	8882	0	0
T1	7599	1	0	0
T2	7326	2	0	0
T3	22370	1	0	0
T4	2895	1	0	0
T5	11665	8	0	0
T6	61590	25	0	0
T7	46954	21	0	0
T8	11486	1	0	0
T9	40681	18	0	0
T10	8887	2	0	0

CascadeLcToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54685509	22048	0	0
T1	15830	11	0	0
T2	15265	2	0	0
T3	46603	1	0	0
T4	6033	2	0	0
T5	24314	8	0	0
T6	128322	73	0	0
T7	97820	59	0	0
T8	23930	16	0	0
T9	84759	52	0	0
T10	18520	6	0	0

CascadeLcToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54685509	22048	0	0
T1	15830	11	0	0
T2	15265	2	0	0
T3	46603	1	0	0
T4	6033	2	0	0
T5	24314	8	0	0
T6	128322	73	0	0
T7	97820	59	0	0
T8	23930	16	0	0
T9	84759	52	0	0
T10	18520	6	0	0

CascadeLcToLcAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1657574	22048	0	0
T1	474	11	0	0
T2	456	2	0	0
T3	1397	1	0	0
T4	180	2	0	0
T5	731	8	0	0
T6	3883	73	0	0
T7	3016	59	0	0
T8	717	16	0	0
T9	2630	52	0	0
T10	555	6	0	0

CascadeLcToLcAonAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1657574	22048	0	0
T1	474	11	0	0
T2	456	2	0	0
T3	1397	1	0	0
T4	180	2	0	0
T5	731	8	0	0
T6	3883	73	0	0
T7	3016	59	0	0
T8	717	16	0	0
T9	2630	52	0	0
T10	555	6	0	0

CascadeLcToLcShadowedAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54685509	22048	0	0
T1	15830	11	0	0
T2	15265	2	0	0
T3	46603	1	0	0
T4	6033	2	0	0
T5	24314	8	0	0
T6	128322	73	0	0
T7	97820	59	0	0
T8	23930	16	0	0
T9	84759	52	0	0
T10	18520	6	0	0

CascadeLcToLcShadowedAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54685509	22048	0	0
T1	15830	11	0	0
T2	15265	2	0	0
T3	46603	1	0	0
T4	6033	2	0	0
T5	24314	8	0	0
T6	128322	73	0	0
T7	97820	59	0	0
T8	23930	16	0	0
T9	84759	52	0	0
T10	18520	6	0	0

CascadePorToAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1657574	7044	0	0
T1	474	1	0	0
T2	456	12	0	0
T3	1397	1	0	0
T4	180	1	0	0
T5	731	8	0	0
T6	3883	11	0	0
T7	3016	13	0	0
T8	717	1	0	0
T9	2630	10	0	0
T10	555	1	0	0

CascadeSysToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54685509	22048	0	0
T1	15830	11	0	0
T2	15265	2	0	0
T3	46603	1	0	0
T4	6033	2	0	0
T5	24314	8	0	0
T6	128322	73	0	0
T7	97820	59	0	0
T8	23930	16	0	0
T9	84759	52	0	0
T10	18520	6	0	0

CascadeSysToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54685509	22048	0	0
T1	15830	11	0	0
T2	15265	2	0	0
T3	46603	1	0	0
T4	6033	2	0	0
T5	24314	8	0	0
T6	128322	73	0	0
T7	97820	59	0	0
T8	23930	16	0	0
T9	84759	52	0	0
T10	18520	6	0	0

ScanRstToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1657574	224	0	0
T6	3883	1	0	0
T7	3016	0	0	0
T8	717	0	0	0
T9	2630	0	0	0
T10	555	0	0	0
T11	5778	0	0	0
T12	31199	8	0	0
T22	5522	2	0	0
T48	0	4	0	0
T51	0	9	0	0
T52	6406	2	0	0
T53	222	0	0	0
T73	0	1	0	0
T80	0	6	0	0
T93	0	4	0	0
T123	0	2	0	0

StablePorToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1657574	8882	0	0
T1	474	1	0	0
T2	456	2	0	0
T3	1397	1	0	0
T4	180	1	0	0
T5	731	8	0	0
T6	3883	25	0	0
T7	3016	21	0	0
T8	717	1	0	0
T9	2630	18	0	0
T10	555	2	0	0

g_power_domains[0].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11645620	22048	0	0
T1	3094	11	0	0
T2	3524	2	0	0
T3	11118	1	0	0
T4	1326	2	0	0
T5	5482	8	0	0
T6	24255	73	0	0
T7	18436	59	0	0
T8	4760	16	0	0
T9	15968	52	0	0
T10	4154	6	0	0

g_power_domains[0].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11645620	22048	0	0
T1	3094	11	0	0
T2	3524	2	0	0
T3	11118	1	0	0
T4	1326	2	0	0
T5	5482	8	0	0
T6	24255	73	0	0
T7	18436	59	0	0
T8	4760	16	0	0
T9	15968	52	0	0
T10	4154	6	0	0

g_power_domains[0].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11645620	22048	0	0
T1	3094	11	0	0
T2	3524	2	0	0
T3	11118	1	0	0
T4	1326	2	0	0
T5	5482	8	0	0
T6	24255	73	0	0
T7	18436	59	0	0
T8	4760	16	0	0
T9	15968	52	0	0
T10	4154	6	0	0

g_power_domains[0].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11645620	22048	0	0
T1	3094	11	0	0
T2	3524	2	0	0
T3	11118	1	0	0
T4	1326	2	0	0
T5	5482	8	0	0
T6	24255	73	0	0
T7	18436	59	0	0
T8	4760	16	0	0
T9	15968	52	0	0
T10	4154	6	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13124236	22048	0	0
T1	3799	11	0	0
T2	3662	2	0	0
T3	11183	1	0	0
T4	1448	2	0	0
T5	5832	8	0	0
T6	30788	73	0	0
T7	23472	59	0	0
T8	5742	16	0	0
T9	20343	52	0	0
T10	4444	6	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13124236	22048	0	0
T1	3799	11	0	0
T2	3662	2	0	0
T3	11183	1	0	0
T4	1448	2	0	0
T5	5832	8	0	0
T6	30788	73	0	0
T7	23472	59	0	0
T8	5742	16	0	0
T9	20343	52	0	0
T10	4444	6	0	0

g_power_domains[1].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11645620	22048	0	0
T1	3094	11	0	0
T2	3524	2	0	0
T3	11118	1	0	0
T4	1326	2	0	0
T5	5482	8	0	0
T6	24255	73	0	0
T7	18436	59	0	0
T8	4760	16	0	0
T9	15968	52	0	0
T10	4154	6	0	0

g_power_domains[1].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11645620	22048	0	0
T1	3094	11	0	0
T2	3524	2	0	0
T3	11118	1	0	0
T4	1326	2	0	0
T5	5482	8	0	0
T6	24255	73	0	0
T7	18436	59	0	0
T8	4760	16	0	0
T9	15968	52	0	0
T10	4154	6	0	0

g_power_domains[1].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11645620	22048	0	0
T1	3094	11	0	0
T2	3524	2	0	0
T3	11118	1	0	0
T4	1326	2	0	0
T5	5482	8	0	0
T6	24255	73	0	0
T7	18436	59	0	0
T8	4760	16	0	0
T9	15968	52	0	0
T10	4154	6	0	0

g_power_domains[1].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11645620	22048	0	0
T1	3094	11	0	0
T2	3524	2	0	0
T3	11118	1	0	0
T4	1326	2	0	0
T5	5482	8	0	0
T6	24255	73	0	0
T7	18436	59	0	0
T8	4760	16	0	0
T9	15968	52	0	0
T10	4154	6	0	0