Unified Coverage Report :: Module :: rstmgr_sw_rst_sva_if

Module : rstmgr_sw_rst_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_sw_rst_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_sw_rst_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_sw_rst_sva_if

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
21	8	8

---

Cond Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Covered	Percent
Conditions	24	24	100.00
Logical	24	24	100.00
Non-Logical	0	0
Event	0	0

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[0])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[1])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T6,T12
1	0	Covered	T1,T2,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[2])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T6,T12
1	0	Covered	T1,T2,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[3])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T6,T12
1	0	Covered	T1,T2,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[4])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T6,T12
1	0	Covered	T1,T2,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[5])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T6,T12
1	0	Covered	T1,T2,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[6])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T6,T12
1	0	Covered	T1,T2,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[7])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T6,T12
1	0	Covered	T1,T2,T4

---

Assert Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions[0].RstEnOff_A	13124236	14065	0	0
gen_assertions[0].RstEnOn_A	13124236	1085	0	0
gen_assertions[0].RstNOff_A	13124236	14065	0	0
gen_assertions[0].RstNOn_A	13124236	1085	0	0
gen_assertions[1].RstEnOff_A	52496300	12801	0	0
gen_assertions[1].RstEnOn_A	52496300	1032	0	0
gen_assertions[1].RstNOff_A	52496300	12801	0	0
gen_assertions[1].RstNOn_A	52496300	1032	0	0
gen_assertions[2].RstEnOff_A	26248819	12841	0	0
gen_assertions[2].RstEnOn_A	26248819	999	0	0
gen_assertions[2].RstNOff_A	26248819	12841	0	0
gen_assertions[2].RstNOn_A	26248819	999	0	0
gen_assertions[3].RstEnOff_A	26249152	12925	0	0
gen_assertions[3].RstEnOn_A	26249152	1076	0	0
gen_assertions[3].RstNOff_A	26249152	12925	0	0
gen_assertions[3].RstNOn_A	26249152	1076	0	0
gen_assertions[4].RstEnOff_A	1657574	21895	0	0
gen_assertions[4].RstEnOn_A	1657574	1159	0	0
gen_assertions[4].RstNOff_A	1657574	21895	0	0
gen_assertions[4].RstNOn_A	1657574	1159	0	0
gen_assertions[5].RstEnOff_A	13124236	14326	0	0
gen_assertions[5].RstEnOn_A	13124236	1199	0	0
gen_assertions[5].RstNOff_A	13124236	14326	0	0
gen_assertions[5].RstNOn_A	13124236	1199	0	0
gen_assertions[6].RstEnOff_A	13124236	14349	0	0
gen_assertions[6].RstEnOn_A	13124236	1221	0	0
gen_assertions[6].RstNOff_A	13124236	14349	0	0
gen_assertions[6].RstNOn_A	13124236	1221	0	0
gen_assertions[7].RstEnOff_A	13124236	14419	0	0
gen_assertions[7].RstEnOn_A	13124236	1289	0	0
gen_assertions[7].RstNOff_A	13124236	14419	0	0
gen_assertions[7].RstNOn_A	13124236	1289	0	0

gen_assertions[0].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13124236	14065	0	0
T1	3799	10	0	0
T2	3662	0	0	0
T3	11183	5	0	0
T4	1448	1	0	0
T5	5832	0	0	0
T6	30788	54	0	0
T7	23472	38	0	0
T8	5742	15	0	0
T9	20343	34	0	0
T10	4444	4	0	0
T11	0	46	0	0
T12	0	264	0	0

gen_assertions[0].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13124236	1085	0	0
T1	3799	2	0	0
T2	3662	0	0	0
T3	11183	5	0	0
T4	1448	1	0	0
T5	5832	0	0	0
T6	30788	6	0	0
T7	23472	0	0	0
T8	5742	4	0	0
T9	20343	0	0	0
T10	4444	0	0	0
T12	0	4	0	0
T36	0	2	0	0
T38	0	9	0	0
T46	0	1	0	0
T48	0	10	0	0

gen_assertions[0].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13124236	14065	0	0
T1	3799	10	0	0
T2	3662	0	0	0
T3	11183	5	0	0
T4	1448	1	0	0
T5	5832	0	0	0
T6	30788	54	0	0
T7	23472	38	0	0
T8	5742	15	0	0
T9	20343	34	0	0
T10	4444	4	0	0
T11	0	46	0	0
T12	0	264	0	0

gen_assertions[0].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13124236	1085	0	0
T1	3799	2	0	0
T2	3662	0	0	0
T3	11183	5	0	0
T4	1448	1	0	0
T5	5832	0	0	0
T6	30788	6	0	0
T7	23472	0	0	0
T8	5742	4	0	0
T9	20343	0	0	0
T10	4444	0	0	0
T12	0	4	0	0
T36	0	2	0	0
T38	0	9	0	0
T46	0	1	0	0
T48	0	10	0	0

gen_assertions[1].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52496300	12801	0	0
T1	15197	9	0	0
T2	14654	0	0	0
T3	44739	7	0	0
T4	5791	1	0	0
T5	23337	0	0	0
T6	123167	46	0	0
T7	93910	33	0	0
T8	22973	12	0	0
T9	81368	31	0	0
T10	17776	4	0	0
T11	0	42	0	0
T12	0	246	0	0

gen_assertions[1].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52496300	1032	0	0
T3	44739	7	0	0
T4	5791	0	0	0
T5	23337	0	0	0
T6	123167	3	0	0
T7	93910	0	0	0
T8	22973	0	0	0
T9	81368	0	0	0
T10	17776	0	0	0
T11	183408	0	0	0
T12	982913	3	0	0
T38	0	9	0	0
T46	0	2	0	0
T48	0	13	0	0
T50	0	3	0	0
T51	0	7	0	0
T79	0	4	0	0
T80	0	4	0	0

gen_assertions[1].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52496300	12801	0	0
T1	15197	9	0	0
T2	14654	0	0	0
T3	44739	7	0	0
T4	5791	1	0	0
T5	23337	0	0	0
T6	123167	46	0	0
T7	93910	33	0	0
T8	22973	12	0	0
T9	81368	31	0	0
T10	17776	4	0	0
T11	0	42	0	0
T12	0	246	0	0

gen_assertions[1].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52496300	1032	0	0
T3	44739	7	0	0
T4	5791	0	0	0
T5	23337	0	0	0
T6	123167	3	0	0
T7	93910	0	0	0
T8	22973	0	0	0
T9	81368	0	0	0
T10	17776	0	0	0
T11	183408	0	0	0
T12	982913	3	0	0
T38	0	9	0	0
T46	0	2	0	0
T48	0	13	0	0
T50	0	3	0	0
T51	0	7	0	0
T79	0	4	0	0
T80	0	4	0	0

gen_assertions[2].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26248819	12841	0	0
T1	7599	9	0	0
T2	7326	0	0	0
T3	22369	7	0	0
T4	2896	1	0	0
T5	11672	0	0	0
T6	61587	48	0	0
T7	46938	33	0	0
T8	11485	12	0	0
T9	40686	31	0	0
T10	8888	4	0	0
T11	0	42	0	0
T12	0	246	0	0

gen_assertions[2].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26248819	999	0	0
T3	22369	7	0	0
T4	2896	0	0	0
T5	11672	0	0	0
T6	61587	5	0	0
T7	46938	0	0	0
T8	11485	0	0	0
T9	40686	0	0	0
T10	8888	0	0	0
T11	91705	0	0	0
T12	491458	3	0	0
T38	0	1	0	0
T46	0	4	0	0
T48	0	9	0	0
T50	0	7	0	0
T51	0	8	0	0
T79	0	7	0	0
T81	0	1	0	0

gen_assertions[2].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26248819	12841	0	0
T1	7599	9	0	0
T2	7326	0	0	0
T3	22369	7	0	0
T4	2896	1	0	0
T5	11672	0	0	0
T6	61587	48	0	0
T7	46938	33	0	0
T8	11485	12	0	0
T9	40686	31	0	0
T10	8888	4	0	0
T11	0	42	0	0
T12	0	246	0	0

gen_assertions[2].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26248819	999	0	0
T3	22369	7	0	0
T4	2896	0	0	0
T5	11672	0	0	0
T6	61587	5	0	0
T7	46938	0	0	0
T8	11485	0	0	0
T9	40686	0	0	0
T10	8888	0	0	0
T11	91705	0	0	0
T12	491458	3	0	0
T38	0	1	0	0
T46	0	4	0	0
T48	0	9	0	0
T50	0	7	0	0
T51	0	8	0	0
T79	0	7	0	0
T81	0	1	0	0

gen_assertions[3].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26249152	12925	0	0
T1	7599	9	0	0
T2	7326	0	0	0
T3	22370	6	0	0
T4	2895	1	0	0
T5	11665	0	0	0
T6	61590	47	0	0
T7	46954	33	0	0
T8	11486	12	0	0
T9	40681	31	0	0
T10	8887	4	0	0
T11	0	42	0	0
T12	0	244	0	0

gen_assertions[3].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26249152	1076	0	0
T3	22370	6	0	0
T4	2895	0	0	0
T5	11665	0	0	0
T6	61590	4	0	0
T7	46954	0	0	0
T8	11486	0	0	0
T9	40681	0	0	0
T10	8887	0	0	0
T11	91707	0	0	0
T12	491454	2	0	0
T46	0	5	0	0
T48	0	12	0	0
T50	0	5	0	0
T51	0	9	0	0
T79	0	8	0	0
T80	0	6	0	0
T82	0	1	0	0

gen_assertions[3].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26249152	12925	0	0
T1	7599	9	0	0
T2	7326	0	0	0
T3	22370	6	0	0
T4	2895	1	0	0
T5	11665	0	0	0
T6	61590	47	0	0
T7	46954	33	0	0
T8	11486	12	0	0
T9	40681	31	0	0
T10	8887	4	0	0
T11	0	42	0	0
T12	0	244	0	0

gen_assertions[3].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26249152	1076	0	0
T3	22370	6	0	0
T4	2895	0	0	0
T5	11665	0	0	0
T6	61590	4	0	0
T7	46954	0	0	0
T8	11486	0	0	0
T9	40681	0	0	0
T10	8887	0	0	0
T11	91707	0	0	0
T12	491454	2	0	0
T46	0	5	0	0
T48	0	12	0	0
T50	0	5	0	0
T51	0	9	0	0
T79	0	8	0	0
T80	0	6	0	0
T82	0	1	0	0

gen_assertions[4].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1657574	21895	0	0
T1	474	11	0	0
T2	456	2	0	0
T3	1397	8	0	0
T4	180	2	0	0
T5	731	2	0	0
T6	3883	76	0	0
T7	3016	59	0	0
T8	717	16	0	0
T9	2630	52	0	0
T10	555	6	0	0

gen_assertions[4].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1657574	1159	0	0
T3	1397	7	0	0
T4	180	0	0	0
T5	731	0	0	0
T6	3883	6	0	0
T7	3016	0	0	0
T8	717	0	0	0
T9	2630	0	0	0
T10	555	0	0	0
T11	5778	0	0	0
T12	31199	5	0	0
T46	0	6	0	0
T48	0	9	0	0
T50	0	8	0	0
T51	0	9	0	0
T79	0	8	0	0
T80	0	3	0	0
T81	0	1	0	0

gen_assertions[4].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1657574	21895	0	0
T1	474	11	0	0
T2	456	2	0	0
T3	1397	8	0	0
T4	180	2	0	0
T5	731	2	0	0
T6	3883	76	0	0
T7	3016	59	0	0
T8	717	16	0	0
T9	2630	52	0	0
T10	555	6	0	0

gen_assertions[4].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1657574	1159	0	0
T3	1397	7	0	0
T4	180	0	0	0
T5	731	0	0	0
T6	3883	6	0	0
T7	3016	0	0	0
T8	717	0	0	0
T9	2630	0	0	0
T10	555	0	0	0
T11	5778	0	0	0
T12	31199	5	0	0
T46	0	6	0	0
T48	0	9	0	0
T50	0	8	0	0
T51	0	9	0	0
T79	0	8	0	0
T80	0	3	0	0
T81	0	1	0	0

gen_assertions[5].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13124236	14326	0	0
T1	3799	10	0	0
T2	3662	0	0	0
T3	11183	10	0	0
T4	1448	1	0	0
T5	5832	0	0	0
T6	30788	52	0	0
T7	23472	38	0	0
T8	5742	15	0	0
T9	20343	34	0	0
T10	4444	4	0	0
T11	0	46	0	0
T12	0	265	0	0

gen_assertions[5].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13124236	1199	0	0
T3	11183	10	0	0
T4	1448	0	0	0
T5	5832	0	0	0
T6	30788	4	0	0
T7	23472	0	0	0
T8	5742	0	0	0
T9	20343	0	0	0
T10	4444	0	0	0
T11	45846	0	0	0
T12	245731	5	0	0
T46	0	7	0	0
T48	0	12	0	0
T50	0	8	0	0
T51	0	8	0	0
T79	0	9	0	0
T80	0	6	0	0
T82	0	1	0	0

gen_assertions[5].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13124236	14326	0	0
T1	3799	10	0	0
T2	3662	0	0	0
T3	11183	10	0	0
T4	1448	1	0	0
T5	5832	0	0	0
T6	30788	52	0	0
T7	23472	38	0	0
T8	5742	15	0	0
T9	20343	34	0	0
T10	4444	4	0	0
T11	0	46	0	0
T12	0	265	0	0

gen_assertions[5].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13124236	1199	0	0
T3	11183	10	0	0
T4	1448	0	0	0
T5	5832	0	0	0
T6	30788	4	0	0
T7	23472	0	0	0
T8	5742	0	0	0
T9	20343	0	0	0
T10	4444	0	0	0
T11	45846	0	0	0
T12	245731	5	0	0
T46	0	7	0	0
T48	0	12	0	0
T50	0	8	0	0
T51	0	8	0	0
T79	0	9	0	0
T80	0	6	0	0
T82	0	1	0	0

gen_assertions[6].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13124236	14349	0	0
T1	3799	10	0	0
T2	3662	0	0	0
T3	11183	10	0	0
T4	1448	1	0	0
T5	5832	0	0	0
T6	30788	53	0	0
T7	23472	38	0	0
T8	5742	15	0	0
T9	20343	34	0	0
T10	4444	4	0	0
T11	0	46	0	0
T12	0	264	0	0

gen_assertions[6].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13124236	1221	0	0
T3	11183	10	0	0
T4	1448	0	0	0
T5	5832	0	0	0
T6	30788	5	0	0
T7	23472	0	0	0
T8	5742	0	0	0
T9	20343	0	0	0
T10	4444	0	0	0
T11	45846	0	0	0
T12	245731	3	0	0
T46	0	8	0	0
T48	0	11	0	0
T50	0	10	0	0
T51	0	9	0	0
T79	0	10	0	0
T80	0	4	0	0
T83	0	8	0	0

gen_assertions[6].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13124236	14349	0	0
T1	3799	10	0	0
T2	3662	0	0	0
T3	11183	10	0	0
T4	1448	1	0	0
T5	5832	0	0	0
T6	30788	53	0	0
T7	23472	38	0	0
T8	5742	15	0	0
T9	20343	34	0	0
T10	4444	4	0	0
T11	0	46	0	0
T12	0	264	0	0

gen_assertions[6].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13124236	1221	0	0
T3	11183	10	0	0
T4	1448	0	0	0
T5	5832	0	0	0
T6	30788	5	0	0
T7	23472	0	0	0
T8	5742	0	0	0
T9	20343	0	0	0
T10	4444	0	0	0
T11	45846	0	0	0
T12	245731	3	0	0
T46	0	8	0	0
T48	0	11	0	0
T50	0	10	0	0
T51	0	9	0	0
T79	0	10	0	0
T80	0	4	0	0
T83	0	8	0	0

gen_assertions[7].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13124236	14419	0	0
T1	3799	10	0	0
T2	3662	0	0	0
T3	11183	13	0	0
T4	1448	1	0	0
T5	5832	0	0	0
T6	30788	55	0	0
T7	23472	38	0	0
T8	5742	15	0	0
T9	20343	34	0	0
T10	4444	4	0	0
T11	0	46	0	0
T12	0	265	0	0

gen_assertions[7].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13124236	1289	0	0
T3	11183	13	0	0
T4	1448	0	0	0
T5	5832	0	0	0
T6	30788	7	0	0
T7	23472	0	0	0
T8	5742	0	0	0
T9	20343	0	0	0
T10	4444	0	0	0
T11	45846	0	0	0
T12	245731	5	0	0
T46	0	8	0	0
T48	0	10	0	0
T50	0	12	0	0
T51	0	5	0	0
T79	0	13	0	0
T80	0	6	0	0
T82	0	1	0	0

gen_assertions[7].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13124236	14419	0	0
T1	3799	10	0	0
T2	3662	0	0	0
T3	11183	13	0	0
T4	1448	1	0	0
T5	5832	0	0	0
T6	30788	55	0	0
T7	23472	38	0	0
T8	5742	15	0	0
T9	20343	34	0	0
T10	4444	4	0	0
T11	0	46	0	0
T12	0	265	0	0

gen_assertions[7].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13124236	1289	0	0
T3	11183	13	0	0
T4	1448	0	0	0
T5	5832	0	0	0
T6	30788	7	0	0
T7	23472	0	0	0
T8	5742	0	0	0
T9	20343	0	0	0
T10	4444	0	0	0
T11	45846	0	0	0
T12	245731	5	0	0
T46	0	8	0	0
T48	0	10	0	0
T50	0	12	0	0
T51	0	5	0	0
T79	0	13	0	0
T80	0	6	0	0
T82	0	1	0	0