Unified Coverage Report :: Module :: rstmgr_csr_assert_fpv

Module : rstmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rstmgr_csr_assert_0/rstmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rstmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rstmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	19	19	100.00	19	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	19	19	100.00	19	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	12421119	9207	0	0
alert_regwen_rd_A	12421119	4383	0	0
cpu_regwen_rd_A	12421119	3986	0	0
sw_rst_ctrl_n_0_rd_A	12421119	9965	0	0
sw_rst_ctrl_n_1_rd_A	12421119	9540	0	0
sw_rst_ctrl_n_2_rd_A	12421119	9815	0	0
sw_rst_ctrl_n_3_rd_A	12421119	9703	0	0
sw_rst_ctrl_n_4_rd_A	12421119	9708	0	0
sw_rst_ctrl_n_5_rd_A	12421119	9953	0	0
sw_rst_ctrl_n_6_rd_A	12421119	9546	0	0
sw_rst_ctrl_n_7_rd_A	12421119	9659	0	0
sw_rst_regwen_0_rd_A	12421119	4641	0	0
sw_rst_regwen_1_rd_A	12421119	4567	0	0
sw_rst_regwen_2_rd_A	12421119	4531	0	0
sw_rst_regwen_3_rd_A	12421119	4709	0	0
sw_rst_regwen_4_rd_A	12421119	4724	0	0
sw_rst_regwen_5_rd_A	12421119	4399	0	0
sw_rst_regwen_6_rd_A	12421119	4406	0	0
sw_rst_regwen_7_rd_A	12421119	4499	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12421119	9207	0	0
T58	19528	3	0	0
T62	6772	226	0	0
T63	2817	161	0	0
T64	4003	10	0	0
T65	15647	1	0	0
T84	3630	217	0	0
T85	3935	152	0	0
T87	2401	54	0	0
T88	3271	18	0	0
T89	2716	33	0	0

alert_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12421119	4383	0	0
T11	40669	31	0	0
T12	214546	0	0	0
T22	38249	73	0	0
T23	26216	0	0	0
T33	5272	0	0	0
T34	1650	0	0	0
T35	5670	0	0	0
T36	3328	0	0	0
T52	44899	62	0	0
T53	1695	0	0	0
T75	0	60	0	0
T94	0	212	0	0
T95	0	170	0	0
T115	0	57	0	0
T116	0	126	0	0
T117	0	60	0	0
T118	0	178	0	0

cpu_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12421119	3986	0	0
T11	40669	57	0	0
T12	214546	0	0	0
T22	38249	57	0	0
T23	26216	0	0	0
T33	5272	0	0	0
T34	1650	0	0	0
T35	5670	0	0	0
T36	3328	0	0	0
T52	44899	48	0	0
T53	1695	0	0	0
T75	0	67	0	0
T94	0	210	0	0
T95	0	131	0	0
T115	0	37	0	0
T116	0	118	0	0
T117	0	59	0	0
T118	0	206	0	0

sw_rst_ctrl_n_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12421119	9965	0	0
T3	11118	167	0	0
T4	1326	0	0	0
T5	5482	0	0	0
T6	24255	0	0	0
T7	18436	0	0	0
T8	4760	47	0	0
T9	15968	0	0	0
T10	4154	0	0	0
T11	40669	44	0	0
T12	214546	0	0	0
T22	0	49	0	0
T36	0	37	0	0
T50	0	149	0	0
T52	0	99	0	0
T79	0	101	0	0
T119	0	28	0	0
T120	0	133	0	0

sw_rst_ctrl_n_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12421119	9540	0	0
T3	11118	133	0	0
T4	1326	0	0	0
T5	5482	0	0	0
T6	24255	0	0	0
T7	18436	0	0	0
T8	4760	58	0	0
T9	15968	0	0	0
T10	4154	0	0	0
T11	40669	71	0	0
T12	214546	0	0	0
T22	0	92	0	0
T36	0	30	0	0
T50	0	143	0	0
T52	0	67	0	0
T79	0	124	0	0
T119	0	51	0	0
T120	0	110	0	0

sw_rst_ctrl_n_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12421119	9815	0	0
T3	11118	194	0	0
T4	1326	0	0	0
T5	5482	0	0	0
T6	24255	0	0	0
T7	18436	0	0	0
T8	4760	48	0	0
T9	15968	0	0	0
T10	4154	0	0	0
T11	40669	41	0	0
T12	214546	0	0	0
T22	0	74	0	0
T36	0	12	0	0
T50	0	194	0	0
T52	0	65	0	0
T79	0	113	0	0
T119	0	26	0	0
T120	0	121	0	0

sw_rst_ctrl_n_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12421119	9703	0	0
T3	11118	208	0	0
T4	1326	0	0	0
T5	5482	0	0	0
T6	24255	0	0	0
T7	18436	0	0	0
T8	4760	55	0	0
T9	15968	0	0	0
T10	4154	0	0	0
T11	40669	59	0	0
T12	214546	0	0	0
T22	0	46	0	0
T36	0	19	0	0
T50	0	129	0	0
T52	0	77	0	0
T79	0	124	0	0
T119	0	37	0	0
T120	0	108	0	0

sw_rst_ctrl_n_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12421119	9708	0	0
T3	11118	170	0	0
T4	1326	0	0	0
T5	5482	0	0	0
T6	24255	0	0	0
T7	18436	0	0	0
T8	4760	32	0	0
T9	15968	0	0	0
T10	4154	0	0	0
T11	40669	37	0	0
T12	214546	0	0	0
T22	0	56	0	0
T36	0	18	0	0
T50	0	202	0	0
T52	0	50	0	0
T79	0	125	0	0
T119	0	45	0	0
T120	0	144	0	0

sw_rst_ctrl_n_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12421119	9953	0	0
T3	11118	173	0	0
T4	1326	0	0	0
T5	5482	0	0	0
T6	24255	0	0	0
T7	18436	0	0	0
T8	4760	57	0	0
T9	15968	0	0	0
T10	4154	0	0	0
T11	40669	37	0	0
T12	214546	0	0	0
T22	0	65	0	0
T36	0	31	0	0
T50	0	187	0	0
T52	0	67	0	0
T79	0	109	0	0
T119	0	52	0	0
T120	0	131	0	0

sw_rst_ctrl_n_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12421119	9546	0	0
T3	11118	209	0	0
T4	1326	0	0	0
T5	5482	0	0	0
T6	24255	0	0	0
T7	18436	0	0	0
T8	4760	63	0	0
T9	15968	0	0	0
T10	4154	0	0	0
T11	40669	39	0	0
T12	214546	0	0	0
T22	0	65	0	0
T36	0	38	0	0
T50	0	160	0	0
T52	0	40	0	0
T79	0	83	0	0
T119	0	46	0	0
T120	0	102	0	0

sw_rst_ctrl_n_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12421119	9659	0	0
T3	11118	204	0	0
T4	1326	0	0	0
T5	5482	0	0	0
T6	24255	0	0	0
T7	18436	0	0	0
T8	4760	44	0	0
T9	15968	0	0	0
T10	4154	0	0	0
T11	40669	47	0	0
T12	214546	0	0	0
T22	0	65	0	0
T36	0	10	0	0
T50	0	148	0	0
T52	0	83	0	0
T79	0	127	0	0
T119	0	42	0	0
T120	0	132	0	0

sw_rst_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12421119	4641	0	0
T3	11118	30	0	0
T4	1326	0	0	0
T5	5482	0	0	0
T6	24255	0	0	0
T7	18436	0	0	0
T8	4760	0	0	0
T9	15968	0	0	0
T10	4154	0	0	0
T11	40669	54	0	0
T12	214546	0	0	0
T22	0	67	0	0
T50	0	27	0	0
T52	0	59	0	0
T75	0	59	0	0
T79	0	35	0	0
T94	0	239	0	0
T120	0	37	0	0
T121	0	14	0	0

sw_rst_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12421119	4567	0	0
T3	11118	30	0	0
T4	1326	0	0	0
T5	5482	0	0	0
T6	24255	0	0	0
T7	18436	0	0	0
T8	4760	0	0	0
T9	15968	0	0	0
T10	4154	0	0	0
T11	40669	29	0	0
T12	214546	0	0	0
T22	0	56	0	0
T50	0	28	0	0
T52	0	80	0	0
T75	0	32	0	0
T79	0	8	0	0
T94	0	198	0	0
T120	0	37	0	0
T121	0	32	0	0

sw_rst_regwen_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12421119	4531	0	0
T3	11118	41	0	0
T4	1326	0	0	0
T5	5482	0	0	0
T6	24255	0	0	0
T7	18436	0	0	0
T8	4760	0	0	0
T9	15968	0	0	0
T10	4154	0	0	0
T11	40669	64	0	0
T12	214546	0	0	0
T22	0	72	0	0
T50	0	34	0	0
T52	0	80	0	0
T75	0	46	0	0
T79	0	9	0	0
T94	0	208	0	0
T120	0	19	0	0
T121	0	27	0	0

sw_rst_regwen_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12421119	4709	0	0
T3	11118	33	0	0
T4	1326	0	0	0
T5	5482	0	0	0
T6	24255	0	0	0
T7	18436	0	0	0
T8	4760	0	0	0
T9	15968	0	0	0
T10	4154	0	0	0
T11	40669	33	0	0
T12	214546	0	0	0
T22	0	65	0	0
T50	0	40	0	0
T52	0	92	0	0
T75	0	63	0	0
T79	0	29	0	0
T94	0	247	0	0
T120	0	42	0	0
T121	0	50	0	0

sw_rst_regwen_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12421119	4724	0	0
T3	11118	21	0	0
T4	1326	0	0	0
T5	5482	0	0	0
T6	24255	0	0	0
T7	18436	0	0	0
T8	4760	0	0	0
T9	15968	0	0	0
T10	4154	0	0	0
T11	40669	53	0	0
T12	214546	0	0	0
T22	0	67	0	0
T50	0	15	0	0
T52	0	62	0	0
T75	0	34	0	0
T79	0	21	0	0
T94	0	279	0	0
T120	0	43	0	0
T121	0	28	0	0

sw_rst_regwen_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12421119	4399	0	0
T3	11118	39	0	0
T4	1326	0	0	0
T5	5482	0	0	0
T6	24255	0	0	0
T7	18436	0	0	0
T8	4760	0	0	0
T9	15968	0	0	0
T10	4154	0	0	0
T11	40669	40	0	0
T12	214546	0	0	0
T22	0	79	0	0
T50	0	31	0	0
T52	0	66	0	0
T75	0	40	0	0
T79	0	25	0	0
T94	0	236	0	0
T120	0	34	0	0
T121	0	27	0	0

sw_rst_regwen_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12421119	4406	0	0
T3	11118	19	0	0
T4	1326	0	0	0
T5	5482	0	0	0
T6	24255	0	0	0
T7	18436	0	0	0
T8	4760	0	0	0
T9	15968	0	0	0
T10	4154	0	0	0
T11	40669	39	0	0
T12	214546	0	0	0
T22	0	63	0	0
T50	0	18	0	0
T52	0	71	0	0
T75	0	40	0	0
T79	0	15	0	0
T94	0	230	0	0
T120	0	36	0	0
T121	0	48	0	0

sw_rst_regwen_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12421119	4499	0	0
T3	11118	34	0	0
T4	1326	0	0	0
T5	5482	0	0	0
T6	24255	0	0	0
T7	18436	0	0	0
T8	4760	0	0	0
T9	15968	0	0	0
T10	4154	0	0	0
T11	40669	62	0	0
T12	214546	0	0	0
T22	0	76	0	0
T50	0	22	0	0
T52	0	55	0	0
T75	0	48	0	0
T79	0	24	0	0
T94	0	228	0	0
T120	0	22	0	0
T121	0	26	0	0