Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	620404	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

371441

1

T1

61

T2

2

T3

378

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	529927	1			T1	102		T3	491		T4	186
values[0x0]	230552	1			T1	61		T2	11		T3	213
values[0x1]	231366	1			T1	47		T2	15		T3	232

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	520603	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

471242

1

T1

86

T2

6

T3

467

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	4310	1			T3	2		T4	1		T7	11
valid_sources[0x01]	3473	1			T1	3		T3	6		T7	10
valid_sources[0x02]	3848	1			T3	4		T4	2		T7	10
valid_sources[0x03]	3533	1			T3	3		T4	2		T7	15
valid_sources[0x04]	4360	1			T3	2		T4	4		T7	15
valid_sources[0x05]	3429	1			T3	6		T4	2		T7	9
valid_sources[0x06]	3745	1			T3	4		T4	1		T7	11
valid_sources[0x07]	3042	1			T3	2		T7	14		T8	1
valid_sources[0x08]	2888	1			T3	3		T4	1		T7	11
valid_sources[0x09]	4268	1			T1	3		T3	2		T4	4
valid_sources[0x0a]	3856	1			T3	2		T7	16		T8	1
valid_sources[0x0b]	3071	1			T3	4		T4	1		T7	8
valid_sources[0x0c]	3007	1			T3	1		T4	3		T7	8
valid_sources[0x0d]	3694	1			T3	2		T4	4		T7	13
valid_sources[0x0e]	4221	1			T1	2		T3	2		T4	2
valid_sources[0x0f]	4952	1			T3	1		T7	13		T8	5
valid_sources[0x10]	3330	1			T1	1		T3	6		T4	1
valid_sources[0x11]	3666	1			T1	1		T3	5		T4	2
valid_sources[0x12]	2934	1			T1	3		T3	3		T4	1
valid_sources[0x13]	4003	1			T3	2		T4	2		T7	11
valid_sources[0x14]	3799	1			T3	3		T7	14		T8	3
valid_sources[0x15]	3189	1			T1	3		T3	4		T7	13
valid_sources[0x16]	6580	1			T1	3		T3	6		T7	10
valid_sources[0x17]	3292	1			T3	5		T4	5		T7	12
valid_sources[0x18]	3174	1			T3	4		T4	1		T7	14
valid_sources[0x19]	2680	1			T1	1		T3	8		T7	9
valid_sources[0x1a]	3527	1			T3	2		T4	6		T7	14
valid_sources[0x1b]	3328	1			T3	2		T4	1		T7	9
valid_sources[0x1c]	8230	1			T3	6		T4	3		T7	12
valid_sources[0x1d]	3778	1			T3	6		T7	10		T10	3
valid_sources[0x1e]	3497	1			T4	3		T7	14		T9	30
valid_sources[0x1f]	7019	1			T3	4		T4	3		T7	15
valid_sources[0x20]	3119	1			T3	7		T4	2		T7	9
valid_sources[0x21]	3106	1			T1	3		T3	9		T4	2
valid_sources[0x22]	3345	1			T3	5		T7	14		T8	2
valid_sources[0x23]	3743	1			T3	5		T4	1		T7	12
valid_sources[0x24]	3921	1			T1	2		T3	3		T4	1
valid_sources[0x25]	3484	1			T1	2		T3	6		T4	6
valid_sources[0x26]	2952	1			T3	4		T4	1		T7	21
valid_sources[0x27]	2910	1			T4	1		T7	11		T8	2
valid_sources[0x28]	2764	1			T3	3		T4	4		T7	8
valid_sources[0x29]	4662	1			T1	1		T3	3		T7	8
valid_sources[0x2a]	5014	1			T1	1		T3	3		T4	1
valid_sources[0x2b]	2918	1			T1	1		T3	6		T4	5
valid_sources[0x2c]	3306	1			T1	1		T3	3		T7	5
valid_sources[0x2d]	7897	1			T1	1		T3	4		T4	1
valid_sources[0x2e]	3882	1			T1	4		T3	3		T4	5
valid_sources[0x2f]	5178	1			T3	4		T4	3		T7	11
valid_sources[0x30]	4743	1			T3	2		T7	15		T10	3
valid_sources[0x31]	3641	1			T3	4		T7	14		T10	3
valid_sources[0x32]	3104	1			T1	1		T3	3		T7	18
valid_sources[0x33]	3213	1			T1	2		T3	4		T7	13
valid_sources[0x34]	3789	1			T3	4		T4	1		T7	15
valid_sources[0x35]	3700	1			T3	3		T4	2		T7	11
valid_sources[0x36]	4251	1			T1	3		T3	7		T4	5
valid_sources[0x37]	3186	1			T3	2		T7	14		T8	1
valid_sources[0x38]	4360	1			T1	2		T3	6		T4	3
valid_sources[0x39]	3625	1			T3	4		T4	3		T7	17
valid_sources[0x3a]	2619	1			T3	3		T7	13		T8	1
valid_sources[0x3b]	3453	1			T1	1		T3	4		T7	9
valid_sources[0x3c]	2992	1			T3	4		T4	3		T7	12
valid_sources[0x3d]	3689	1			T3	1		T4	2		T7	6
valid_sources[0x3e]	3664	1			T3	5		T4	3		T7	18
valid_sources[0x3f]	4512	1			T1	2		T3	5		T4	2
valid_sources[0x40]	3388	1			T3	3		T7	10		T9	32
valid_sources[0x41]	4529	1			T3	4		T4	2		T7	17
valid_sources[0x42]	3834	1			T3	5		T7	10		T8	5
valid_sources[0x43]	3741	1			T1	1		T3	3		T4	2
valid_sources[0x44]	3240	1			T1	4		T3	5		T7	10
valid_sources[0x45]	3465	1			T3	2		T7	15		T10	2
valid_sources[0x46]	3785	1			T4	1		T7	22		T10	1
valid_sources[0x47]	3365	1			T1	1		T3	4		T4	3
valid_sources[0x48]	6447	1			T3	3		T4	1		T7	12
valid_sources[0x49]	3289	1			T1	1		T3	4		T7	11
valid_sources[0x4a]	4984	1			T1	1		T3	2		T4	1
valid_sources[0x4b]	3368	1			T1	1		T3	5		T7	10
valid_sources[0x4c]	3027	1			T1	3		T3	2		T7	12
valid_sources[0x4d]	3815	1			T3	2		T7	19		T8	2
valid_sources[0x4e]	6196	1			T3	3		T4	2		T7	14
valid_sources[0x4f]	3136	1			T3	3		T7	10		T9	17
valid_sources[0x50]	5341	1			T1	1		T3	4		T4	8
valid_sources[0x51]	3314	1			T3	1		T4	3		T7	13
valid_sources[0x52]	2838	1			T3	8		T7	11		T8	1
valid_sources[0x53]	3461	1			T3	2		T4	1		T7	9
valid_sources[0x54]	3651	1			T3	4		T7	13		T8	2
valid_sources[0x55]	3264	1			T3	10		T4	2		T7	18
valid_sources[0x56]	2919	1			T1	3		T3	3		T7	13
valid_sources[0x57]	3829	1			T3	4		T4	1		T7	8
valid_sources[0x58]	4670	1			T3	7		T7	17		T8	5
valid_sources[0x59]	4565	1			T1	3		T7	15		T8	5
valid_sources[0x5a]	6162	1			T1	1		T4	1		T7	12
valid_sources[0x5b]	4527	1			T3	1		T4	3		T7	14
valid_sources[0x5c]	3058	1			T1	1		T2	14		T3	1
valid_sources[0x5d]	3775	1			T1	1		T3	4		T4	2
valid_sources[0x5e]	3524	1			T3	2		T7	13		T8	1
valid_sources[0x5f]	2905	1			T1	1		T3	5		T4	1
valid_sources[0x60]	3573	1			T3	3		T4	3		T7	8
valid_sources[0x61]	5276	1			T3	8		T4	2		T7	13
valid_sources[0x62]	3646	1			T1	1		T3	2		T4	1
valid_sources[0x63]	5839	1			T1	1		T3	3		T7	19
valid_sources[0x64]	4591	1			T3	2		T7	11		T10	3
valid_sources[0x65]	3293	1			T1	1		T3	3		T4	5
valid_sources[0x66]	3660	1			T1	2		T3	5		T4	2
valid_sources[0x67]	5070	1			T3	4		T4	2		T7	14
valid_sources[0x68]	3071	1			T1	3		T3	1		T7	11
valid_sources[0x69]	3852	1			T1	1		T3	2		T4	2
valid_sources[0x6a]	4725	1			T3	2		T4	3		T7	12
valid_sources[0x6b]	4548	1			T3	10		T4	3		T7	6
valid_sources[0x6c]	2719	1			T3	3		T4	3		T7	18
valid_sources[0x6d]	3318	1			T1	3		T3	7		T4	3
valid_sources[0x6e]	3703	1			T3	2		T4	4		T7	14
valid_sources[0x6f]	3118	1			T3	2		T7	9		T10	4
valid_sources[0x70]	3746	1			T4	2		T7	13		T10	1
valid_sources[0x71]	3227	1			T3	1		T7	15		T8	2
valid_sources[0x72]	2763	1			T3	4		T4	3		T7	10
valid_sources[0x73]	3390	1			T3	3		T4	1		T7	11
valid_sources[0x74]	4172	1			T3	5		T7	19		T8	2
valid_sources[0x75]	3250	1			T1	1		T3	1		T4	1
valid_sources[0x76]	3728	1			T3	6		T7	15		T8	1
valid_sources[0x77]	2843	1			T1	1		T3	4		T4	2
valid_sources[0x78]	3741	1			T1	1		T3	2		T7	18
valid_sources[0x79]	3973	1			T3	4		T4	3		T7	12
valid_sources[0x7a]	4261	1			T3	4		T7	11		T10	4
valid_sources[0x7b]	3202	1			T1	1		T3	1		T4	1
valid_sources[0x7c]	3451	1			T1	3		T3	5		T4	2
valid_sources[0x7d]	3744	1			T3	1		T7	19		T8	1
valid_sources[0x7e]	3107	1			T3	5		T4	1		T7	7
valid_sources[0x7f]	4069	1			T3	5		T4	1		T7	17
valid_sources[0x80]	3273	1			T3	2		T4	2		T7	9

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

248214

1

T1

43

T3

269

T4

81

values[0x0]

all_enables

biggest_size

80013

1

T1

14

T2

2

T3

78

values[0x1]

all_enables

biggest_size

43214

1

T1

4

T3

31

T4

13