Unified Coverage Report :: Module :: rstmgr_cascading_sva_if

Module : rstmgr_cascading_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_cascading_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_cascading_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_cascading_sva_if

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	100	1	1	100.00
ALWAYS	103	1	1	100.00
ALWAYS	107	1	1	100.00
ALWAYS	127	1	1	100.00
ALWAYS	138	1	1	100.00
ALWAYS	141	1	1	100.00
ALWAYS	144	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
100	1	1
103	1	1
107	1	1
127	1	1
138	1	1
141	1	1
144	1	1

---

Cond Coverage for Module : rstmgr_cascading_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       103
 EXPRESSION (((!scanmode)) || scan_rst_ni)
             ------1------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T8,T11
0	1	Covered	T11,T12,T13
1	0	Covered	T4,T11,T12

 LINE       107
 EXPRESSION (por_n_i[rstmgr_pkg::DomainAonSel] && ((!scanmode)))
             ----------------1----------------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T4,T8,T11
1	1	Covered	T1,T2,T3

---

Assert Coverage for Module : rstmgr_cascading_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	31	31	100.00	31	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	31	31	100.00	31	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CascadeEffAonToRstPorAboveFall_A	55155979	9246	0	0
CascadeEffAonToRstPorAboveRise_A	55155979	9246	0	0
CascadeEffAonToRstPorIoAboveFall_A	52948016	9246	0	0
CascadeEffAonToRstPorIoAboveRise_A	52948016	9246	0	0
CascadeEffAonToRstPorIoDiv2AboveFall_A	26474912	9246	0	0
CascadeEffAonToRstPorIoDiv2AboveRise_A	26474912	9246	0	0
CascadeEffAonToRstPorIoDiv4AboveFall_A	13237315	9246	0	0
CascadeEffAonToRstPorIoDiv4AboveRise_A	13237315	9246	0	0
CascadeEffAonToRstPorUcbAboveFall_A	26474792	9246	0	0
CascadeEffAonToRstPorUcbAboveRise_A	26474792	9246	0	0
CascadeLcToLcAboveFall_A	55155979	22411	0	0
CascadeLcToLcAboveRise_A	55155979	22411	0	0
CascadeLcToLcAonAboveFall_A	1671168	22411	0	0
CascadeLcToLcAonAboveRise_A	1671168	22411	0	0
CascadeLcToLcShadowedAboveFall_A	55155979	22411	0	0
CascadeLcToLcShadowedAboveRise_A	55155979	22411	0	0
CascadePorToAonAboveFall_A	1671168	7430	0	0
CascadeSysToSysAboveFall_A	55155979	22411	0	0
CascadeSysToSysAboveRise_A	55155979	22411	0	0
ScanRstToAonRise_A	1671168	246	0	0
StablePorToAonRise_A	1671168	9246	0	0
g_power_domains[0].CascadeLcToSysAboveFall_A	11774898	22411	0	0
g_power_domains[0].CascadeLcToSysAboveRise_A	11774898	22411	0	0
g_power_domains[0].CascadeLocalRstToLcAboveFall_A	11774898	22411	0	0
g_power_domains[0].CascadeLocalRstToLcAboveRise_A	11774898	22411	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A	13237315	22411	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A	13237315	22411	0	0
g_power_domains[1].CascadeLcToSysAboveFall_A	11774898	22411	0	0
g_power_domains[1].CascadeLcToSysAboveRise_A	11774898	22411	0	0
g_power_domains[1].CascadeLocalRstToLcAboveFall_A	11774898	22411	0	0
g_power_domains[1].CascadeLocalRstToLcAboveRise_A	11774898	22411	0	0

CascadeEffAonToRstPorAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55155979	9246	0	0
T1	10772	1	0	0
T2	8385	1	0	0
T3	13364	1	0	0
T4	20614	2	0	0
T5	19842	2	0	0
T6	24337	8	0	0
T7	121488	27	0	0
T8	11592	2	0	0
T9	17134	1	0	0
T10	43164	1	0	0

CascadeEffAonToRstPorAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55155979	9246	0	0
T1	10772	1	0	0
T2	8385	1	0	0
T3	13364	1	0	0
T4	20614	2	0	0
T5	19842	2	0	0
T6	24337	8	0	0
T7	121488	27	0	0
T8	11592	2	0	0
T9	17134	1	0	0
T10	43164	1	0	0

CascadeEffAonToRstPorIoAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52948016	9246	0	0
T1	10340	1	0	0
T2	8048	1	0	0
T3	12830	1	0	0
T4	19788	2	0	0
T5	19046	2	0	0
T6	23351	8	0	0
T7	116630	27	0	0
T8	11128	2	0	0
T9	16448	1	0	0
T10	41436	1	0	0

CascadeEffAonToRstPorIoAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52948016	9246	0	0
T1	10340	1	0	0
T2	8048	1	0	0
T3	12830	1	0	0
T4	19788	2	0	0
T5	19046	2	0	0
T6	23351	8	0	0
T7	116630	27	0	0
T8	11128	2	0	0
T9	16448	1	0	0
T10	41436	1	0	0

CascadeEffAonToRstPorIoDiv2AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26474912	9246	0	0
T1	5171	1	0	0
T2	4024	1	0	0
T3	6415	1	0	0
T4	9893	2	0	0
T5	9523	2	0	0
T6	11683	8	0	0
T7	58314	27	0	0
T8	5562	2	0	0
T9	8222	1	0	0
T10	20718	1	0	0

CascadeEffAonToRstPorIoDiv2AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26474912	9246	0	0
T1	5171	1	0	0
T2	4024	1	0	0
T3	6415	1	0	0
T4	9893	2	0	0
T5	9523	2	0	0
T6	11683	8	0	0
T7	58314	27	0	0
T8	5562	2	0	0
T9	8222	1	0	0
T10	20718	1	0	0

CascadeEffAonToRstPorIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13237315	9246	0	0
T1	2585	1	0	0
T2	2011	1	0	0
T3	3207	1	0	0
T4	4947	2	0	0
T5	4761	2	0	0
T6	5840	8	0	0
T7	29158	27	0	0
T8	2781	2	0	0
T9	4110	1	0	0
T10	10358	1	0	0

CascadeEffAonToRstPorIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13237315	9246	0	0
T1	2585	1	0	0
T2	2011	1	0	0
T3	3207	1	0	0
T4	4947	2	0	0
T5	4761	2	0	0
T6	5840	8	0	0
T7	29158	27	0	0
T8	2781	2	0	0
T9	4110	1	0	0
T10	10358	1	0	0

CascadeEffAonToRstPorUcbAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26474792	9246	0	0
T1	5170	1	0	0
T2	4025	1	0	0
T3	6415	1	0	0
T4	9891	2	0	0
T5	9523	2	0	0
T6	11677	8	0	0
T7	58332	27	0	0
T8	5564	2	0	0
T9	8223	1	0	0
T10	20718	1	0	0

CascadeEffAonToRstPorUcbAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26474792	9246	0	0
T1	5170	1	0	0
T2	4025	1	0	0
T3	6415	1	0	0
T4	9891	2	0	0
T5	9523	2	0	0
T6	11677	8	0	0
T7	58332	27	0	0
T8	5564	2	0	0
T9	8223	1	0	0
T10	20718	1	0	0

CascadeLcToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55155979	22411	0	0
T1	10772	11	0	0
T2	8385	1	0	0
T3	13364	1	0	0
T4	20614	6	0	0
T5	19842	2	0	0
T6	24337	8	0	0
T7	121488	102	0	0
T8	11592	6	0	0
T9	17134	21	0	0
T10	43164	1	0	0

CascadeLcToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55155979	22411	0	0
T1	10772	11	0	0
T2	8385	1	0	0
T3	13364	1	0	0
T4	20614	6	0	0
T5	19842	2	0	0
T6	24337	8	0	0
T7	121488	102	0	0
T8	11592	6	0	0
T9	17134	21	0	0
T10	43164	1	0	0

CascadeLcToLcAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1671168	22411	0	0
T1	321	11	0	0
T2	250	1	0	0
T3	400	1	0	0
T4	617	6	0	0
T5	593	2	0	0
T6	731	8	0	0
T7	3659	102	0	0
T8	346	6	0	0
T9	512	21	0	0
T10	1294	1	0	0

CascadeLcToLcAonAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1671168	22411	0	0
T1	321	11	0	0
T2	250	1	0	0
T3	400	1	0	0
T4	617	6	0	0
T5	593	2	0	0
T6	731	8	0	0
T7	3659	102	0	0
T8	346	6	0	0
T9	512	21	0	0
T10	1294	1	0	0

CascadeLcToLcShadowedAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55155979	22411	0	0
T1	10772	11	0	0
T2	8385	1	0	0
T3	13364	1	0	0
T4	20614	6	0	0
T5	19842	2	0	0
T6	24337	8	0	0
T7	121488	102	0	0
T8	11592	6	0	0
T9	17134	21	0	0
T10	43164	1	0	0

CascadeLcToLcShadowedAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55155979	22411	0	0
T1	10772	11	0	0
T2	8385	1	0	0
T3	13364	1	0	0
T4	20614	6	0	0
T5	19842	2	0	0
T6	24337	8	0	0
T7	121488	102	0	0
T8	11592	6	0	0
T9	17134	21	0	0
T10	43164	1	0	0

CascadePorToAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1671168	7430	0	0
T1	321	1	0	0
T2	250	1	0	0
T3	400	1	0	0
T4	617	1	0	0
T5	593	19	0	0
T6	731	8	0	0
T7	3659	27	0	0
T8	346	1	0	0
T9	512	1	0	0
T10	1294	1	0	0

CascadeSysToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55155979	22411	0	0
T1	10772	11	0	0
T2	8385	1	0	0
T3	13364	1	0	0
T4	20614	6	0	0
T5	19842	2	0	0
T6	24337	8	0	0
T7	121488	102	0	0
T8	11592	6	0	0
T9	17134	21	0	0
T10	43164	1	0	0

CascadeSysToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55155979	22411	0	0
T1	10772	11	0	0
T2	8385	1	0	0
T3	13364	1	0	0
T4	20614	6	0	0
T5	19842	2	0	0
T6	24337	8	0	0
T7	121488	102	0	0
T8	11592	6	0	0
T9	17134	21	0	0
T10	43164	1	0	0

ScanRstToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1671168	246	0	0
T11	16323	1	0	0
T12	32923	3	0	0
T13	3537	1	0	0
T14	513	0	0	0
T16	730	0	0	0
T26	206	0	0	0
T36	167	0	0	0
T51	28128	2	0	0
T52	527	0	0	0
T68	735	0	0	0
T80	0	2	0	0
T92	0	1	0	0
T94	0	2	0	0
T95	0	3	0	0
T96	0	1	0	0
T102	0	2	0	0

StablePorToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1671168	9246	0	0
T1	321	1	0	0
T2	250	1	0	0
T3	400	1	0	0
T4	617	2	0	0
T5	593	2	0	0
T6	731	8	0	0
T7	3659	27	0	0
T8	346	2	0	0
T9	512	1	0	0
T10	1294	1	0	0

g_power_domains[0].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11774898	22411	0	0
T1	1988	11	0	0
T2	1945	1	0	0
T3	3188	1	0	0
T4	4704	6	0	0
T5	4695	2	0	0
T6	5486	8	0	0
T7	25897	102	0	0
T8	2447	6	0	0
T9	2644	21	0	0
T10	10268	1	0	0

g_power_domains[0].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11774898	22411	0	0
T1	1988	11	0	0
T2	1945	1	0	0
T3	3188	1	0	0
T4	4704	6	0	0
T5	4695	2	0	0
T6	5486	8	0	0
T7	25897	102	0	0
T8	2447	6	0	0
T9	2644	21	0	0
T10	10268	1	0	0

g_power_domains[0].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11774898	22411	0	0
T1	1988	11	0	0
T2	1945	1	0	0
T3	3188	1	0	0
T4	4704	6	0	0
T5	4695	2	0	0
T6	5486	8	0	0
T7	25897	102	0	0
T8	2447	6	0	0
T9	2644	21	0	0
T10	10268	1	0	0

g_power_domains[0].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11774898	22411	0	0
T1	1988	11	0	0
T2	1945	1	0	0
T3	3188	1	0	0
T4	4704	6	0	0
T5	4695	2	0	0
T6	5486	8	0	0
T7	25897	102	0	0
T8	2447	6	0	0
T9	2644	21	0	0
T10	10268	1	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13237315	22411	0	0
T1	2585	11	0	0
T2	2011	1	0	0
T3	3207	1	0	0
T4	4947	6	0	0
T5	4761	2	0	0
T6	5840	8	0	0
T7	29158	102	0	0
T8	2781	6	0	0
T9	4110	21	0	0
T10	10358	1	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13237315	22411	0	0
T1	2585	11	0	0
T2	2011	1	0	0
T3	3207	1	0	0
T4	4947	6	0	0
T5	4761	2	0	0
T6	5840	8	0	0
T7	29158	102	0	0
T8	2781	6	0	0
T9	4110	21	0	0
T10	10358	1	0	0

g_power_domains[1].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11774898	22411	0	0
T1	1988	11	0	0
T2	1945	1	0	0
T3	3188	1	0	0
T4	4704	6	0	0
T5	4695	2	0	0
T6	5486	8	0	0
T7	25897	102	0	0
T8	2447	6	0	0
T9	2644	21	0	0
T10	10268	1	0	0

g_power_domains[1].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11774898	22411	0	0
T1	1988	11	0	0
T2	1945	1	0	0
T3	3188	1	0	0
T4	4704	6	0	0
T5	4695	2	0	0
T6	5486	8	0	0
T7	25897	102	0	0
T8	2447	6	0	0
T9	2644	21	0	0
T10	10268	1	0	0

g_power_domains[1].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11774898	22411	0	0
T1	1988	11	0	0
T2	1945	1	0	0
T3	3188	1	0	0
T4	4704	6	0	0
T5	4695	2	0	0
T6	5486	8	0	0
T7	25897	102	0	0
T8	2447	6	0	0
T9	2644	21	0	0
T10	10268	1	0	0

g_power_domains[1].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11774898	22411	0	0
T1	1988	11	0	0
T2	1945	1	0	0
T3	3188	1	0	0
T4	4704	6	0	0
T5	4695	2	0	0
T6	5486	8	0	0
T7	25897	102	0	0
T8	2447	6	0	0
T9	2644	21	0	0
T10	10268	1	0	0