Unified Coverage Report :: Module :: rstmgr_sw_rst_sva_if

Module : rstmgr_sw_rst_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_sw_rst_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_sw_rst_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_sw_rst_sva_if

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
21	8	8

---

Cond Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Covered	Percent
Conditions	24	24	100.00
Logical	24	24	100.00
Non-Logical	0	0
Event	0	0

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[0])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T4,T5

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[1])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T9
1	0	Covered	T1,T4,T5

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[2])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T8,T10
1	0	Covered	T1,T4,T5

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[3])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T8,T10
1	0	Covered	T1,T4,T5

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[4])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T4,T8
1	0	Covered	T1,T4,T5

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[5])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T10,T11
1	0	Covered	T1,T4,T5

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[6])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T10,T11
1	0	Covered	T1,T4,T5

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[7])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T8,T10
1	0	Covered	T1,T4,T5

---

Assert Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions[0].RstEnOff_A	13237315	14033	0	0
gen_assertions[0].RstEnOn_A	13237315	1049	0	0
gen_assertions[0].RstNOff_A	13237315	14033	0	0
gen_assertions[0].RstNOn_A	13237315	1049	0	0
gen_assertions[1].RstEnOff_A	52948016	12778	0	0
gen_assertions[1].RstEnOn_A	52948016	1005	0	0
gen_assertions[1].RstNOff_A	52948016	12778	0	0
gen_assertions[1].RstNOn_A	52948016	1005	0	0
gen_assertions[2].RstEnOff_A	26474912	12849	0	0
gen_assertions[2].RstEnOn_A	26474912	1001	0	0
gen_assertions[2].RstNOff_A	26474912	12849	0	0
gen_assertions[2].RstNOn_A	26474912	1001	0	0
gen_assertions[3].RstEnOff_A	26474792	12887	0	0
gen_assertions[3].RstEnOn_A	26474792	1037	0	0
gen_assertions[3].RstNOff_A	26474792	12887	0	0
gen_assertions[3].RstNOn_A	26474792	1037	0	0
gen_assertions[4].RstEnOff_A	1671168	22221	0	0
gen_assertions[4].RstEnOn_A	1671168	1121	0	0
gen_assertions[4].RstNOff_A	1671168	22221	0	0
gen_assertions[4].RstNOn_A	1671168	1121	0	0
gen_assertions[5].RstEnOff_A	13237315	14286	0	0
gen_assertions[5].RstEnOn_A	13237315	1152	0	0
gen_assertions[5].RstNOff_A	13237315	14286	0	0
gen_assertions[5].RstNOn_A	13237315	1152	0	0
gen_assertions[6].RstEnOff_A	13237315	14300	0	0
gen_assertions[6].RstEnOn_A	13237315	1170	0	0
gen_assertions[6].RstNOff_A	13237315	14300	0	0
gen_assertions[6].RstNOn_A	13237315	1170	0	0
gen_assertions[7].RstEnOff_A	13237315	14359	0	0
gen_assertions[7].RstEnOn_A	13237315	1228	0	0
gen_assertions[7].RstNOff_A	13237315	14359	0	0
gen_assertions[7].RstNOn_A	13237315	1228	0	0

gen_assertions[0].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13237315	14033	0	0
T1	2585	10	0	0
T2	2011	0	0	0
T3	3207	6	0	0
T4	4947	5	0	0
T5	4761	0	0	0
T6	5840	0	0	0
T7	29158	75	0	0
T8	2781	4	0	0
T9	4110	20	0	0
T10	10358	4	0	0
T11	0	106	0	0
T12	0	271	0	0
T13	0	60	0	0

gen_assertions[0].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13237315	1049	0	0
T1	2585	2	0	0
T2	2011	0	0	0
T3	3207	6	0	0
T4	4947	1	0	0
T5	4761	0	0	0
T6	5840	0	0	0
T7	29158	0	0	0
T8	2781	0	0	0
T9	4110	8	0	0
T10	10358	4	0	0
T11	0	16	0	0
T12	0	24	0	0
T13	0	7	0	0
T26	0	1	0	0
T51	0	33	0	0

gen_assertions[0].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13237315	14033	0	0
T1	2585	10	0	0
T2	2011	0	0	0
T3	3207	6	0	0
T4	4947	5	0	0
T5	4761	0	0	0
T6	5840	0	0	0
T7	29158	75	0	0
T8	2781	4	0	0
T9	4110	20	0	0
T10	10358	4	0	0
T11	0	106	0	0
T12	0	271	0	0
T13	0	60	0	0

gen_assertions[0].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13237315	1049	0	0
T1	2585	2	0	0
T2	2011	0	0	0
T3	3207	6	0	0
T4	4947	1	0	0
T5	4761	0	0	0
T6	5840	0	0	0
T7	29158	0	0	0
T8	2781	0	0	0
T9	4110	8	0	0
T10	10358	4	0	0
T11	0	16	0	0
T12	0	24	0	0
T13	0	7	0	0
T26	0	1	0	0
T51	0	33	0	0

gen_assertions[1].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52948016	12778	0	0
T1	10340	9	0	0
T2	8048	0	0	0
T3	12830	6	0	0
T4	19788	4	0	0
T5	19046	0	0	0
T6	23351	0	0	0
T7	116630	69	0	0
T8	11128	4	0	0
T9	16448	17	0	0
T10	41436	4	0	0
T11	0	103	0	0
T12	0	244	0	0
T13	0	54	0	0

gen_assertions[1].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52948016	1005	0	0
T1	10340	6	0	0
T2	8048	0	0	0
T3	12830	6	0	0
T4	19788	0	0	0
T5	19046	0	0	0
T6	23351	0	0	0
T7	116630	0	0	0
T8	11128	0	0	0
T9	16448	7	0	0
T10	41436	4	0	0
T11	0	19	0	0
T12	0	26	0	0
T13	0	7	0	0
T47	0	1	0	0
T51	0	37	0	0
T56	0	1	0	0

gen_assertions[1].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52948016	12778	0	0
T1	10340	9	0	0
T2	8048	0	0	0
T3	12830	6	0	0
T4	19788	4	0	0
T5	19046	0	0	0
T6	23351	0	0	0
T7	116630	69	0	0
T8	11128	4	0	0
T9	16448	17	0	0
T10	41436	4	0	0
T11	0	103	0	0
T12	0	244	0	0
T13	0	54	0	0

gen_assertions[1].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52948016	1005	0	0
T1	10340	6	0	0
T2	8048	0	0	0
T3	12830	6	0	0
T4	19788	0	0	0
T5	19046	0	0	0
T6	23351	0	0	0
T7	116630	0	0	0
T8	11128	0	0	0
T9	16448	7	0	0
T10	41436	4	0	0
T11	0	19	0	0
T12	0	26	0	0
T13	0	7	0	0
T47	0	1	0	0
T51	0	37	0	0
T56	0	1	0	0

gen_assertions[2].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26474912	12849	0	0
T1	5171	9	0	0
T2	4024	0	0	0
T3	6415	7	0	0
T4	9893	4	0	0
T5	9523	0	0	0
T6	11683	0	0	0
T7	58314	69	0	0
T8	5562	5	0	0
T9	8222	17	0	0
T10	20718	3	0	0
T11	0	99	0	0
T12	0	244	0	0
T13	0	52	0	0

gen_assertions[2].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26474912	1001	0	0
T3	6415	7	0	0
T4	9893	0	0	0
T5	9523	0	0	0
T6	11683	0	0	0
T7	58314	0	0	0
T8	5562	1	0	0
T9	8222	0	0	0
T10	20718	3	0	0
T11	259318	16	0	0
T12	0	25	0	0
T13	0	4	0	0
T15	11671	0	0	0
T47	0	3	0	0
T50	0	4	0	0
T51	0	37	0	0
T79	0	3	0	0

gen_assertions[2].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26474912	12849	0	0
T1	5171	9	0	0
T2	4024	0	0	0
T3	6415	7	0	0
T4	9893	4	0	0
T5	9523	0	0	0
T6	11683	0	0	0
T7	58314	69	0	0
T8	5562	5	0	0
T9	8222	17	0	0
T10	20718	3	0	0
T11	0	99	0	0
T12	0	244	0	0
T13	0	52	0	0

gen_assertions[2].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26474912	1001	0	0
T3	6415	7	0	0
T4	9893	0	0	0
T5	9523	0	0	0
T6	11683	0	0	0
T7	58314	0	0	0
T8	5562	1	0	0
T9	8222	0	0	0
T10	20718	3	0	0
T11	259318	16	0	0
T12	0	25	0	0
T13	0	4	0	0
T15	11671	0	0	0
T47	0	3	0	0
T50	0	4	0	0
T51	0	37	0	0
T79	0	3	0	0

gen_assertions[3].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26474792	12887	0	0
T1	5170	9	0	0
T2	4025	0	0	0
T3	6415	7	0	0
T4	9891	4	0	0
T5	9523	0	0	0
T6	11677	0	0	0
T7	58332	69	0	0
T8	5564	5	0	0
T9	8223	17	0	0
T10	20718	6	0	0
T11	0	102	0	0
T12	0	245	0	0
T13	0	55	0	0

gen_assertions[3].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26474792	1037	0	0
T3	6415	7	0	0
T4	9891	0	0	0
T5	9523	0	0	0
T6	11677	0	0	0
T7	58332	0	0	0
T8	5564	1	0	0
T9	8223	0	0	0
T10	20718	6	0	0
T11	259307	19	0	0
T12	0	28	0	0
T13	0	7	0	0
T15	11664	0	0	0
T47	0	4	0	0
T50	0	4	0	0
T51	0	41	0	0
T79	0	4	0	0

gen_assertions[3].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26474792	12887	0	0
T1	5170	9	0	0
T2	4025	0	0	0
T3	6415	7	0	0
T4	9891	4	0	0
T5	9523	0	0	0
T6	11677	0	0	0
T7	58332	69	0	0
T8	5564	5	0	0
T9	8223	17	0	0
T10	20718	6	0	0
T11	0	102	0	0
T12	0	245	0	0
T13	0	55	0	0

gen_assertions[3].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26474792	1037	0	0
T3	6415	7	0	0
T4	9891	0	0	0
T5	9523	0	0	0
T6	11677	0	0	0
T7	58332	0	0	0
T8	5564	1	0	0
T9	8223	0	0	0
T10	20718	6	0	0
T11	259307	19	0	0
T12	0	28	0	0
T13	0	7	0	0
T15	11664	0	0	0
T47	0	4	0	0
T50	0	4	0	0
T51	0	41	0	0
T79	0	4	0	0

gen_assertions[4].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1671168	22221	0	0
T1	321	11	0	0
T2	250	1	0	0
T3	400	11	0	0
T4	617	7	0	0
T5	593	2	0	0
T6	731	3	0	0
T7	3659	74	0	0
T8	346	7	0	0
T9	512	20	0	0
T10	1294	9	0	0

gen_assertions[4].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1671168	1121	0	0
T3	400	10	0	0
T4	617	1	0	0
T5	593	0	0	0
T6	731	0	0	0
T7	3659	0	0	0
T8	346	1	0	0
T9	512	0	0	0
T10	1294	8	0	0
T11	16323	21	0	0
T12	0	22	0	0
T13	0	6	0	0
T15	732	0	0	0
T47	0	5	0	0
T50	0	6	0	0
T51	0	38	0	0

gen_assertions[4].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1671168	22221	0	0
T1	321	11	0	0
T2	250	1	0	0
T3	400	11	0	0
T4	617	7	0	0
T5	593	2	0	0
T6	731	3	0	0
T7	3659	74	0	0
T8	346	7	0	0
T9	512	20	0	0
T10	1294	9	0	0

gen_assertions[4].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1671168	1121	0	0
T3	400	10	0	0
T4	617	1	0	0
T5	593	0	0	0
T6	731	0	0	0
T7	3659	0	0	0
T8	346	1	0	0
T9	512	0	0	0
T10	1294	8	0	0
T11	16323	21	0	0
T12	0	22	0	0
T13	0	6	0	0
T15	732	0	0	0
T47	0	5	0	0
T50	0	6	0	0
T51	0	38	0	0

gen_assertions[5].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13237315	14286	0	0
T1	2585	10	0	0
T2	2011	0	0	0
T3	3207	9	0	0
T4	4947	4	0	0
T5	4761	0	0	0
T6	5840	0	0	0
T7	29158	75	0	0
T8	2781	4	0	0
T9	4110	20	0	0
T10	10358	8	0	0
T11	0	113	0	0
T12	0	270	0	0
T13	0	60	0	0

gen_assertions[5].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13237315	1152	0	0
T3	3207	9	0	0
T4	4947	0	0	0
T5	4761	0	0	0
T6	5840	0	0	0
T7	29158	0	0	0
T8	2781	0	0	0
T9	4110	0	0	0
T10	10358	8	0	0
T11	129664	23	0	0
T12	0	23	0	0
T13	0	7	0	0
T15	5831	0	0	0
T47	0	5	0	0
T50	0	6	0	0
T51	0	43	0	0
T79	0	6	0	0
T80	0	22	0	0

gen_assertions[5].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13237315	14286	0	0
T1	2585	10	0	0
T2	2011	0	0	0
T3	3207	9	0	0
T4	4947	4	0	0
T5	4761	0	0	0
T6	5840	0	0	0
T7	29158	75	0	0
T8	2781	4	0	0
T9	4110	20	0	0
T10	10358	8	0	0
T11	0	113	0	0
T12	0	270	0	0
T13	0	60	0	0

gen_assertions[5].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13237315	1152	0	0
T3	3207	9	0	0
T4	4947	0	0	0
T5	4761	0	0	0
T6	5840	0	0	0
T7	29158	0	0	0
T8	2781	0	0	0
T9	4110	0	0	0
T10	10358	8	0	0
T11	129664	23	0	0
T12	0	23	0	0
T13	0	7	0	0
T15	5831	0	0	0
T47	0	5	0	0
T50	0	6	0	0
T51	0	43	0	0
T79	0	6	0	0
T80	0	22	0	0

gen_assertions[6].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13237315	14300	0	0
T1	2585	10	0	0
T2	2011	0	0	0
T3	3207	11	0	0
T4	4947	4	0	0
T5	4761	0	0	0
T6	5840	0	0	0
T7	29158	75	0	0
T8	2781	4	0	0
T9	4110	20	0	0
T10	10358	11	0	0
T11	0	106	0	0
T12	0	275	0	0
T13	0	61	0	0

gen_assertions[6].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13237315	1170	0	0
T3	3207	11	0	0
T4	4947	0	0	0
T5	4761	0	0	0
T6	5840	0	0	0
T7	29158	0	0	0
T8	2781	0	0	0
T9	4110	0	0	0
T10	10358	11	0	0
T11	129664	17	0	0
T12	0	26	0	0
T13	0	9	0	0
T15	5831	0	0	0
T47	0	6	0	0
T50	0	8	0	0
T51	0	33	0	0
T79	0	7	0	0
T80	0	18	0	0

gen_assertions[6].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13237315	14300	0	0
T1	2585	10	0	0
T2	2011	0	0	0
T3	3207	11	0	0
T4	4947	4	0	0
T5	4761	0	0	0
T6	5840	0	0	0
T7	29158	75	0	0
T8	2781	4	0	0
T9	4110	20	0	0
T10	10358	11	0	0
T11	0	106	0	0
T12	0	275	0	0
T13	0	61	0	0

gen_assertions[6].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13237315	1170	0	0
T3	3207	11	0	0
T4	4947	0	0	0
T5	4761	0	0	0
T6	5840	0	0	0
T7	29158	0	0	0
T8	2781	0	0	0
T9	4110	0	0	0
T10	10358	11	0	0
T11	129664	17	0	0
T12	0	26	0	0
T13	0	9	0	0
T15	5831	0	0	0
T47	0	6	0	0
T50	0	8	0	0
T51	0	33	0	0
T79	0	7	0	0
T80	0	18	0	0

gen_assertions[7].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13237315	14359	0	0
T1	2585	10	0	0
T2	2011	0	0	0
T3	3207	11	0	0
T4	4947	4	0	0
T5	4761	0	0	0
T6	5840	0	0	0
T7	29158	75	0	0
T8	2781	5	0	0
T9	4110	20	0	0
T10	10358	10	0	0
T11	0	109	0	0
T12	0	272	0	0
T13	0	57	0	0

gen_assertions[7].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13237315	1228	0	0
T3	3207	11	0	0
T4	4947	0	0	0
T5	4761	0	0	0
T6	5840	0	0	0
T7	29158	0	0	0
T8	2781	1	0	0
T9	4110	0	0	0
T10	10358	10	0	0
T11	129664	18	0	0
T12	0	24	0	0
T13	0	5	0	0
T15	5831	0	0	0
T47	0	8	0	0
T50	0	10	0	0
T51	0	39	0	0
T79	0	8	0	0

gen_assertions[7].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13237315	14359	0	0
T1	2585	10	0	0
T2	2011	0	0	0
T3	3207	11	0	0
T4	4947	4	0	0
T5	4761	0	0	0
T6	5840	0	0	0
T7	29158	75	0	0
T8	2781	5	0	0
T9	4110	20	0	0
T10	10358	10	0	0
T11	0	109	0	0
T12	0	272	0	0
T13	0	57	0	0

gen_assertions[7].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13237315	1228	0	0
T3	3207	11	0	0
T4	4947	0	0	0
T5	4761	0	0	0
T6	5840	0	0	0
T7	29158	0	0	0
T8	2781	1	0	0
T9	4110	0	0	0
T10	10358	10	0	0
T11	129664	18	0	0
T12	0	24	0	0
T13	0	5	0	0
T15	5831	0	0	0
T47	0	8	0	0
T50	0	10	0	0
T51	0	39	0	0
T79	0	8	0	0