Unified Coverage Report :: Module :: rstmgr_csr_assert_fpv

Module : rstmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rstmgr_csr_assert_0/rstmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rstmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rstmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	19	19	100.00	19	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	19	19	100.00	19	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	12566271	7149	0	0
alert_regwen_rd_A	12566271	5652	0	0
cpu_regwen_rd_A	12566271	5637	0	0
sw_rst_ctrl_n_0_rd_A	12566271	12073	0	0
sw_rst_ctrl_n_1_rd_A	12566271	12189	0	0
sw_rst_ctrl_n_2_rd_A	12566271	11931	0	0
sw_rst_ctrl_n_3_rd_A	12566271	12009	0	0
sw_rst_ctrl_n_4_rd_A	12566271	12128	0	0
sw_rst_ctrl_n_5_rd_A	12566271	12025	0	0
sw_rst_ctrl_n_6_rd_A	12566271	12058	0	0
sw_rst_ctrl_n_7_rd_A	12566271	12314	0	0
sw_rst_regwen_0_rd_A	12566271	6135	0	0
sw_rst_regwen_1_rd_A	12566271	6306	0	0
sw_rst_regwen_2_rd_A	12566271	6400	0	0
sw_rst_regwen_3_rd_A	12566271	6225	0	0
sw_rst_regwen_4_rd_A	12566271	6382	0	0
sw_rst_regwen_5_rd_A	12566271	6427	0	0
sw_rst_regwen_6_rd_A	12566271	6402	0	0
sw_rst_regwen_7_rd_A	12566271	6367	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12566271	7149	0	0
T58	11072	2	0	0
T60	2770	116	0	0
T63	6822	321	0	0
T64	6286	280	0	0
T70	4381	28	0	0
T82	4047	529	0	0
T83	16486	3	0	0
T84	3538	37	0	0
T85	5761	94	0	0
T88	16884	2	0	0

alert_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12566271	5652	0	0
T11	117542	125	0	0
T12	226719	0	0	0
T13	21771	0	0	0
T14	3878	0	0	0
T16	5098	0	0	0
T26	1429	0	0	0
T36	1269	0	0	0
T51	200885	238	0	0
T52	4082	0	0	0
T68	4527	0	0	0
T92	0	24	0	0
T95	0	182	0	0
T97	0	140	0	0
T100	0	479	0	0
T119	0	105	0	0
T120	0	30	0	0
T121	0	195	0	0
T122	0	74	0	0

cpu_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12566271	5637	0	0
T11	117542	141	0	0
T12	226719	0	0	0
T13	21771	0	0	0
T14	3878	0	0	0
T16	5098	0	0	0
T26	1429	0	0	0
T36	1269	0	0	0
T51	200885	234	0	0
T52	4082	0	0	0
T68	4527	0	0	0
T92	0	30	0	0
T95	0	166	0	0
T97	0	144	0	0
T100	0	506	0	0
T119	0	128	0	0
T120	0	72	0	0
T121	0	167	0	0
T122	0	67	0	0

sw_rst_ctrl_n_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12566271	12073	0	0
T10	10268	127	0	0
T11	117542	405	0	0
T12	226719	0	0	0
T13	21771	0	0	0
T14	3878	0	0	0
T15	5479	0	0	0
T16	5098	0	0	0
T26	1429	0	0	0
T36	1269	0	0	0
T47	0	113	0	0
T51	200885	760	0	0
T56	0	12	0	0
T68	0	35	0	0
T79	0	123	0	0
T92	0	42	0	0
T95	0	205	0	0
T123	0	10	0	0

sw_rst_ctrl_n_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12566271	12189	0	0
T10	10268	163	0	0
T11	117542	375	0	0
T12	226719	0	0	0
T13	21771	0	0	0
T14	3878	0	0	0
T15	5479	0	0	0
T16	5098	0	0	0
T26	1429	0	0	0
T36	1269	0	0	0
T47	0	114	0	0
T51	200885	791	0	0
T56	0	18	0	0
T68	0	39	0	0
T79	0	112	0	0
T92	0	51	0	0
T95	0	291	0	0
T123	0	7	0	0

sw_rst_ctrl_n_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12566271	11931	0	0
T10	10268	144	0	0
T11	117542	362	0	0
T12	226719	0	0	0
T13	21771	0	0	0
T14	3878	0	0	0
T15	5479	0	0	0
T16	5098	0	0	0
T26	1429	0	0	0
T36	1269	0	0	0
T47	0	95	0	0
T51	200885	761	0	0
T56	0	16	0	0
T68	0	43	0	0
T79	0	133	0	0
T92	0	51	0	0
T95	0	241	0	0
T123	0	9	0	0

sw_rst_ctrl_n_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12566271	12009	0	0
T10	10268	160	0	0
T11	117542	421	0	0
T12	226719	0	0	0
T13	21771	0	0	0
T14	3878	0	0	0
T15	5479	0	0	0
T16	5098	0	0	0
T26	1429	0	0	0
T36	1269	0	0	0
T47	0	132	0	0
T51	200885	796	0	0
T56	0	7	0	0
T68	0	33	0	0
T79	0	142	0	0
T92	0	42	0	0
T95	0	261	0	0
T123	0	7	0	0

sw_rst_ctrl_n_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12566271	12128	0	0
T10	10268	176	0	0
T11	117542	360	0	0
T12	226719	0	0	0
T13	21771	0	0	0
T14	3878	0	0	0
T15	5479	0	0	0
T16	5098	0	0	0
T26	1429	0	0	0
T36	1269	0	0	0
T47	0	121	0	0
T51	200885	821	0	0
T56	0	16	0	0
T68	0	34	0	0
T79	0	119	0	0
T92	0	41	0	0
T95	0	223	0	0
T123	0	18	0	0

sw_rst_ctrl_n_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12566271	12025	0	0
T10	10268	138	0	0
T11	117542	414	0	0
T12	226719	0	0	0
T13	21771	0	0	0
T14	3878	0	0	0
T15	5479	0	0	0
T16	5098	0	0	0
T26	1429	0	0	0
T36	1269	0	0	0
T47	0	121	0	0
T51	200885	784	0	0
T56	0	10	0	0
T68	0	31	0	0
T79	0	110	0	0
T92	0	59	0	0
T95	0	213	0	0
T123	0	18	0	0

sw_rst_ctrl_n_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12566271	12058	0	0
T10	10268	155	0	0
T11	117542	444	0	0
T12	226719	0	0	0
T13	21771	0	0	0
T14	3878	0	0	0
T15	5479	0	0	0
T16	5098	0	0	0
T26	1429	0	0	0
T36	1269	0	0	0
T47	0	91	0	0
T51	200885	767	0	0
T56	0	8	0	0
T68	0	38	0	0
T79	0	123	0	0
T92	0	29	0	0
T95	0	310	0	0
T123	0	18	0	0

sw_rst_ctrl_n_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12566271	12314	0	0
T10	10268	164	0	0
T11	117542	425	0	0
T12	226719	0	0	0
T13	21771	0	0	0
T14	3878	0	0	0
T15	5479	0	0	0
T16	5098	0	0	0
T26	1429	0	0	0
T36	1269	0	0	0
T47	0	130	0	0
T51	200885	744	0	0
T56	0	12	0	0
T68	0	36	0	0
T79	0	123	0	0
T92	0	35	0	0
T95	0	249	0	0
T123	0	13	0	0

sw_rst_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12566271	6135	0	0
T10	10268	24	0	0
T11	117542	170	0	0
T12	226719	0	0	0
T13	21771	0	0	0
T14	3878	0	0	0
T15	5479	0	0	0
T16	5098	0	0	0
T26	1429	0	0	0
T36	1269	0	0	0
T47	0	26	0	0
T51	200885	257	0	0
T56	0	6	0	0
T79	0	32	0	0
T92	0	14	0	0
T95	0	179	0	0
T123	0	7	0	0
T124	0	34	0	0

sw_rst_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12566271	6306	0	0
T10	10268	39	0	0
T11	117542	132	0	0
T12	226719	0	0	0
T13	21771	0	0	0
T14	3878	0	0	0
T15	5479	0	0	0
T16	5098	0	0	0
T26	1429	0	0	0
T36	1269	0	0	0
T47	0	38	0	0
T51	200885	293	0	0
T56	0	8	0	0
T79	0	29	0	0
T92	0	66	0	0
T95	0	226	0	0
T123	0	7	0	0
T124	0	33	0	0

sw_rst_regwen_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12566271	6400	0	0
T10	10268	40	0	0
T11	117542	147	0	0
T12	226719	0	0	0
T13	21771	0	0	0
T14	3878	0	0	0
T15	5479	0	0	0
T16	5098	0	0	0
T26	1429	0	0	0
T36	1269	0	0	0
T47	0	42	0	0
T51	200885	271	0	0
T56	0	6	0	0
T79	0	33	0	0
T92	0	34	0	0
T95	0	166	0	0
T123	0	4	0	0
T124	0	38	0	0

sw_rst_regwen_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12566271	6225	0	0
T10	10268	44	0	0
T11	117542	122	0	0
T12	226719	0	0	0
T13	21771	0	0	0
T14	3878	0	0	0
T15	5479	0	0	0
T16	5098	0	0	0
T26	1429	0	0	0
T36	1269	0	0	0
T47	0	22	0	0
T51	200885	241	0	0
T56	0	7	0	0
T79	0	28	0	0
T92	0	45	0	0
T95	0	149	0	0
T123	0	10	0	0
T124	0	37	0	0

sw_rst_regwen_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12566271	6382	0	0
T10	10268	28	0	0
T11	117542	172	0	0
T12	226719	0	0	0
T13	21771	0	0	0
T14	3878	0	0	0
T15	5479	0	0	0
T16	5098	0	0	0
T26	1429	0	0	0
T36	1269	0	0	0
T47	0	28	0	0
T51	200885	248	0	0
T56	0	12	0	0
T79	0	32	0	0
T92	0	44	0	0
T95	0	204	0	0
T123	0	8	0	0
T124	0	37	0	0

sw_rst_regwen_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12566271	6427	0	0
T10	10268	20	0	0
T11	117542	152	0	0
T12	226719	0	0	0
T13	21771	0	0	0
T14	3878	0	0	0
T15	5479	0	0	0
T16	5098	0	0	0
T26	1429	0	0	0
T36	1269	0	0	0
T47	0	20	0	0
T51	200885	275	0	0
T56	0	13	0	0
T79	0	33	0	0
T92	0	28	0	0
T95	0	219	0	0
T123	0	5	0	0
T124	0	26	0	0

sw_rst_regwen_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12566271	6402	0	0
T10	10268	34	0	0
T11	117542	146	0	0
T12	226719	0	0	0
T13	21771	0	0	0
T14	3878	0	0	0
T15	5479	0	0	0
T16	5098	0	0	0
T26	1429	0	0	0
T36	1269	0	0	0
T47	0	41	0	0
T51	200885	267	0	0
T56	0	8	0	0
T79	0	40	0	0
T92	0	46	0	0
T95	0	171	0	0
T123	0	8	0	0
T124	0	26	0	0

sw_rst_regwen_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12566271	6367	0	0
T10	10268	35	0	0
T11	117542	134	0	0
T12	226719	0	0	0
T13	21771	0	0	0
T14	3878	0	0	0
T15	5479	0	0	0
T16	5098	0	0	0
T26	1429	0	0	0
T36	1269	0	0	0
T47	0	28	0	0
T51	200885	275	0	0
T56	0	8	0	0
T79	0	13	0	0
T92	0	38	0	0
T95	0	209	0	0
T123	0	2	0	0
T124	0	26	0	0