Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	574743	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

345948

1

T2

9

T3

1111

T4

1132

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	489552	1			T3	1798		T4	1702		T5	1414
values[0x0]	215581	1			T2	16		T3	614		T4	668
values[0x1]	215558	1			T2	15		T3	604		T4	669

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	482370	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

438321

1

T2

12

T3

1420

T4

1430

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	3169	1			T3	8		T4	13		T7	35
valid_sources[0x01]	3888	1			T3	6		T4	25		T5	10
valid_sources[0x02]	3171	1			T3	15		T4	9		T5	16
valid_sources[0x03]	3010	1			T3	19		T4	9		T5	11
valid_sources[0x04]	3865	1			T3	9		T4	23		T5	6
valid_sources[0x05]	3740	1			T3	13		T4	13		T5	19
valid_sources[0x06]	3040	1			T3	7		T4	13		T5	2
valid_sources[0x07]	3016	1			T3	8		T4	8		T5	5
valid_sources[0x08]	3169	1			T3	8		T4	16		T5	6
valid_sources[0x09]	3117	1			T3	5		T4	9		T5	4
valid_sources[0x0a]	6329	1			T3	15		T4	11		T5	30
valid_sources[0x0b]	3324	1			T3	6		T4	11		T5	27
valid_sources[0x0c]	3242	1			T3	5		T4	9		T5	11
valid_sources[0x0d]	3444	1			T3	11		T4	15		T5	3
valid_sources[0x0e]	3610	1			T3	13		T4	23		T5	7
valid_sources[0x0f]	3105	1			T3	4		T4	12		T5	17
valid_sources[0x10]	2728	1			T3	18		T4	10		T5	20
valid_sources[0x11]	6514	1			T3	19		T4	14		T5	9
valid_sources[0x12]	2868	1			T3	10		T4	13		T5	2
valid_sources[0x13]	3506	1			T3	16		T4	15		T5	5
valid_sources[0x14]	3872	1			T3	6		T4	11		T5	2
valid_sources[0x15]	4111	1			T3	11		T4	20		T5	2
valid_sources[0x16]	3548	1			T3	13		T4	20		T5	4
valid_sources[0x17]	3813	1			T3	13		T4	15		T5	28
valid_sources[0x18]	3406	1			T3	9		T4	13		T5	4
valid_sources[0x19]	4210	1			T3	11		T4	4		T5	10
valid_sources[0x1a]	3116	1			T3	14		T4	9		T5	7
valid_sources[0x1b]	2885	1			T3	16		T4	20		T5	19
valid_sources[0x1c]	2898	1			T3	7		T4	12		T5	3
valid_sources[0x1d]	3497	1			T3	16		T4	9		T5	1
valid_sources[0x1e]	6170	1			T3	10		T4	11		T5	15
valid_sources[0x1f]	3021	1			T3	8		T4	16		T5	9
valid_sources[0x20]	2782	1			T3	8		T4	8		T5	3
valid_sources[0x21]	3548	1			T3	15		T4	8		T5	8
valid_sources[0x22]	3384	1			T3	10		T4	6		T5	8
valid_sources[0x23]	3364	1			T3	9		T4	8		T5	14
valid_sources[0x24]	4358	1			T3	14		T4	9		T5	14
valid_sources[0x25]	3771	1			T3	15		T4	9		T7	22
valid_sources[0x26]	2843	1			T3	11		T4	5		T5	12
valid_sources[0x27]	2843	1			T3	6		T4	18		T5	16
valid_sources[0x28]	3554	1			T3	6		T4	15		T5	9
valid_sources[0x29]	3528	1			T3	10		T4	9		T5	43
valid_sources[0x2a]	3051	1			T3	10		T4	12		T5	5
valid_sources[0x2b]	4927	1			T3	16		T4	13		T5	7
valid_sources[0x2c]	3687	1			T3	12		T4	13		T5	17
valid_sources[0x2d]	2862	1			T3	8		T4	13		T5	10
valid_sources[0x2e]	3327	1			T3	11		T4	18		T5	5
valid_sources[0x2f]	3122	1			T3	10		T4	14		T5	10
valid_sources[0x30]	2740	1			T3	15		T4	12		T5	10
valid_sources[0x31]	3141	1			T3	15		T4	10		T5	24
valid_sources[0x32]	3299	1			T3	12		T4	10		T5	9
valid_sources[0x33]	3554	1			T3	13		T4	18		T5	9
valid_sources[0x34]	6257	1			T3	12		T4	17		T5	9
valid_sources[0x35]	6308	1			T3	4		T4	15		T7	51
valid_sources[0x36]	7009	1			T3	10		T4	14		T5	4
valid_sources[0x37]	3143	1			T3	12		T4	10		T5	11
valid_sources[0x38]	2860	1			T3	4		T4	12		T7	45
valid_sources[0x39]	6112	1			T3	7		T4	12		T5	12
valid_sources[0x3a]	6730	1			T3	7		T4	9		T7	39
valid_sources[0x3b]	3377	1			T3	7		T4	11		T7	34
valid_sources[0x3c]	2932	1			T3	8		T4	8		T7	43
valid_sources[0x3d]	3229	1			T3	13		T4	9		T5	2
valid_sources[0x3e]	3497	1			T3	16		T4	9		T5	1
valid_sources[0x3f]	3746	1			T3	6		T4	10		T5	4
valid_sources[0x40]	2571	1			T3	8		T4	12		T5	15
valid_sources[0x41]	3266	1			T3	18		T4	15		T7	52
valid_sources[0x42]	2947	1			T3	15		T4	12		T5	14
valid_sources[0x43]	3300	1			T3	16		T4	15		T5	11
valid_sources[0x44]	6425	1			T3	7		T4	9		T5	22
valid_sources[0x45]	3984	1			T3	7		T4	6		T5	9
valid_sources[0x46]	2930	1			T3	7		T4	9		T5	13
valid_sources[0x47]	4627	1			T3	5		T4	3		T5	8
valid_sources[0x48]	3029	1			T3	14		T4	12		T5	30
valid_sources[0x49]	3764	1			T3	16		T4	6		T5	7
valid_sources[0x4a]	5589	1			T3	13		T4	31		T5	25
valid_sources[0x4b]	4116	1			T3	18		T4	10		T5	5
valid_sources[0x4c]	3051	1			T3	8		T4	8		T5	8
valid_sources[0x4d]	3207	1			T3	19		T4	12		T5	9
valid_sources[0x4e]	3560	1			T3	18		T4	8		T5	8
valid_sources[0x4f]	4135	1			T3	11		T4	13		T5	18
valid_sources[0x50]	3621	1			T3	6		T4	7		T5	7
valid_sources[0x51]	3137	1			T3	10		T4	10		T5	4
valid_sources[0x52]	4665	1			T3	21		T4	8		T5	9
valid_sources[0x53]	3063	1			T3	19		T4	13		T5	2
valid_sources[0x54]	3886	1			T3	14		T4	10		T5	7
valid_sources[0x55]	3494	1			T3	4		T4	11		T5	6
valid_sources[0x56]	2870	1			T3	11		T4	7		T5	7
valid_sources[0x57]	2482	1			T3	10		T4	7		T5	8
valid_sources[0x58]	3610	1			T3	16		T4	9		T5	6
valid_sources[0x59]	3165	1			T3	16		T4	18		T5	7
valid_sources[0x5a]	3467	1			T3	12		T4	10		T5	28
valid_sources[0x5b]	3189	1			T3	7		T4	10		T5	5
valid_sources[0x5c]	5554	1			T3	12		T4	9		T7	29
valid_sources[0x5d]	3603	1			T3	10		T4	13		T5	5
valid_sources[0x5e]	3165	1			T3	8		T4	8		T5	19
valid_sources[0x5f]	3611	1			T3	10		T4	15		T5	1
valid_sources[0x60]	3333	1			T3	9		T4	5		T5	5
valid_sources[0x61]	3445	1			T3	10		T4	16		T5	4
valid_sources[0x62]	3067	1			T3	9		T4	12		T5	3
valid_sources[0x63]	3044	1			T3	15		T4	15		T5	8
valid_sources[0x64]	5044	1			T3	11		T4	11		T5	1
valid_sources[0x65]	3717	1			T3	11		T4	9		T5	10
valid_sources[0x66]	4151	1			T3	10		T4	10		T5	2
valid_sources[0x67]	3058	1			T3	8		T4	8		T5	7
valid_sources[0x68]	3665	1			T3	9		T4	16		T5	1
valid_sources[0x69]	3327	1			T3	20		T4	8		T5	13
valid_sources[0x6a]	2850	1			T3	16		T4	18		T5	1
valid_sources[0x6b]	2925	1			T3	5		T4	13		T5	15
valid_sources[0x6c]	2744	1			T3	4		T4	10		T5	20
valid_sources[0x6d]	6418	1			T3	11		T4	7		T5	14
valid_sources[0x6e]	3133	1			T3	12		T4	15		T5	15
valid_sources[0x6f]	3026	1			T3	12		T4	11		T5	36
valid_sources[0x70]	3903	1			T3	12		T4	12		T7	86
valid_sources[0x71]	3908	1			T3	13		T4	8		T5	22
valid_sources[0x72]	6381	1			T3	7		T4	6		T5	15
valid_sources[0x73]	2920	1			T3	8		T4	19		T5	12
valid_sources[0x74]	3074	1			T3	14		T4	8		T5	4
valid_sources[0x75]	3325	1			T3	3		T4	10		T7	63
valid_sources[0x76]	3392	1			T3	12		T4	6		T7	31
valid_sources[0x77]	2934	1			T3	6		T4	12		T5	19
valid_sources[0x78]	3233	1			T3	14		T4	13		T5	7
valid_sources[0x79]	3087	1			T3	14		T4	12		T5	19
valid_sources[0x7a]	3103	1			T3	19		T4	17		T7	41
valid_sources[0x7b]	3324	1			T3	11		T4	7		T5	7
valid_sources[0x7c]	2939	1			T3	10		T4	12		T5	14
valid_sources[0x7d]	2882	1			T3	11		T4	16		T5	2
valid_sources[0x7e]	2893	1			T3	7		T4	18		T5	2
valid_sources[0x7f]	3369	1			T3	4		T4	8		T5	6
valid_sources[0x80]	3756	1			T3	22		T4	12		T5	8

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

229764

1

T3

823

T4

797

T5

700

values[0x0]

all_enables

biggest_size

75551

1

T2

6

T3

198

T4

223

values[0x1]

all_enables

biggest_size

40633

1

T2

3

T3

90

T4

112