Unified Coverage Report :: Module :: pwrmgr_rstmgr_sva_if

Module : pwrmgr_rstmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_rstmgr_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_rstmgr_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_rstmgr_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	33	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' or '../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
33	1	1

---

Cond Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       33
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T3,T4

---

Assert Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions_per_power_domains[0].LcHandshakeOff_A	10294503	12305	0	0
gen_assertions_per_power_domains[0].LcHandshakeOn_A	10294503	113709	0	0
gen_assertions_per_power_domains[0].SysHandshakeOff_A	10294503	6009541	0	0
gen_assertions_per_power_domains[0].SysHandshakeOn_A	10294503	181072	0	0
gen_assertions_per_power_domains[1].LcHandshakeOff_A	10294503	12305	0	0
gen_assertions_per_power_domains[1].LcHandshakeOn_A	10294503	113709	0	0
gen_assertions_per_power_domains[1].SysHandshakeOff_A	10294503	6009541	0	0
gen_assertions_per_power_domains[1].SysHandshakeOn_A	10294503	181072	0	0

gen_assertions_per_power_domains[0].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10294503	12305	0	0
T3	34860	28	0	0
T4	32345	40	0	0
T5	27422	28	0	0
T6	1634	6	0	0
T7	118947	135	0	0
T8	5692	0	0	0
T9	5274	0	0	0
T10	3330	4	0	0
T11	10093	0	0	0
T12	2563	4	0	0
T13	0	43	0	0
T15	0	36	0	0
T16	0	3	0	0

gen_assertions_per_power_domains[0].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10294503	113709	0	0
T3	34860	260	0	0
T4	32345	366	0	0
T5	27422	259	0	0
T6	1634	54	0	0
T7	118947	1245	0	0
T8	5692	0	0	0
T9	5274	0	0	0
T10	3330	38	0	0
T11	10093	0	0	0
T12	2563	37	0	0
T13	0	392	0	0
T15	0	330	0	0
T16	0	27	0	0

gen_assertions_per_power_domains[0].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10294503	6009541	0	0
T1	5792	706	0	0
T2	1596	1007	0	0
T3	34860	22793	0	0
T4	32345	23205	0	0
T5	27422	18881	0	0
T6	1634	946	0	0
T7	118947	89879	0	0
T8	5692	569	0	0
T9	5274	563	0	0
T10	3330	2324	0	0

gen_assertions_per_power_domains[0].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10294503	181072	0	0
T3	34860	421	0	0
T4	32345	602	0	0
T5	27422	432	0	0
T6	1634	93	0	0
T7	118947	1968	0	0
T8	5692	0	0	0
T9	5274	0	0	0
T10	3330	57	0	0
T11	10093	0	0	0
T12	2563	58	0	0
T13	0	624	0	0
T15	0	506	0	0
T16	0	46	0	0

gen_assertions_per_power_domains[1].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10294503	12305	0	0
T3	34860	28	0	0
T4	32345	40	0	0
T5	27422	28	0	0
T6	1634	6	0	0
T7	118947	135	0	0
T8	5692	0	0	0
T9	5274	0	0	0
T10	3330	4	0	0
T11	10093	0	0	0
T12	2563	4	0	0
T13	0	43	0	0
T15	0	36	0	0
T16	0	3	0	0

gen_assertions_per_power_domains[1].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10294503	113709	0	0
T3	34860	260	0	0
T4	32345	366	0	0
T5	27422	259	0	0
T6	1634	54	0	0
T7	118947	1245	0	0
T8	5692	0	0	0
T9	5274	0	0	0
T10	3330	38	0	0
T11	10093	0	0	0
T12	2563	37	0	0
T13	0	392	0	0
T15	0	330	0	0
T16	0	27	0	0

gen_assertions_per_power_domains[1].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10294503	6009541	0	0
T1	5792	706	0	0
T2	1596	1007	0	0
T3	34860	22793	0	0
T4	32345	23205	0	0
T5	27422	18881	0	0
T6	1634	946	0	0
T7	118947	89879	0	0
T8	5692	569	0	0
T9	5274	563	0	0
T10	3330	2324	0	0

gen_assertions_per_power_domains[1].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10294503	181072	0	0
T3	34860	421	0	0
T4	32345	602	0	0
T5	27422	432	0	0
T6	1634	93	0	0
T7	118947	1968	0	0
T8	5692	0	0	0
T9	5274	0	0	0
T10	3330	57	0	0
T11	10093	0	0	0
T12	2563	58	0	0
T13	0	624	0	0
T15	0	506	0	0
T16	0	46	0	0