Unified Coverage Report :: Module :: rstmgr_cascading_sva_if

Module : rstmgr_cascading_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_cascading_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_cascading_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_cascading_sva_if

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	100	1	1	100.00
ALWAYS	103	1	1	100.00
ALWAYS	107	1	1	100.00
ALWAYS	127	1	1	100.00
ALWAYS	138	1	1	100.00
ALWAYS	141	1	1	100.00
ALWAYS	144	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
100	1	1
103	1	1
107	1	1
127	1	1
138	1	1
141	1	1
144	1	1

---

Cond Coverage for Module : rstmgr_cascading_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       103
 EXPRESSION (((!scanmode)) || scan_rst_ni)
             ------1------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T3,T4,T5
0	1	Covered	T3,T4,T5
1	0	Covered	T3,T4,T5

 LINE       107
 EXPRESSION (por_n_i[rstmgr_pkg::DomainAonSel] && ((!scanmode)))
             ----------------1----------------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T3,T4,T5
1	1	Covered	T1,T2,T3

---

Assert Coverage for Module : rstmgr_cascading_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	31	31	100.00	31	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	31	31	100.00	31	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CascadeEffAonToRstPorAboveFall_A	48502320	7878	0	0
CascadeEffAonToRstPorAboveRise_A	48502320	7878	0	0
CascadeEffAonToRstPorIoAboveFall_A	46560777	7878	0	0
CascadeEffAonToRstPorIoAboveRise_A	46560777	7878	0	0
CascadeEffAonToRstPorIoDiv2AboveFall_A	23280748	7878	0	0
CascadeEffAonToRstPorIoDiv2AboveRise_A	23280748	7878	0	0
CascadeEffAonToRstPorIoDiv4AboveFall_A	11640161	7878	0	0
CascadeEffAonToRstPorIoDiv4AboveRise_A	11640161	7878	0	0
CascadeEffAonToRstPorUcbAboveFall_A	23280903	7878	0	0
CascadeEffAonToRstPorUcbAboveRise_A	23280903	7878	0	0
CascadeLcToLcAboveFall_A	48502320	20183	0	0
CascadeLcToLcAboveRise_A	48502320	20183	0	0
CascadeLcToLcAonAboveFall_A	1469688	20183	0	0
CascadeLcToLcAonAboveRise_A	1469688	20183	0	0
CascadeLcToLcShadowedAboveFall_A	48502320	20183	0	0
CascadeLcToLcShadowedAboveRise_A	48502320	20183	0	0
CascadePorToAonAboveFall_A	1469688	6319	0	0
CascadeSysToSysAboveFall_A	48502320	20183	0	0
CascadeSysToSysAboveRise_A	48502320	20183	0	0
ScanRstToAonRise_A	1469688	192	0	0
StablePorToAonRise_A	1469688	7878	0	0
g_power_domains[0].CascadeLcToSysAboveFall_A	10294503	20183	0	0
g_power_domains[0].CascadeLcToSysAboveRise_A	10294503	20183	0	0
g_power_domains[0].CascadeLocalRstToLcAboveFall_A	10294503	20183	0	0
g_power_domains[0].CascadeLocalRstToLcAboveRise_A	10294503	20183	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A	11640161	20183	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A	11640161	20183	0	0
g_power_domains[1].CascadeLcToSysAboveFall_A	10294503	20183	0	0
g_power_domains[1].CascadeLcToSysAboveRise_A	10294503	20183	0	0
g_power_domains[1].CascadeLocalRstToLcAboveFall_A	10294503	20183	0	0
g_power_domains[1].CascadeLocalRstToLcAboveRise_A	10294503	20183	0	0

CascadeEffAonToRstPorAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	48502320	7878	0	0
T1	24817	8	0	0
T2	6931	1	0	0
T3	164809	27	0	0
T4	157187	20	0	0
T5	129279	19	0	0
T6	9003	1	0	0
T7	561952	64	0	0
T8	24389	8	0	0
T9	24259	8	0	0
T10	14876	2	0	0

CascadeEffAonToRstPorAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	48502320	7878	0	0
T1	24817	8	0	0
T2	6931	1	0	0
T3	164809	27	0	0
T4	157187	20	0	0
T5	129279	19	0	0
T6	9003	1	0	0
T7	561952	64	0	0
T8	24389	8	0	0
T9	24259	8	0	0
T10	14876	2	0	0

CascadeEffAonToRstPorIoAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	46560777	7878	0	0
T1	23810	8	0	0
T2	6654	1	0	0
T3	158193	27	0	0
T4	150884	20	0	0
T5	124085	19	0	0
T6	8641	1	0	0
T7	539447	64	0	0
T8	23424	8	0	0
T9	23279	8	0	0
T10	14281	2	0	0

CascadeEffAonToRstPorIoAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	46560777	7878	0	0
T1	23810	8	0	0
T2	6654	1	0	0
T3	158193	27	0	0
T4	150884	20	0	0
T5	124085	19	0	0
T6	8641	1	0	0
T7	539447	64	0	0
T8	23424	8	0	0
T9	23279	8	0	0
T10	14281	2	0	0

CascadeEffAonToRstPorIoDiv2AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23280748	7878	0	0
T1	11908	8	0	0
T2	3326	1	0	0
T3	79097	27	0	0
T4	75454	20	0	0
T5	62052	19	0	0
T6	4320	1	0	0
T7	269739	64	0	0
T8	11709	8	0	0
T9	11641	8	0	0
T10	7140	2	0	0

CascadeEffAonToRstPorIoDiv2AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23280748	7878	0	0
T1	11908	8	0	0
T2	3326	1	0	0
T3	79097	27	0	0
T4	75454	20	0	0
T5	62052	19	0	0
T6	4320	1	0	0
T7	269739	64	0	0
T8	11709	8	0	0
T9	11641	8	0	0
T10	7140	2	0	0

CascadeEffAonToRstPorIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11640161	7878	0	0
T1	5947	8	0	0
T2	1663	1	0	0
T3	39551	27	0	0
T4	37724	20	0	0
T5	31030	19	0	0
T6	2159	1	0	0
T7	134874	64	0	0
T8	5854	8	0	0
T9	5819	8	0	0
T10	3568	2	0	0

CascadeEffAonToRstPorIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11640161	7878	0	0
T1	5947	8	0	0
T2	1663	1	0	0
T3	39551	27	0	0
T4	37724	20	0	0
T5	31030	19	0	0
T6	2159	1	0	0
T7	134874	64	0	0
T8	5854	8	0	0
T9	5819	8	0	0
T10	3568	2	0	0

CascadeEffAonToRstPorUcbAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23280903	7878	0	0
T1	11908	8	0	0
T2	3326	1	0	0
T3	79097	27	0	0
T4	75438	20	0	0
T5	62051	19	0	0
T6	4321	1	0	0
T7	269734	64	0	0
T8	11707	8	0	0
T9	11635	8	0	0
T10	7141	2	0	0

CascadeEffAonToRstPorUcbAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23280903	7878	0	0
T1	11908	8	0	0
T2	3326	1	0	0
T3	79097	27	0	0
T4	75438	20	0	0
T5	62051	19	0	0
T6	4321	1	0	0
T7	269734	64	0	0
T8	11707	8	0	0
T9	11635	8	0	0
T10	7141	2	0	0

CascadeLcToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	48502320	20183	0	0
T1	24817	8	0	0
T2	6931	1	0	0
T3	164809	55	0	0
T4	157187	60	0	0
T5	129279	47	0	0
T6	9003	7	0	0
T7	561952	199	0	0
T8	24389	8	0	0
T9	24259	8	0	0
T10	14876	6	0	0

CascadeLcToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	48502320	20183	0	0
T1	24817	8	0	0
T2	6931	1	0	0
T3	164809	55	0	0
T4	157187	60	0	0
T5	129279	47	0	0
T6	9003	7	0	0
T7	561952	199	0	0
T8	24389	8	0	0
T9	24259	8	0	0
T10	14876	6	0	0

CascadeLcToLcAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1469688	20183	0	0
T1	746	8	0	0
T2	207	1	0	0
T3	5024	55	0	0
T4	4767	60	0	0
T5	3923	47	0	0
T6	269	7	0	0
T7	17068	199	0	0
T8	734	8	0	0
T9	729	8	0	0
T10	445	6	0	0

CascadeLcToLcAonAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1469688	20183	0	0
T1	746	8	0	0
T2	207	1	0	0
T3	5024	55	0	0
T4	4767	60	0	0
T5	3923	47	0	0
T6	269	7	0	0
T7	17068	199	0	0
T8	734	8	0	0
T9	729	8	0	0
T10	445	6	0	0

CascadeLcToLcShadowedAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	48502320	20183	0	0
T1	24817	8	0	0
T2	6931	1	0	0
T3	164809	55	0	0
T4	157187	60	0	0
T5	129279	47	0	0
T6	9003	7	0	0
T7	561952	199	0	0
T8	24389	8	0	0
T9	24259	8	0	0
T10	14876	6	0	0

CascadeLcToLcShadowedAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	48502320	20183	0	0
T1	24817	8	0	0
T2	6931	1	0	0
T3	164809	55	0	0
T4	157187	60	0	0
T5	129279	47	0	0
T6	9003	7	0	0
T7	561952	199	0	0
T8	24389	8	0	0
T9	24259	8	0	0
T10	14876	6	0	0

CascadePorToAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1469688	6319	0	0
T1	746	8	0	0
T2	207	1	0	0
T3	5024	13	0	0
T4	4767	10	0	0
T5	3923	9	0	0
T6	269	1	0	0
T7	17068	30	0	0
T8	734	8	0	0
T9	729	8	0	0
T10	445	1	0	0

CascadeSysToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	48502320	20183	0	0
T1	24817	8	0	0
T2	6931	1	0	0
T3	164809	55	0	0
T4	157187	60	0	0
T5	129279	47	0	0
T6	9003	7	0	0
T7	561952	199	0	0
T8	24389	8	0	0
T9	24259	8	0	0
T10	14876	6	0	0

CascadeSysToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	48502320	20183	0	0
T1	24817	8	0	0
T2	6931	1	0	0
T3	164809	55	0	0
T4	157187	60	0	0
T5	129279	47	0	0
T6	9003	7	0	0
T7	561952	199	0	0
T8	24389	8	0	0
T9	24259	8	0	0
T10	14876	6	0	0

ScanRstToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1469688	192	0	0
T7	17068	4	0	0
T8	734	0	0	0
T9	729	0	0	0
T10	445	0	0	0
T11	1268	0	0	0
T12	355	0	0	0
T13	4737	2	0	0
T14	995	0	0	0
T15	0	1	0	0
T60	0	1	0	0
T61	0	1	0	0
T62	0	1	0	0
T63	0	6	0	0
T66	0	1	0	0
T79	216	0	0	0
T92	732	0	0	0
T97	0	1	0	0
T100	0	8	0	0

StablePorToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1469688	7878	0	0
T1	746	8	0	0
T2	207	1	0	0
T3	5024	27	0	0
T4	4767	20	0	0
T5	3923	19	0	0
T6	269	1	0	0
T7	17068	64	0	0
T8	734	8	0	0
T9	729	8	0	0
T10	445	2	0	0

g_power_domains[0].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10294503	20183	0	0
T1	5792	8	0	0
T2	1596	1	0	0
T3	34860	55	0	0
T4	32345	60	0	0
T5	27422	47	0	0
T6	1634	7	0	0
T7	118947	199	0	0
T8	5692	8	0	0
T9	5274	8	0	0
T10	3330	6	0	0

g_power_domains[0].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10294503	20183	0	0
T1	5792	8	0	0
T2	1596	1	0	0
T3	34860	55	0	0
T4	32345	60	0	0
T5	27422	47	0	0
T6	1634	7	0	0
T7	118947	199	0	0
T8	5692	8	0	0
T9	5274	8	0	0
T10	3330	6	0	0

g_power_domains[0].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10294503	20183	0	0
T1	5792	8	0	0
T2	1596	1	0	0
T3	34860	55	0	0
T4	32345	60	0	0
T5	27422	47	0	0
T6	1634	7	0	0
T7	118947	199	0	0
T8	5692	8	0	0
T9	5274	8	0	0
T10	3330	6	0	0

g_power_domains[0].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10294503	20183	0	0
T1	5792	8	0	0
T2	1596	1	0	0
T3	34860	55	0	0
T4	32345	60	0	0
T5	27422	47	0	0
T6	1634	7	0	0
T7	118947	199	0	0
T8	5692	8	0	0
T9	5274	8	0	0
T10	3330	6	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11640161	20183	0	0
T1	5947	8	0	0
T2	1663	1	0	0
T3	39551	55	0	0
T4	37724	60	0	0
T5	31030	47	0	0
T6	2159	7	0	0
T7	134874	199	0	0
T8	5854	8	0	0
T9	5819	8	0	0
T10	3568	6	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11640161	20183	0	0
T1	5947	8	0	0
T2	1663	1	0	0
T3	39551	55	0	0
T4	37724	60	0	0
T5	31030	47	0	0
T6	2159	7	0	0
T7	134874	199	0	0
T8	5854	8	0	0
T9	5819	8	0	0
T10	3568	6	0	0

g_power_domains[1].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10294503	20183	0	0
T1	5792	8	0	0
T2	1596	1	0	0
T3	34860	55	0	0
T4	32345	60	0	0
T5	27422	47	0	0
T6	1634	7	0	0
T7	118947	199	0	0
T8	5692	8	0	0
T9	5274	8	0	0
T10	3330	6	0	0

g_power_domains[1].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10294503	20183	0	0
T1	5792	8	0	0
T2	1596	1	0	0
T3	34860	55	0	0
T4	32345	60	0	0
T5	27422	47	0	0
T6	1634	7	0	0
T7	118947	199	0	0
T8	5692	8	0	0
T9	5274	8	0	0
T10	3330	6	0	0

g_power_domains[1].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10294503	20183	0	0
T1	5792	8	0	0
T2	1596	1	0	0
T3	34860	55	0	0
T4	32345	60	0	0
T5	27422	47	0	0
T6	1634	7	0	0
T7	118947	199	0	0
T8	5692	8	0	0
T9	5274	8	0	0
T10	3330	6	0	0

g_power_domains[1].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10294503	20183	0	0
T1	5792	8	0	0
T2	1596	1	0	0
T3	34860	55	0	0
T4	32345	60	0	0
T5	27422	47	0	0
T6	1634	7	0	0
T7	118947	199	0	0
T8	5692	8	0	0
T9	5274	8	0	0
T10	3330	6	0	0