Unified Coverage Report :: Module :: rstmgr_sw_rst_sva_if

Module : rstmgr_sw_rst_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_sw_rst_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_sw_rst_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_sw_rst_sva_if

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
21	8	8

---

Cond Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Covered	Percent
Conditions	24	24	100.00
Logical	24	24	100.00
Non-Logical	0	0
Event	0	0

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[0])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T7,T11
1	0	Covered	T1,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[1])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T7,T11
1	0	Covered	T1,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[2])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T11,T14
1	0	Covered	T1,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[3])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T11,T12
1	0	Covered	T1,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[4])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T11,T14
1	0	Covered	T1,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[5])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T11,T14
1	0	Covered	T1,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[6])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T11,T14
1	0	Covered	T1,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[7])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T11,T14
1	0	Covered	T1,T3,T4

---

Assert Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions[0].RstEnOff_A	11640161	13111	0	0
gen_assertions[0].RstEnOn_A	11640161	999	0	0
gen_assertions[0].RstNOff_A	11640161	13111	0	0
gen_assertions[0].RstNOn_A	11640161	999	0	0
gen_assertions[1].RstEnOff_A	46560777	11949	0	0
gen_assertions[1].RstEnOn_A	46560777	946	0	0
gen_assertions[1].RstNOff_A	46560777	11949	0	0
gen_assertions[1].RstNOn_A	46560777	946	0	0
gen_assertions[2].RstEnOff_A	23280748	12027	0	0
gen_assertions[2].RstEnOn_A	23280748	968	0	0
gen_assertions[2].RstNOff_A	23280748	12027	0	0
gen_assertions[2].RstNOn_A	23280748	968	0	0
gen_assertions[3].RstEnOff_A	23280903	12076	0	0
gen_assertions[3].RstEnOn_A	23280903	1005	0	0
gen_assertions[3].RstNOff_A	23280903	12076	0	0
gen_assertions[3].RstNOn_A	23280903	1005	0	0
gen_assertions[4].RstEnOff_A	1469688	19846	0	0
gen_assertions[4].RstEnOn_A	1469688	1075	0	0
gen_assertions[4].RstNOff_A	1469688	19846	0	0
gen_assertions[4].RstNOn_A	1469688	1075	0	0
gen_assertions[5].RstEnOff_A	11640161	13390	0	0
gen_assertions[5].RstEnOn_A	11640161	1125	0	0
gen_assertions[5].RstNOff_A	11640161	13390	0	0
gen_assertions[5].RstNOn_A	11640161	1125	0	0
gen_assertions[6].RstEnOff_A	11640161	13418	0	0
gen_assertions[6].RstEnOn_A	11640161	1153	0	0
gen_assertions[6].RstNOff_A	11640161	13418	0	0
gen_assertions[6].RstNOn_A	11640161	1153	0	0
gen_assertions[7].RstEnOff_A	11640161	13481	0	0
gen_assertions[7].RstEnOn_A	11640161	1210	0	0
gen_assertions[7].RstNOff_A	11640161	13481	0	0
gen_assertions[7].RstNOn_A	11640161	1210	0	0

gen_assertions[0].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11640161	13111	0	0
T3	39551	28	0	0
T4	37724	40	0	0
T5	31030	28	0	0
T6	2159	6	0	0
T7	134874	162	0	0
T8	5854	0	0	0
T9	5819	0	0	0
T10	3568	4	0	0
T11	10158	5	0	0
T12	2850	4	0	0
T13	0	43	0	0
T14	0	5	0	0

gen_assertions[0].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11640161	999	0	0
T6	2159	1	0	0
T7	134874	27	0	0
T8	5854	0	0	0
T9	5819	0	0	0
T10	3568	0	0	0
T11	10158	5	0	0
T12	2850	0	0	0
T13	37090	0	0	0
T14	7968	5	0	0
T16	0	1	0	0
T27	0	1	0	0
T28	0	5	0	0
T30	0	1	0	0
T33	0	19	0	0
T67	0	3	0	0
T79	1743	0	0	0

gen_assertions[0].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11640161	13111	0	0
T3	39551	28	0	0
T4	37724	40	0	0
T5	31030	28	0	0
T6	2159	6	0	0
T7	134874	162	0	0
T8	5854	0	0	0
T9	5819	0	0	0
T10	3568	4	0	0
T11	10158	5	0	0
T12	2850	4	0	0
T13	0	43	0	0
T14	0	5	0	0

gen_assertions[0].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11640161	999	0	0
T6	2159	1	0	0
T7	134874	27	0	0
T8	5854	0	0	0
T9	5819	0	0	0
T10	3568	0	0	0
T11	10158	5	0	0
T12	2850	0	0	0
T13	37090	0	0	0
T14	7968	5	0	0
T16	0	1	0	0
T27	0	1	0	0
T28	0	5	0	0
T30	0	1	0	0
T33	0	19	0	0
T67	0	3	0	0
T79	1743	0	0	0

gen_assertions[1].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	46560777	11949	0	0
T3	158193	27	0	0
T4	150884	37	0	0
T5	124085	26	0	0
T6	8641	5	0	0
T7	539447	146	0	0
T8	23424	0	0	0
T9	23279	0	0	0
T10	14281	4	0	0
T11	40642	4	0	0
T12	11405	4	0	0
T13	0	40	0	0
T14	0	8	0	0

gen_assertions[1].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	46560777	946	0	0
T6	8641	1	0	0
T7	539447	25	0	0
T8	23424	0	0	0
T9	23279	0	0	0
T10	14281	0	0	0
T11	40642	4	0	0
T12	11405	0	0	0
T13	148351	0	0	0
T14	31877	8	0	0
T28	0	2	0	0
T33	0	14	0	0
T67	0	4	0	0
T79	6974	0	0	0
T95	0	3	0	0
T96	0	1	0	0
T97	0	20	0	0

gen_assertions[1].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	46560777	11949	0	0
T3	158193	27	0	0
T4	150884	37	0	0
T5	124085	26	0	0
T6	8641	5	0	0
T7	539447	146	0	0
T8	23424	0	0	0
T9	23279	0	0	0
T10	14281	4	0	0
T11	40642	4	0	0
T12	11405	4	0	0
T13	0	40	0	0
T14	0	8	0	0

gen_assertions[1].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	46560777	946	0	0
T6	8641	1	0	0
T7	539447	25	0	0
T8	23424	0	0	0
T9	23279	0	0	0
T10	14281	0	0	0
T11	40642	4	0	0
T12	11405	0	0	0
T13	148351	0	0	0
T14	31877	8	0	0
T28	0	2	0	0
T33	0	14	0	0
T67	0	4	0	0
T79	6974	0	0	0
T95	0	3	0	0
T96	0	1	0	0
T97	0	20	0	0

gen_assertions[2].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23280748	12027	0	0
T3	79097	27	0	0
T4	75454	37	0	0
T5	62052	26	0	0
T6	4320	5	0	0
T7	269739	139	0	0
T8	11709	0	0	0
T9	11641	0	0	0
T10	7140	4	0	0
T11	20320	8	0	0
T12	5702	4	0	0
T13	0	40	0	0
T14	0	8	0	0

gen_assertions[2].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23280748	968	0	0
T7	269739	18	0	0
T8	11709	0	0	0
T9	11641	0	0	0
T10	7140	0	0	0
T11	20320	8	0	0
T12	5702	0	0	0
T13	74184	0	0	0
T14	15939	8	0	0
T28	0	1	0	0
T30	0	1	0	0
T33	0	17	0	0
T61	0	1	0	0
T67	0	5	0	0
T79	3487	0	0	0
T92	11680	0	0	0
T95	0	3	0	0
T97	0	24	0	0

gen_assertions[2].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23280748	12027	0	0
T3	79097	27	0	0
T4	75454	37	0	0
T5	62052	26	0	0
T6	4320	5	0	0
T7	269739	139	0	0
T8	11709	0	0	0
T9	11641	0	0	0
T10	7140	4	0	0
T11	20320	8	0	0
T12	5702	4	0	0
T13	0	40	0	0
T14	0	8	0	0

gen_assertions[2].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23280748	968	0	0
T7	269739	18	0	0
T8	11709	0	0	0
T9	11641	0	0	0
T10	7140	0	0	0
T11	20320	8	0	0
T12	5702	0	0	0
T13	74184	0	0	0
T14	15939	8	0	0
T28	0	1	0	0
T30	0	1	0	0
T33	0	17	0	0
T61	0	1	0	0
T67	0	5	0	0
T79	3487	0	0	0
T92	11680	0	0	0
T95	0	3	0	0
T97	0	24	0	0

gen_assertions[3].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23280903	12076	0	0
T3	79097	27	0	0
T4	75438	37	0	0
T5	62051	26	0	0
T6	4321	5	0	0
T7	269734	146	0	0
T8	11707	0	0	0
T9	11635	0	0	0
T10	7141	4	0	0
T11	20320	8	0	0
T12	5703	5	0	0
T13	0	40	0	0
T14	0	8	0	0

gen_assertions[3].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23280903	1005	0	0
T7	269734	25	0	0
T8	11707	0	0	0
T9	11635	0	0	0
T10	7141	0	0	0
T11	20320	8	0	0
T12	5703	1	0	0
T13	74183	0	0	0
T14	15939	8	0	0
T30	0	1	0	0
T33	0	14	0	0
T67	0	4	0	0
T79	3487	0	0	0
T92	11689	0	0	0
T95	0	5	0	0
T97	0	26	0	0
T98	0	1	0	0

gen_assertions[3].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23280903	12076	0	0
T3	79097	27	0	0
T4	75438	37	0	0
T5	62051	26	0	0
T6	4321	5	0	0
T7	269734	146	0	0
T8	11707	0	0	0
T9	11635	0	0	0
T10	7141	4	0	0
T11	20320	8	0	0
T12	5703	5	0	0
T13	0	40	0	0
T14	0	8	0	0

gen_assertions[3].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23280903	1005	0	0
T7	269734	25	0	0
T8	11707	0	0	0
T9	11635	0	0	0
T10	7141	0	0	0
T11	20320	8	0	0
T12	5703	1	0	0
T13	74183	0	0	0
T14	15939	8	0	0
T30	0	1	0	0
T33	0	14	0	0
T67	0	4	0	0
T79	3487	0	0	0
T92	11689	0	0	0
T95	0	5	0	0
T97	0	26	0	0
T98	0	1	0	0

gen_assertions[4].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1469688	19846	0	0
T1	746	3	0	0
T2	207	1	0	0
T3	5024	55	0	0
T4	4767	60	0	0
T5	3923	47	0	0
T6	269	6	0	0
T7	17068	221	0	0
T8	734	2	0	0
T9	729	2	0	0
T10	445	6	0	0

gen_assertions[4].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1469688	1075	0	0
T7	17068	26	0	0
T8	734	0	0	0
T9	729	0	0	0
T10	445	0	0	0
T11	1268	9	0	0
T12	355	0	0	0
T13	4737	0	0	0
T14	995	10	0	0
T33	0	21	0	0
T63	0	30	0	0
T65	0	1	0	0
T67	0	7	0	0
T79	216	0	0	0
T92	732	0	0	0
T95	0	6	0	0
T97	0	28	0	0
T98	0	1	0	0

gen_assertions[4].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1469688	19846	0	0
T1	746	3	0	0
T2	207	1	0	0
T3	5024	55	0	0
T4	4767	60	0	0
T5	3923	47	0	0
T6	269	6	0	0
T7	17068	221	0	0
T8	734	2	0	0
T9	729	2	0	0
T10	445	6	0	0

gen_assertions[4].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1469688	1075	0	0
T7	17068	26	0	0
T8	734	0	0	0
T9	729	0	0	0
T10	445	0	0	0
T11	1268	9	0	0
T12	355	0	0	0
T13	4737	0	0	0
T14	995	10	0	0
T33	0	21	0	0
T63	0	30	0	0
T65	0	1	0	0
T67	0	7	0	0
T79	216	0	0	0
T92	732	0	0	0
T95	0	6	0	0
T97	0	28	0	0
T98	0	1	0	0

gen_assertions[5].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11640161	13390	0	0
T3	39551	28	0	0
T4	37724	40	0	0
T5	31030	28	0	0
T6	2159	6	0	0
T7	134874	161	0	0
T8	5854	0	0	0
T9	5819	0	0	0
T10	3568	4	0	0
T11	10158	11	0	0
T12	2850	4	0	0
T13	0	43	0	0
T14	0	10	0	0

gen_assertions[5].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11640161	1125	0	0
T7	134874	26	0	0
T8	5854	0	0	0
T9	5819	0	0	0
T10	3568	0	0	0
T11	10158	11	0	0
T12	2850	0	0	0
T13	37090	0	0	0
T14	7968	10	0	0
T33	0	17	0	0
T63	0	23	0	0
T67	0	5	0	0
T79	1743	0	0	0
T92	5843	0	0	0
T95	0	6	0	0
T97	0	27	0	0
T99	0	1	0	0
T100	0	33	0	0

gen_assertions[5].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11640161	13390	0	0
T3	39551	28	0	0
T4	37724	40	0	0
T5	31030	28	0	0
T6	2159	6	0	0
T7	134874	161	0	0
T8	5854	0	0	0
T9	5819	0	0	0
T10	3568	4	0	0
T11	10158	11	0	0
T12	2850	4	0	0
T13	0	43	0	0
T14	0	10	0	0

gen_assertions[5].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11640161	1125	0	0
T7	134874	26	0	0
T8	5854	0	0	0
T9	5819	0	0	0
T10	3568	0	0	0
T11	10158	11	0	0
T12	2850	0	0	0
T13	37090	0	0	0
T14	7968	10	0	0
T33	0	17	0	0
T63	0	23	0	0
T67	0	5	0	0
T79	1743	0	0	0
T92	5843	0	0	0
T95	0	6	0	0
T97	0	27	0	0
T99	0	1	0	0
T100	0	33	0	0

gen_assertions[6].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11640161	13418	0	0
T3	39551	28	0	0
T4	37724	40	0	0
T5	31030	28	0	0
T6	2159	6	0	0
T7	134874	161	0	0
T8	5854	0	0	0
T9	5819	0	0	0
T10	3568	4	0	0
T11	10158	11	0	0
T12	2850	4	0	0
T13	0	43	0	0
T14	0	13	0	0

gen_assertions[6].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11640161	1153	0	0
T7	134874	26	0	0
T8	5854	0	0	0
T9	5819	0	0	0
T10	3568	0	0	0
T11	10158	11	0	0
T12	2850	0	0	0
T13	37090	0	0	0
T14	7968	13	0	0
T30	0	1	0	0
T33	0	17	0	0
T63	0	28	0	0
T67	0	8	0	0
T79	1743	0	0	0
T92	5843	0	0	0
T95	0	8	0	0
T97	0	23	0	0
T100	0	32	0	0

gen_assertions[6].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11640161	13418	0	0
T3	39551	28	0	0
T4	37724	40	0	0
T5	31030	28	0	0
T6	2159	6	0	0
T7	134874	161	0	0
T8	5854	0	0	0
T9	5819	0	0	0
T10	3568	4	0	0
T11	10158	11	0	0
T12	2850	4	0	0
T13	0	43	0	0
T14	0	13	0	0

gen_assertions[6].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11640161	1153	0	0
T7	134874	26	0	0
T8	5854	0	0	0
T9	5819	0	0	0
T10	3568	0	0	0
T11	10158	11	0	0
T12	2850	0	0	0
T13	37090	0	0	0
T14	7968	13	0	0
T30	0	1	0	0
T33	0	17	0	0
T63	0	28	0	0
T67	0	8	0	0
T79	1743	0	0	0
T92	5843	0	0	0
T95	0	8	0	0
T97	0	23	0	0
T100	0	32	0	0

gen_assertions[7].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11640161	13481	0	0
T3	39551	28	0	0
T4	37724	40	0	0
T5	31030	28	0	0
T6	2159	6	0	0
T7	134874	158	0	0
T8	5854	0	0	0
T9	5819	0	0	0
T10	3568	4	0	0
T11	10158	14	0	0
T12	2850	4	0	0
T13	0	43	0	0
T14	0	12	0	0

gen_assertions[7].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11640161	1210	0	0
T7	134874	23	0	0
T8	5854	0	0	0
T9	5819	0	0	0
T10	3568	0	0	0
T11	10158	14	0	0
T12	2850	0	0	0
T13	37090	0	0	0
T14	7968	12	0	0
T33	0	19	0	0
T63	0	31	0	0
T67	0	9	0	0
T79	1743	0	0	0
T92	5843	0	0	0
T95	0	9	0	0
T97	0	20	0	0
T100	0	31	0	0
T101	0	8	0	0

gen_assertions[7].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11640161	13481	0	0
T3	39551	28	0	0
T4	37724	40	0	0
T5	31030	28	0	0
T6	2159	6	0	0
T7	134874	158	0	0
T8	5854	0	0	0
T9	5819	0	0	0
T10	3568	4	0	0
T11	10158	14	0	0
T12	2850	4	0	0
T13	0	43	0	0
T14	0	12	0	0

gen_assertions[7].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11640161	1210	0	0
T7	134874	23	0	0
T8	5854	0	0	0
T9	5819	0	0	0
T10	3568	0	0	0
T11	10158	14	0	0
T12	2850	0	0	0
T13	37090	0	0	0
T14	7968	12	0	0
T33	0	19	0	0
T63	0	31	0	0
T67	0	9	0	0
T79	1743	0	0	0
T92	5843	0	0	0
T95	0	9	0	0
T97	0	20	0	0
T100	0	31	0	0
T101	0	8	0	0