Unified Coverage Report :: Module :: rstmgr_csr_assert_fpv

Module : rstmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rstmgr_csr_assert_0/rstmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rstmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rstmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	19	19	100.00	19	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	19	19	100.00	19	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	11056942	8670	0	0
alert_regwen_rd_A	11056942	4206	0	0
cpu_regwen_rd_A	11056942	4146	0	0
sw_rst_ctrl_n_0_rd_A	11056942	8172	0	0
sw_rst_ctrl_n_1_rd_A	11056942	8220	0	0
sw_rst_ctrl_n_2_rd_A	11056942	8023	0	0
sw_rst_ctrl_n_3_rd_A	11056942	7927	0	0
sw_rst_ctrl_n_4_rd_A	11056942	8027	0	0
sw_rst_ctrl_n_5_rd_A	11056942	8240	0	0
sw_rst_ctrl_n_6_rd_A	11056942	7985	0	0
sw_rst_ctrl_n_7_rd_A	11056942	7982	0	0
sw_rst_regwen_0_rd_A	11056942	4710	0	0
sw_rst_regwen_1_rd_A	11056942	4747	0	0
sw_rst_regwen_2_rd_A	11056942	4719	0	0
sw_rst_regwen_3_rd_A	11056942	4698	0	0
sw_rst_regwen_4_rd_A	11056942	4763	0	0
sw_rst_regwen_5_rd_A	11056942	4897	0	0
sw_rst_regwen_6_rd_A	11056942	4652	0	0
sw_rst_regwen_7_rd_A	11056942	4687	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11056942	8670	0	0
T68	3878	10	0	0
T71	17531	4	0	0
T73	4103	22	0	0
T74	2633	38	0	0
T75	3566	235	0	0
T102	2922	26	0	0
T103	4699	15	0	0
T104	4555	12	0	0
T105	3522	26	0	0
T106	3895	16	0	0

alert_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11056942	4206	0	0
T60	38747	88	0	0
T61	2625	0	0	0
T62	27571	0	0	0
T63	105323	0	0	0
T64	1670	0	0	0
T65	4257	0	0	0
T66	18544	0	0	0
T100	114436	0	0	0
T109	1815	0	0	0
T110	1886	0	0	0
T114	0	31	0	0
T116	0	72	0	0
T118	0	59	0	0
T143	0	68	0	0
T144	0	69	0	0
T145	0	95	0	0
T146	0	54	0	0
T147	0	31	0	0
T148	0	123	0	0

cpu_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11056942	4146	0	0
T60	38747	85	0	0
T61	2625	0	0	0
T62	27571	0	0	0
T63	105323	0	0	0
T64	1670	0	0	0
T65	4257	0	0	0
T66	18544	0	0	0
T100	114436	0	0	0
T109	1815	0	0	0
T110	1886	0	0	0
T114	0	34	0	0
T116	0	71	0	0
T118	0	70	0	0
T143	0	90	0	0
T144	0	68	0	0
T145	0	100	0	0
T146	0	48	0	0
T147	0	47	0	0
T148	0	76	0	0

sw_rst_ctrl_n_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11056942	8172	0	0
T11	10093	96	0	0
T12	2563	0	0	0
T13	32739	0	0	0
T14	7878	0	0	0
T15	17855	0	0	0
T16	1986	11	0	0
T60	0	87	0	0
T67	6918	0	0	0
T79	1652	0	0	0
T92	5298	0	0	0
T93	2372	0	0	0
T95	0	130	0	0
T98	0	13	0	0
T143	0	242	0	0
T149	0	4	0	0
T150	0	7	0	0
T151	0	159	0	0
T152	0	87	0	0

sw_rst_ctrl_n_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11056942	8220	0	0
T11	10093	140	0	0
T12	2563	0	0	0
T13	32739	0	0	0
T14	7878	0	0	0
T15	17855	0	0	0
T16	1986	10	0	0
T60	0	97	0	0
T67	6918	0	0	0
T79	1652	0	0	0
T92	5298	0	0	0
T93	2372	0	0	0
T95	0	129	0	0
T98	0	10	0	0
T118	0	72	0	0
T143	0	218	0	0
T149	0	12	0	0
T151	0	126	0	0
T152	0	109	0	0

sw_rst_ctrl_n_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11056942	8023	0	0
T11	10093	93	0	0
T12	2563	0	0	0
T13	32739	0	0	0
T14	7878	0	0	0
T15	17855	0	0	0
T16	1986	9	0	0
T60	0	89	0	0
T67	6918	0	0	0
T79	1652	0	0	0
T92	5298	0	0	0
T93	2372	0	0	0
T95	0	129	0	0
T98	0	11	0	0
T118	0	45	0	0
T143	0	248	0	0
T150	0	13	0	0
T151	0	130	0	0
T152	0	98	0	0

sw_rst_ctrl_n_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11056942	7927	0	0
T11	10093	109	0	0
T12	2563	0	0	0
T13	32739	0	0	0
T14	7878	0	0	0
T15	17855	0	0	0
T16	1986	11	0	0
T60	0	80	0	0
T67	6918	0	0	0
T79	1652	0	0	0
T92	5298	0	0	0
T93	2372	0	0	0
T95	0	134	0	0
T98	0	19	0	0
T143	0	252	0	0
T149	0	11	0	0
T150	0	2	0	0
T151	0	135	0	0
T152	0	119	0	0

sw_rst_ctrl_n_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11056942	8027	0	0
T11	10093	98	0	0
T12	2563	0	0	0
T13	32739	0	0	0
T14	7878	0	0	0
T15	17855	0	0	0
T16	1986	12	0	0
T60	0	80	0	0
T67	6918	0	0	0
T79	1652	0	0	0
T92	5298	0	0	0
T93	2372	0	0	0
T95	0	145	0	0
T98	0	17	0	0
T118	0	85	0	0
T143	0	234	0	0
T150	0	8	0	0
T151	0	119	0	0
T152	0	134	0	0

sw_rst_ctrl_n_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11056942	8240	0	0
T11	10093	103	0	0
T12	2563	0	0	0
T13	32739	0	0	0
T14	7878	0	0	0
T15	17855	0	0	0
T16	1986	8	0	0
T60	0	67	0	0
T67	6918	0	0	0
T79	1652	0	0	0
T92	5298	0	0	0
T93	2372	0	0	0
T95	0	135	0	0
T98	0	7	0	0
T118	0	74	0	0
T143	0	218	0	0
T149	0	8	0	0
T151	0	183	0	0
T152	0	86	0	0

sw_rst_ctrl_n_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11056942	7985	0	0
T11	10093	105	0	0
T12	2563	0	0	0
T13	32739	0	0	0
T14	7878	0	0	0
T15	17855	0	0	0
T16	1986	11	0	0
T60	0	90	0	0
T67	6918	0	0	0
T79	1652	0	0	0
T92	5298	0	0	0
T93	2372	0	0	0
T95	0	115	0	0
T98	0	22	0	0
T143	0	222	0	0
T149	0	4	0	0
T150	0	2	0	0
T151	0	184	0	0
T152	0	105	0	0

sw_rst_ctrl_n_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11056942	7982	0	0
T11	10093	86	0	0
T12	2563	0	0	0
T13	32739	0	0	0
T14	7878	0	0	0
T15	17855	0	0	0
T16	1986	6	0	0
T60	0	93	0	0
T67	6918	0	0	0
T79	1652	0	0	0
T92	5298	0	0	0
T93	2372	0	0	0
T95	0	145	0	0
T98	0	13	0	0
T143	0	236	0	0
T149	0	6	0	0
T150	0	15	0	0
T151	0	143	0	0
T152	0	96	0	0

sw_rst_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11056942	4710	0	0
T11	10093	18	0	0
T12	2563	0	0	0
T13	32739	0	0	0
T14	7878	0	0	0
T15	17855	0	0	0
T16	1986	0	0	0
T60	0	96	0	0
T67	6918	0	0	0
T79	1652	0	0	0
T92	5298	0	0	0
T93	2372	0	0	0
T95	0	22	0	0
T98	0	2	0	0
T118	0	52	0	0
T143	0	77	0	0
T150	0	3	0	0
T151	0	22	0	0
T152	0	17	0	0
T153	0	10	0	0

sw_rst_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11056942	4747	0	0
T11	10093	18	0	0
T12	2563	0	0	0
T13	32739	0	0	0
T14	7878	0	0	0
T15	17855	0	0	0
T16	1986	0	0	0
T60	0	75	0	0
T67	6918	0	0	0
T79	1652	0	0	0
T92	5298	0	0	0
T93	2372	0	0	0
T95	0	20	0	0
T98	0	8	0	0
T118	0	57	0	0
T143	0	67	0	0
T151	0	24	0	0
T152	0	15	0	0
T153	0	1	0	0
T154	0	20	0	0

sw_rst_regwen_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11056942	4719	0	0
T11	10093	16	0	0
T12	2563	0	0	0
T13	32739	0	0	0
T14	7878	0	0	0
T15	17855	0	0	0
T16	1986	0	0	0
T60	0	94	0	0
T67	6918	0	0	0
T79	1652	0	0	0
T92	5298	0	0	0
T93	2372	0	0	0
T95	0	21	0	0
T98	0	6	0	0
T118	0	62	0	0
T143	0	81	0	0
T150	0	3	0	0
T151	0	35	0	0
T152	0	18	0	0
T153	0	10	0	0

sw_rst_regwen_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11056942	4698	0	0
T11	10093	16	0	0
T12	2563	0	0	0
T13	32739	0	0	0
T14	7878	0	0	0
T15	17855	0	0	0
T16	1986	0	0	0
T60	0	71	0	0
T67	6918	0	0	0
T79	1652	0	0	0
T92	5298	0	0	0
T93	2372	0	0	0
T95	0	27	0	0
T98	0	6	0	0
T118	0	66	0	0
T143	0	87	0	0
T150	0	6	0	0
T151	0	40	0	0
T152	0	11	0	0
T153	0	3	0	0

sw_rst_regwen_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11056942	4763	0	0
T11	10093	20	0	0
T12	2563	0	0	0
T13	32739	0	0	0
T14	7878	0	0	0
T15	17855	0	0	0
T16	1986	0	0	0
T60	0	63	0	0
T67	6918	0	0	0
T79	1652	0	0	0
T92	5298	0	0	0
T93	2372	0	0	0
T95	0	40	0	0
T98	0	6	0	0
T118	0	63	0	0
T143	0	84	0	0
T150	0	10	0	0
T151	0	34	0	0
T152	0	25	0	0
T153	0	16	0	0

sw_rst_regwen_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11056942	4897	0	0
T11	10093	9	0	0
T12	2563	0	0	0
T13	32739	0	0	0
T14	7878	0	0	0
T15	17855	0	0	0
T16	1986	0	0	0
T60	0	75	0	0
T67	6918	0	0	0
T79	1652	0	0	0
T92	5298	0	0	0
T93	2372	0	0	0
T95	0	44	0	0
T98	0	9	0	0
T118	0	71	0	0
T143	0	64	0	0
T150	0	9	0	0
T151	0	36	0	0
T152	0	10	0	0
T153	0	4	0	0

sw_rst_regwen_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11056942	4652	0	0
T11	10093	15	0	0
T12	2563	0	0	0
T13	32739	0	0	0
T14	7878	0	0	0
T15	17855	0	0	0
T16	1986	0	0	0
T60	0	53	0	0
T67	6918	0	0	0
T79	1652	0	0	0
T92	5298	0	0	0
T93	2372	0	0	0
T95	0	34	0	0
T98	0	1	0	0
T118	0	83	0	0
T143	0	87	0	0
T150	0	6	0	0
T151	0	24	0	0
T152	0	22	0	0
T153	0	6	0	0

sw_rst_regwen_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11056942	4687	0	0
T11	10093	20	0	0
T12	2563	0	0	0
T13	32739	0	0	0
T14	7878	0	0	0
T15	17855	0	0	0
T16	1986	0	0	0
T60	0	79	0	0
T67	6918	0	0	0
T79	1652	0	0	0
T92	5298	0	0	0
T93	2372	0	0	0
T95	0	47	0	0
T98	0	10	0	0
T118	0	77	0	0
T143	0	93	0	0
T150	0	5	0	0
T151	0	33	0	0
T152	0	20	0	0
T153	0	3	0	0