Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	602277	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

363877

1

T1

114

T2

1041

T3

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	515635	1			T1	160		T2	1508		T4	1
values[0x0]	224885	1			T1	80		T2	649		T3	2
values[0x1]	225634	1			T1	89		T2	668		T3	4

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	504741	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

461413

1

T1

152

T2

1335

T3

3

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	3275	1			T7	21		T9	17		T11	6
valid_sources[0x01]	3913	1			T7	56		T8	6		T9	17
valid_sources[0x02]	3092	1			T1	4		T7	63		T9	16
valid_sources[0x03]	3615	1			T1	1		T7	81		T9	7
valid_sources[0x04]	3746	1			T1	2		T5	1		T7	82
valid_sources[0x05]	3072	1			T1	2		T7	43		T9	20
valid_sources[0x06]	3179	1			T1	1		T5	1		T7	64
valid_sources[0x07]	3144	1			T1	4		T5	1		T7	33
valid_sources[0x08]	3209	1			T1	1		T6	7		T7	47
valid_sources[0x09]	3557	1			T1	1		T2	443		T7	72
valid_sources[0x0a]	3694	1			T1	4		T5	2		T6	9
valid_sources[0x0b]	3035	1			T1	2		T7	43		T9	7
valid_sources[0x0c]	2995	1			T5	2		T7	76		T9	7
valid_sources[0x0d]	3882	1			T1	1		T5	2		T7	65
valid_sources[0x0e]	3438	1			T1	1		T2	13		T6	4
valid_sources[0x0f]	5163	1			T1	1		T6	8		T7	22
valid_sources[0x10]	3379	1			T1	2		T2	142		T7	41
valid_sources[0x11]	3375	1			T1	3		T7	17		T9	8
valid_sources[0x12]	3277	1			T1	1		T7	40		T9	11
valid_sources[0x13]	3097	1			T1	1		T7	27		T9	15
valid_sources[0x14]	3876	1			T7	31		T9	7		T10	1
valid_sources[0x15]	3787	1			T1	1		T7	49		T9	25
valid_sources[0x16]	2932	1			T7	39		T9	8		T11	1
valid_sources[0x17]	4535	1			T1	5		T5	1		T7	65
valid_sources[0x18]	5483	1			T7	86		T8	2		T9	19
valid_sources[0x19]	3944	1			T1	1		T5	2		T7	61
valid_sources[0x1a]	4208	1			T5	1		T7	49		T9	4
valid_sources[0x1b]	3046	1			T1	1		T7	43		T8	1
valid_sources[0x1c]	3190	1			T7	32		T8	1		T9	24
valid_sources[0x1d]	3611	1			T1	3		T7	32		T8	1
valid_sources[0x1e]	4169	1			T1	1		T7	75		T9	9
valid_sources[0x1f]	3192	1			T1	2		T7	42		T9	22
valid_sources[0x20]	3083	1			T7	58		T8	1		T9	6
valid_sources[0x21]	4113	1			T6	2		T7	66		T9	19
valid_sources[0x22]	3477	1			T7	29		T9	4		T11	20
valid_sources[0x23]	2946	1			T1	1		T7	64		T9	5
valid_sources[0x24]	3480	1			T1	1		T7	33		T9	11
valid_sources[0x25]	3157	1			T1	2		T7	81		T8	1
valid_sources[0x26]	3337	1			T1	1		T7	33		T9	23
valid_sources[0x27]	3117	1			T6	13		T7	20		T8	2
valid_sources[0x28]	3090	1			T2	113		T5	1		T7	30
valid_sources[0x29]	4354	1			T7	88		T9	7		T11	6
valid_sources[0x2a]	3299	1			T7	52		T9	4		T11	11
valid_sources[0x2b]	3046	1			T1	2		T7	35		T8	4
valid_sources[0x2c]	3068	1			T7	49		T8	3		T9	23
valid_sources[0x2d]	4309	1			T1	1		T7	66		T9	17
valid_sources[0x2e]	4466	1			T7	31		T8	1		T9	10
valid_sources[0x2f]	3286	1			T1	3		T6	5		T7	47
valid_sources[0x30]	3683	1			T6	1		T7	31		T8	2
valid_sources[0x31]	4594	1			T1	1		T5	1		T7	78
valid_sources[0x32]	4326	1			T7	50		T9	22		T10	1
valid_sources[0x33]	3309	1			T1	1		T7	86		T9	9
valid_sources[0x34]	3555	1			T1	2		T5	1		T7	61
valid_sources[0x35]	3780	1			T1	3		T7	45		T9	7
valid_sources[0x36]	4971	1			T5	1		T7	14		T8	1
valid_sources[0x37]	3197	1			T1	1		T5	2		T7	31
valid_sources[0x38]	4613	1			T1	2		T5	1		T7	56
valid_sources[0x39]	3121	1			T1	1		T5	1		T7	35
valid_sources[0x3a]	5301	1			T7	86		T8	1		T9	5
valid_sources[0x3b]	3768	1			T1	1		T6	11		T7	52
valid_sources[0x3c]	3651	1			T1	1		T5	1		T7	92
valid_sources[0x3d]	3525	1			T7	41		T9	10		T11	2
valid_sources[0x3e]	3648	1			T1	1		T4	1		T7	27
valid_sources[0x3f]	4740	1			T1	1		T7	46		T8	1
valid_sources[0x40]	3077	1			T7	60		T9	17		T11	6
valid_sources[0x41]	3195	1			T1	2		T7	44		T9	11
valid_sources[0x42]	3424	1			T1	1		T7	40		T9	14
valid_sources[0x43]	2897	1			T1	2		T7	46		T9	4
valid_sources[0x44]	3691	1			T1	1		T7	19		T8	2
valid_sources[0x45]	4192	1			T1	2		T5	1		T7	56
valid_sources[0x46]	3167	1			T7	22		T8	1		T9	15
valid_sources[0x47]	3148	1			T1	2		T5	1		T7	45
valid_sources[0x48]	2837	1			T2	3		T7	55		T9	3
valid_sources[0x49]	3332	1			T1	2		T2	349		T5	1
valid_sources[0x4a]	4485	1			T1	1		T2	240		T7	42
valid_sources[0x4b]	3022	1			T1	3		T5	1		T7	31
valid_sources[0x4c]	3597	1			T1	2		T7	30		T8	1
valid_sources[0x4d]	3416	1			T1	3		T7	53		T8	1
valid_sources[0x4e]	3382	1			T1	2		T7	46		T9	16
valid_sources[0x4f]	4623	1			T1	1		T7	20		T8	3
valid_sources[0x50]	3990	1			T1	2		T7	80		T9	15
valid_sources[0x51]	3747	1			T1	1		T7	34		T9	7
valid_sources[0x52]	4218	1			T1	4		T7	63		T9	9
valid_sources[0x53]	3255	1			T1	1		T7	31		T9	9
valid_sources[0x54]	3763	1			T5	1		T6	7		T7	38
valid_sources[0x55]	4202	1			T7	42		T8	4		T9	10
valid_sources[0x56]	2906	1			T1	3		T7	13		T8	1
valid_sources[0x57]	7204	1			T1	5		T5	1		T7	38
valid_sources[0x58]	4377	1			T1	2		T7	34		T9	21
valid_sources[0x59]	3653	1			T5	1		T7	23		T9	8
valid_sources[0x5a]	6140	1			T1	3		T5	2		T7	40
valid_sources[0x5b]	3069	1			T1	1		T7	41		T9	33
valid_sources[0x5c]	3233	1			T1	2		T7	40		T9	7
valid_sources[0x5d]	2884	1			T1	2		T7	72		T8	4
valid_sources[0x5e]	3267	1			T7	15		T8	1		T9	8
valid_sources[0x5f]	5405	1			T1	1		T5	1		T7	31
valid_sources[0x60]	3771	1			T1	3		T2	4		T7	68
valid_sources[0x61]	4527	1			T1	4		T7	48		T9	2
valid_sources[0x62]	2972	1			T1	2		T7	61		T9	8
valid_sources[0x63]	3355	1			T1	1		T2	43		T5	1
valid_sources[0x64]	3889	1			T1	1		T5	1		T6	2
valid_sources[0x65]	3783	1			T1	2		T6	16		T7	65
valid_sources[0x66]	3143	1			T1	1		T2	112		T7	15
valid_sources[0x67]	3183	1			T1	1		T7	26		T8	1
valid_sources[0x68]	3129	1			T1	3		T6	2		T7	22
valid_sources[0x69]	4761	1			T1	1		T7	47		T8	1
valid_sources[0x6a]	2894	1			T1	1		T7	49		T9	23
valid_sources[0x6b]	3342	1			T1	2		T7	32		T9	8
valid_sources[0x6c]	4156	1			T1	1		T5	1		T7	50
valid_sources[0x6d]	3561	1			T1	1		T7	74		T8	1
valid_sources[0x6e]	3575	1			T1	3		T5	1		T7	67
valid_sources[0x6f]	3367	1			T7	36		T9	11		T11	6
valid_sources[0x70]	3669	1			T1	1		T7	32		T8	1
valid_sources[0x71]	3087	1			T1	1		T7	78		T9	11
valid_sources[0x72]	4353	1			T2	110		T7	119		T8	2
valid_sources[0x73]	3161	1			T7	32		T9	10		T11	6
valid_sources[0x74]	2808	1			T1	1		T5	1		T7	41
valid_sources[0x75]	4796	1			T1	2		T5	1		T7	29
valid_sources[0x76]	3351	1			T7	58		T8	1		T9	7
valid_sources[0x77]	3684	1			T7	61		T8	3		T9	9
valid_sources[0x78]	3519	1			T1	1		T2	834		T5	1
valid_sources[0x79]	3511	1			T7	22		T8	2		T9	24
valid_sources[0x7a]	3695	1			T7	44		T9	1		T11	19
valid_sources[0x7b]	4034	1			T1	1		T5	1		T7	37
valid_sources[0x7c]	3928	1			T1	2		T3	6		T7	45
valid_sources[0x7d]	4142	1			T1	2		T7	57		T9	19
valid_sources[0x7e]	3572	1			T1	1		T7	56		T8	1
valid_sources[0x7f]	3300	1			T1	1		T5	2		T7	20
valid_sources[0x80]	3051	1			T7	50		T9	5		T10	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

241984

1

T1

77

T2

719

T5

17

values[0x0]

all_enables

biggest_size

79256

1

T1

23

T2

202

T5

7

values[0x1]

all_enables

biggest_size

42637

1

T1

14

T2

120

T3

1