Unified Coverage Report :: Module :: pwrmgr_rstmgr_sva_if

Module : pwrmgr_rstmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_rstmgr_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_rstmgr_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_rstmgr_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	33	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' or '../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
33	1	1

---

Cond Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       33
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T2,T4,T6

---

Assert Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions_per_power_domains[0].LcHandshakeOff_A	11203083	12754	0	0
gen_assertions_per_power_domains[0].LcHandshakeOn_A	11203083	117790	0	0
gen_assertions_per_power_domains[0].SysHandshakeOff_A	11203083	6636587	0	0
gen_assertions_per_power_domains[0].SysHandshakeOn_A	11203083	188536	0	0
gen_assertions_per_power_domains[1].LcHandshakeOff_A	11203083	12754	0	0
gen_assertions_per_power_domains[1].LcHandshakeOn_A	11203083	117790	0	0
gen_assertions_per_power_domains[1].SysHandshakeOff_A	11203083	6636587	0	0
gen_assertions_per_power_domains[1].SysHandshakeOn_A	11203083	188536	0	0

gen_assertions_per_power_domains[0].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11203083	12754	0	0
T1	2421	16	0	0
T2	14832	45	0	0
T3	1385	0	0	0
T4	6121	0	0	0
T5	1814	4	0	0
T6	3514	4	0	0
T7	136056	145	0	0
T8	2033	4	0	0
T9	52938	75	0	0
T10	1729	0	0	0
T11	0	31	0	0
T13	0	27	0	0
T23	0	147	0	0

gen_assertions_per_power_domains[0].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11203083	117790	0	0
T1	2421	144	0	0
T2	14832	413	0	0
T3	1385	0	0	0
T4	6121	0	0	0
T5	1814	36	0	0
T6	3514	37	0	0
T7	136056	1350	0	0
T8	2033	37	0	0
T9	52938	701	0	0
T10	1729	0	0	0
T11	0	280	0	0
T13	0	244	0	0
T23	0	1343	0	0

gen_assertions_per_power_domains[0].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11203083	6636587	0	0
T1	2421	1633	0	0
T2	14832	7805	0	0
T3	1385	760	0	0
T4	6121	922	0	0
T5	1814	1150	0	0
T6	3514	2525	0	0
T7	136056	98620	0	0
T8	2033	1104	0	0
T9	52938	35834	0	0
T10	1729	1128	0	0

gen_assertions_per_power_domains[0].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11203083	188536	0	0
T1	2421	214	0	0
T2	14832	670	0	0
T3	1385	0	0	0
T4	6121	0	0	0
T5	1814	66	0	0
T6	3514	50	0	0
T7	136056	2151	0	0
T8	2033	57	0	0
T9	52938	1100	0	0
T10	1729	0	0	0
T11	0	416	0	0
T13	0	410	0	0
T23	0	2165	0	0

gen_assertions_per_power_domains[1].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11203083	12754	0	0
T1	2421	16	0	0
T2	14832	45	0	0
T3	1385	0	0	0
T4	6121	0	0	0
T5	1814	4	0	0
T6	3514	4	0	0
T7	136056	145	0	0
T8	2033	4	0	0
T9	52938	75	0	0
T10	1729	0	0	0
T11	0	31	0	0
T13	0	27	0	0
T23	0	147	0	0

gen_assertions_per_power_domains[1].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11203083	117790	0	0
T1	2421	144	0	0
T2	14832	413	0	0
T3	1385	0	0	0
T4	6121	0	0	0
T5	1814	36	0	0
T6	3514	37	0	0
T7	136056	1350	0	0
T8	2033	37	0	0
T9	52938	701	0	0
T10	1729	0	0	0
T11	0	280	0	0
T13	0	244	0	0
T23	0	1343	0	0

gen_assertions_per_power_domains[1].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11203083	6636587	0	0
T1	2421	1633	0	0
T2	14832	7805	0	0
T3	1385	760	0	0
T4	6121	922	0	0
T5	1814	1150	0	0
T6	3514	2525	0	0
T7	136056	98620	0	0
T8	2033	1104	0	0
T9	52938	35834	0	0
T10	1729	1128	0	0

gen_assertions_per_power_domains[1].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11203083	188536	0	0
T1	2421	214	0	0
T2	14832	670	0	0
T3	1385	0	0	0
T4	6121	0	0	0
T5	1814	66	0	0
T6	3514	50	0	0
T7	136056	2151	0	0
T8	2033	57	0	0
T9	52938	1100	0	0
T10	1729	0	0	0
T11	0	416	0	0
T13	0	410	0	0
T23	0	2165	0	0