Unified Coverage Report :: Module :: rstmgr_cascading_sva_if

Module : rstmgr_cascading_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_cascading_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_cascading_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_cascading_sva_if

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	100	1	1	100.00
ALWAYS	103	1	1	100.00
ALWAYS	107	1	1	100.00
ALWAYS	127	1	1	100.00
ALWAYS	138	1	1	100.00
ALWAYS	141	1	1	100.00
ALWAYS	144	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
100	1	1
103	1	1
107	1	1
127	1	1
138	1	1
141	1	1
144	1	1

---

Cond Coverage for Module : rstmgr_cascading_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       103
 EXPRESSION (((!scanmode)) || scan_rst_ni)
             ------1------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T2,T6,T7
0	1	Covered	T2,T7,T8
1	0	Covered	T7,T11,T13

 LINE       107
 EXPRESSION (por_n_i[rstmgr_pkg::DomainAonSel] && ((!scanmode)))
             ----------------1----------------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T7
1	0	Covered	T2,T6,T7
1	1	Covered	T1,T2,T3

---

Assert Coverage for Module : rstmgr_cascading_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	31	31	100.00	31	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	31	31	100.00	31	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CascadeEffAonToRstPorAboveFall_A	52702843	8470	0	0
CascadeEffAonToRstPorAboveRise_A	52702843	8470	0	0
CascadeEffAonToRstPorIoAboveFall_A	50593361	8470	0	0
CascadeEffAonToRstPorIoAboveRise_A	50593361	8470	0	0
CascadeEffAonToRstPorIoDiv2AboveFall_A	25297388	8470	0	0
CascadeEffAonToRstPorIoDiv2AboveRise_A	25297388	8470	0	0
CascadeEffAonToRstPorIoDiv4AboveFall_A	12648406	8470	0	0
CascadeEffAonToRstPorIoDiv4AboveRise_A	12648406	8470	0	0
CascadeEffAonToRstPorUcbAboveFall_A	25297398	8470	0	0
CascadeEffAonToRstPorUcbAboveRise_A	25297398	8470	0	0
CascadeLcToLcAboveFall_A	52702843	21224	0	0
CascadeLcToLcAboveRise_A	52702843	21224	0	0
CascadeLcToLcAonAboveFall_A	1597223	21224	0	0
CascadeLcToLcAonAboveRise_A	1597223	21224	0	0
CascadeLcToLcShadowedAboveFall_A	52702843	21224	0	0
CascadeLcToLcShadowedAboveRise_A	52702843	21224	0	0
CascadePorToAonAboveFall_A	1597223	6688	0	0
CascadeSysToSysAboveFall_A	52702843	21224	0	0
CascadeSysToSysAboveRise_A	52702843	21224	0	0
ScanRstToAonRise_A	1597223	189	0	0
StablePorToAonRise_A	1597223	8470	0	0
g_power_domains[0].CascadeLcToSysAboveFall_A	11203083	21224	0	0
g_power_domains[0].CascadeLcToSysAboveRise_A	11203083	21224	0	0
g_power_domains[0].CascadeLocalRstToLcAboveFall_A	11203083	21224	0	0
g_power_domains[0].CascadeLocalRstToLcAboveRise_A	11203083	21224	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A	12648406	21224	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A	12648406	21224	0	0
g_power_domains[1].CascadeLcToSysAboveFall_A	11203083	21224	0	0
g_power_domains[1].CascadeLcToSysAboveRise_A	11203083	21224	0	0
g_power_domains[1].CascadeLocalRstToLcAboveFall_A	11203083	21224	0	0
g_power_domains[1].CascadeLocalRstToLcAboveRise_A	11203083	21224	0	0

CascadeEffAonToRstPorAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52702843	8470	0	0
T1	14815	1	0	0
T2	83021	14	0	0
T3	5951	1	0	0
T4	25886	2	0	0
T5	9112	1	0	0
T6	15050	2	0	0
T7	638444	80	0	0
T8	9679	2	0	0
T9	234246	27	0	0
T10	7484	1	0	0

CascadeEffAonToRstPorAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52702843	8470	0	0
T1	14815	1	0	0
T2	83021	14	0	0
T3	5951	1	0	0
T4	25886	2	0	0
T5	9112	1	0	0
T6	15050	2	0	0
T7	638444	80	0	0
T8	9679	2	0	0
T9	234246	27	0	0
T10	7484	1	0	0

CascadeEffAonToRstPorIoAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50593361	8470	0	0
T1	14222	1	0	0
T2	79707	14	0	0
T3	5713	1	0	0
T4	24848	2	0	0
T5	8747	1	0	0
T6	14455	2	0	0
T7	612925	80	0	0
T8	9291	2	0	0
T9	224906	27	0	0
T10	7185	1	0	0

CascadeEffAonToRstPorIoAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50593361	8470	0	0
T1	14222	1	0	0
T2	79707	14	0	0
T3	5713	1	0	0
T4	24848	2	0	0
T5	8747	1	0	0
T6	14455	2	0	0
T7	612925	80	0	0
T8	9291	2	0	0
T9	224906	27	0	0
T10	7185	1	0	0

CascadeEffAonToRstPorIoDiv2AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25297388	8470	0	0
T1	7111	1	0	0
T2	39846	14	0	0
T3	2855	1	0	0
T4	12424	2	0	0
T5	4373	1	0	0
T6	7226	2	0	0
T7	306465	80	0	0
T8	4643	2	0	0
T9	112449	27	0	0
T10	3592	1	0	0

CascadeEffAonToRstPorIoDiv2AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25297388	8470	0	0
T1	7111	1	0	0
T2	39846	14	0	0
T3	2855	1	0	0
T4	12424	2	0	0
T5	4373	1	0	0
T6	7226	2	0	0
T7	306465	80	0	0
T8	4643	2	0	0
T9	112449	27	0	0
T10	3592	1	0	0

CascadeEffAonToRstPorIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12648406	8470	0	0
T1	3555	1	0	0
T2	19921	14	0	0
T3	1426	1	0	0
T4	6211	2	0	0
T5	2185	1	0	0
T6	3613	2	0	0
T7	153235	80	0	0
T8	2320	2	0	0
T9	56231	27	0	0
T10	1794	1	0	0

CascadeEffAonToRstPorIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12648406	8470	0	0
T1	3555	1	0	0
T2	19921	14	0	0
T3	1426	1	0	0
T4	6211	2	0	0
T5	2185	1	0	0
T6	3613	2	0	0
T7	153235	80	0	0
T8	2320	2	0	0
T9	56231	27	0	0
T10	1794	1	0	0

CascadeEffAonToRstPorUcbAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25297398	8470	0	0
T1	7111	1	0	0
T2	39848	14	0	0
T3	2856	1	0	0
T4	12425	2	0	0
T5	4373	1	0	0
T6	7225	2	0	0
T7	306481	80	0	0
T8	4644	2	0	0
T9	112447	27	0	0
T10	3592	1	0	0

CascadeEffAonToRstPorUcbAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25297398	8470	0	0
T1	7111	1	0	0
T2	39848	14	0	0
T3	2856	1	0	0
T4	12425	2	0	0
T5	4373	1	0	0
T6	7225	2	0	0
T7	306481	80	0	0
T8	4644	2	0	0
T9	112447	27	0	0
T10	3592	1	0	0

CascadeLcToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52702843	21224	0	0
T1	14815	17	0	0
T2	83021	59	0	0
T3	5951	1	0	0
T4	25886	2	0	0
T5	9112	5	0	0
T6	15050	6	0	0
T7	638444	225	0	0
T8	9679	6	0	0
T9	234246	102	0	0
T10	7484	1	0	0

CascadeLcToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52702843	21224	0	0
T1	14815	17	0	0
T2	83021	59	0	0
T3	5951	1	0	0
T4	25886	2	0	0
T5	9112	5	0	0
T6	15050	6	0	0
T7	638444	225	0	0
T8	9679	6	0	0
T9	234246	102	0	0
T10	7484	1	0	0

CascadeLcToLcAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1597223	21224	0	0
T1	443	17	0	0
T2	2575	59	0	0
T3	177	1	0	0
T4	776	2	0	0
T5	272	5	0	0
T6	451	6	0	0
T7	19490	225	0	0
T8	289	6	0	0
T9	7042	102	0	0
T10	223	1	0	0

CascadeLcToLcAonAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1597223	21224	0	0
T1	443	17	0	0
T2	2575	59	0	0
T3	177	1	0	0
T4	776	2	0	0
T5	272	5	0	0
T6	451	6	0	0
T7	19490	225	0	0
T8	289	6	0	0
T9	7042	102	0	0
T10	223	1	0	0

CascadeLcToLcShadowedAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52702843	21224	0	0
T1	14815	17	0	0
T2	83021	59	0	0
T3	5951	1	0	0
T4	25886	2	0	0
T5	9112	5	0	0
T6	15050	6	0	0
T7	638444	225	0	0
T8	9679	6	0	0
T9	234246	102	0	0
T10	7484	1	0	0

CascadeLcToLcShadowedAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52702843	21224	0	0
T1	14815	17	0	0
T2	83021	59	0	0
T3	5951	1	0	0
T4	25886	2	0	0
T5	9112	5	0	0
T6	15050	6	0	0
T7	638444	225	0	0
T8	9679	6	0	0
T9	234246	102	0	0
T10	7484	1	0	0

CascadePorToAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1597223	6688	0	0
T1	443	1	0	0
T2	2575	9	0	0
T3	177	1	0	0
T4	776	20	0	0
T5	272	1	0	0
T6	451	1	0	0
T7	19490	41	0	0
T8	289	1	0	0
T9	7042	27	0	0
T10	223	1	0	0

CascadeSysToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52702843	21224	0	0
T1	14815	17	0	0
T2	83021	59	0	0
T3	5951	1	0	0
T4	25886	2	0	0
T5	9112	5	0	0
T6	15050	6	0	0
T7	638444	225	0	0
T8	9679	6	0	0
T9	234246	102	0	0
T10	7484	1	0	0

CascadeSysToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52702843	21224	0	0
T1	14815	17	0	0
T2	83021	59	0	0
T3	5951	1	0	0
T4	25886	2	0	0
T5	9112	5	0	0
T6	15050	6	0	0
T7	638444	225	0	0
T8	9679	6	0	0
T9	234246	102	0	0
T10	7484	1	0	0

ScanRstToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1597223	189	0	0
T2	2575	1	0	0
T3	177	0	0	0
T4	776	0	0	0
T5	272	0	0	0
T6	451	0	0	0
T7	19490	7	0	0
T8	289	0	0	0
T9	7042	0	0	0
T10	223	0	0	0
T11	4173	2	0	0
T13	0	2	0	0
T34	0	1	0	0
T38	0	2	0	0
T85	0	2	0	0
T98	0	1	0	0
T101	0	2	0	0
T129	0	1	0	0

StablePorToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1597223	8470	0	0
T1	443	1	0	0
T2	2575	14	0	0
T3	177	1	0	0
T4	776	2	0	0
T5	272	1	0	0
T6	451	2	0	0
T7	19490	80	0	0
T8	289	2	0	0
T9	7042	27	0	0
T10	223	1	0	0

g_power_domains[0].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11203083	21224	0	0
T1	2421	17	0	0
T2	14832	59	0	0
T3	1385	1	0	0
T4	6121	2	0	0
T5	1814	5	0	0
T6	3514	6	0	0
T7	136056	225	0	0
T8	2033	6	0	0
T9	52938	102	0	0
T10	1729	1	0	0

g_power_domains[0].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11203083	21224	0	0
T1	2421	17	0	0
T2	14832	59	0	0
T3	1385	1	0	0
T4	6121	2	0	0
T5	1814	5	0	0
T6	3514	6	0	0
T7	136056	225	0	0
T8	2033	6	0	0
T9	52938	102	0	0
T10	1729	1	0	0

g_power_domains[0].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11203083	21224	0	0
T1	2421	17	0	0
T2	14832	59	0	0
T3	1385	1	0	0
T4	6121	2	0	0
T5	1814	5	0	0
T6	3514	6	0	0
T7	136056	225	0	0
T8	2033	6	0	0
T9	52938	102	0	0
T10	1729	1	0	0

g_power_domains[0].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11203083	21224	0	0
T1	2421	17	0	0
T2	14832	59	0	0
T3	1385	1	0	0
T4	6121	2	0	0
T5	1814	5	0	0
T6	3514	6	0	0
T7	136056	225	0	0
T8	2033	6	0	0
T9	52938	102	0	0
T10	1729	1	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12648406	21224	0	0
T1	3555	17	0	0
T2	19921	59	0	0
T3	1426	1	0	0
T4	6211	2	0	0
T5	2185	5	0	0
T6	3613	6	0	0
T7	153235	225	0	0
T8	2320	6	0	0
T9	56231	102	0	0
T10	1794	1	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12648406	21224	0	0
T1	3555	17	0	0
T2	19921	59	0	0
T3	1426	1	0	0
T4	6211	2	0	0
T5	2185	5	0	0
T6	3613	6	0	0
T7	153235	225	0	0
T8	2320	6	0	0
T9	56231	102	0	0
T10	1794	1	0	0

g_power_domains[1].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11203083	21224	0	0
T1	2421	17	0	0
T2	14832	59	0	0
T3	1385	1	0	0
T4	6121	2	0	0
T5	1814	5	0	0
T6	3514	6	0	0
T7	136056	225	0	0
T8	2033	6	0	0
T9	52938	102	0	0
T10	1729	1	0	0

g_power_domains[1].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11203083	21224	0	0
T1	2421	17	0	0
T2	14832	59	0	0
T3	1385	1	0	0
T4	6121	2	0	0
T5	1814	5	0	0
T6	3514	6	0	0
T7	136056	225	0	0
T8	2033	6	0	0
T9	52938	102	0	0
T10	1729	1	0	0

g_power_domains[1].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11203083	21224	0	0
T1	2421	17	0	0
T2	14832	59	0	0
T3	1385	1	0	0
T4	6121	2	0	0
T5	1814	5	0	0
T6	3514	6	0	0
T7	136056	225	0	0
T8	2033	6	0	0
T9	52938	102	0	0
T10	1729	1	0	0

g_power_domains[1].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11203083	21224	0	0
T1	2421	17	0	0
T2	14832	59	0	0
T3	1385	1	0	0
T4	6121	2	0	0
T5	1814	5	0	0
T6	3514	6	0	0
T7	136056	225	0	0
T8	2033	6	0	0
T9	52938	102	0	0
T10	1729	1	0	0