Unified Coverage Report :: Module :: rstmgr_sw_rst_sva_if

Module : rstmgr_sw_rst_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_sw_rst_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_sw_rst_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_sw_rst_sva_if

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
21	8	8

---

Cond Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Covered	Percent
Conditions	24	24	100.00
Logical	24	24	100.00
Non-Logical	0	0
Event	0	0

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[0])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T5,T7
1	0	Covered	T1,T2,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[1])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T5,T7
1	0	Covered	T1,T2,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[2])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T7,T12
1	0	Covered	T1,T2,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[3])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T12,T41
1	0	Covered	T1,T2,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[4])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T12,T41
1	0	Covered	T1,T2,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[5])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T12,T41
1	0	Covered	T1,T2,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[6])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T12,T41
1	0	Covered	T1,T2,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[7])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T12,T41
1	0	Covered	T1,T2,T4

---

Assert Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions[0].RstEnOff_A	12648406	13667	0	0
gen_assertions[0].RstEnOn_A	12648406	1098	0	0
gen_assertions[0].RstNOff_A	12648406	13667	0	0
gen_assertions[0].RstNOn_A	12648406	1098	0	0
gen_assertions[1].RstEnOff_A	50593361	12460	0	0
gen_assertions[1].RstEnOn_A	50593361	992	0	0
gen_assertions[1].RstNOff_A	50593361	12460	0	0
gen_assertions[1].RstNOn_A	50593361	992	0	0
gen_assertions[2].RstEnOff_A	25297388	12539	0	0
gen_assertions[2].RstEnOn_A	25297388	1021	0	0
gen_assertions[2].RstNOff_A	25297388	12539	0	0
gen_assertions[2].RstNOn_A	25297388	1021	0	0
gen_assertions[3].RstEnOff_A	25297398	12609	0	0
gen_assertions[3].RstEnOn_A	25297398	1096	0	0
gen_assertions[3].RstNOff_A	25297398	12609	0	0
gen_assertions[3].RstNOn_A	25297398	1096	0	0
gen_assertions[4].RstEnOff_A	1597223	20955	0	0
gen_assertions[4].RstEnOn_A	1597223	1117	0	0
gen_assertions[4].RstNOff_A	1597223	20955	0	0
gen_assertions[4].RstNOn_A	1597223	1117	0	0
gen_assertions[5].RstEnOff_A	12648406	13891	0	0
gen_assertions[5].RstEnOn_A	12648406	1173	0	0
gen_assertions[5].RstNOff_A	12648406	13891	0	0
gen_assertions[5].RstNOn_A	12648406	1173	0	0
gen_assertions[6].RstEnOff_A	12648406	13960	0	0
gen_assertions[6].RstEnOn_A	12648406	1237	0	0
gen_assertions[6].RstNOff_A	12648406	13960	0	0
gen_assertions[6].RstNOn_A	12648406	1237	0	0
gen_assertions[7].RstEnOff_A	12648406	14000	0	0
gen_assertions[7].RstEnOn_A	12648406	1280	0	0
gen_assertions[7].RstNOff_A	12648406	14000	0	0
gen_assertions[7].RstNOn_A	12648406	1280	0	0

gen_assertions[0].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12648406	13667	0	0
T1	3555	16	0	0
T2	19921	45	0	0
T3	1426	0	0	0
T4	6211	0	0	0
T5	2185	4	0	0
T6	3613	4	0	0
T7	153235	165	0	0
T8	2320	4	0	0
T9	56231	75	0	0
T10	1794	0	0	0
T11	0	31	0	0
T12	0	6	0	0
T13	0	27	0	0

gen_assertions[0].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12648406	1098	0	0
T1	3555	10	0	0
T2	19921	0	0	0
T3	1426	0	0	0
T4	6211	0	0	0
T5	2185	1	0	0
T6	3613	0	0	0
T7	153235	22	0	0
T8	2320	0	0	0
T9	56231	0	0	0
T10	1794	0	0	0
T12	0	6	0	0
T37	0	4	0	0
T41	0	3	0	0
T58	0	1	0	0
T63	0	1	0	0
T83	0	3	0	0
T84	0	1	0	0

gen_assertions[0].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12648406	13667	0	0
T1	3555	16	0	0
T2	19921	45	0	0
T3	1426	0	0	0
T4	6211	0	0	0
T5	2185	4	0	0
T6	3613	4	0	0
T7	153235	165	0	0
T8	2320	4	0	0
T9	56231	75	0	0
T10	1794	0	0	0
T11	0	31	0	0
T12	0	6	0	0
T13	0	27	0	0

gen_assertions[0].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12648406	1098	0	0
T1	3555	10	0	0
T2	19921	0	0	0
T3	1426	0	0	0
T4	6211	0	0	0
T5	2185	1	0	0
T6	3613	0	0	0
T7	153235	22	0	0
T8	2320	0	0	0
T9	56231	0	0	0
T10	1794	0	0	0
T12	0	6	0	0
T37	0	4	0	0
T41	0	3	0	0
T58	0	1	0	0
T63	0	1	0	0
T83	0	3	0	0
T84	0	1	0	0

gen_assertions[1].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50593361	12460	0	0
T1	14222	15	0	0
T2	79707	42	0	0
T3	5713	0	0	0
T4	24848	0	0	0
T5	8747	4	0	0
T6	14455	2	0	0
T7	612925	156	0	0
T8	9291	2	0	0
T9	224906	65	0	0
T10	7185	0	0	0
T11	0	25	0	0
T12	0	4	0	0
T13	0	25	0	0

gen_assertions[1].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50593361	992	0	0
T1	14222	2	0	0
T2	79707	0	0	0
T3	5713	0	0	0
T4	24848	0	0	0
T5	8747	1	0	0
T6	14455	0	0	0
T7	612925	26	0	0
T8	9291	0	0	0
T9	224906	0	0	0
T10	7185	0	0	0
T12	0	4	0	0
T41	0	3	0	0
T52	0	7	0	0
T59	0	3	0	0
T64	0	1	0	0
T85	0	12	0	0
T86	0	1	0	0

gen_assertions[1].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50593361	12460	0	0
T1	14222	15	0	0
T2	79707	42	0	0
T3	5713	0	0	0
T4	24848	0	0	0
T5	8747	4	0	0
T6	14455	2	0	0
T7	612925	156	0	0
T8	9291	2	0	0
T9	224906	65	0	0
T10	7185	0	0	0
T11	0	25	0	0
T12	0	4	0	0
T13	0	25	0	0

gen_assertions[1].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50593361	992	0	0
T1	14222	2	0	0
T2	79707	0	0	0
T3	5713	0	0	0
T4	24848	0	0	0
T5	8747	1	0	0
T6	14455	0	0	0
T7	612925	26	0	0
T8	9291	0	0	0
T9	224906	0	0	0
T10	7185	0	0	0
T12	0	4	0	0
T41	0	3	0	0
T52	0	7	0	0
T59	0	3	0	0
T64	0	1	0	0
T85	0	12	0	0
T86	0	1	0	0

gen_assertions[2].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25297388	12539	0	0
T1	7111	15	0	0
T2	39846	42	0	0
T3	2855	0	0	0
T4	12424	0	0	0
T5	4373	4	0	0
T6	7226	2	0	0
T7	306465	158	0	0
T8	4643	2	0	0
T9	112449	65	0	0
T10	3592	0	0	0
T11	0	25	0	0
T12	0	6	0	0
T13	0	25	0	0

gen_assertions[2].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25297388	1021	0	0
T5	4373	1	0	0
T6	7226	0	0	0
T7	306465	27	0	0
T8	4643	0	0	0
T9	112449	0	0	0
T10	3592	0	0	0
T11	65272	0	0	0
T12	22575	6	0	0
T13	70063	0	0	0
T23	333351	0	0	0
T41	0	6	0	0
T52	0	7	0	0
T53	0	1	0	0
T59	0	7	0	0
T63	0	1	0	0
T64	0	1	0	0
T85	0	11	0	0

gen_assertions[2].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25297388	12539	0	0
T1	7111	15	0	0
T2	39846	42	0	0
T3	2855	0	0	0
T4	12424	0	0	0
T5	4373	4	0	0
T6	7226	2	0	0
T7	306465	158	0	0
T8	4643	2	0	0
T9	112449	65	0	0
T10	3592	0	0	0
T11	0	25	0	0
T12	0	6	0	0
T13	0	25	0	0

gen_assertions[2].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25297388	1021	0	0
T5	4373	1	0	0
T6	7226	0	0	0
T7	306465	27	0	0
T8	4643	0	0	0
T9	112449	0	0	0
T10	3592	0	0	0
T11	65272	0	0	0
T12	22575	6	0	0
T13	70063	0	0	0
T23	333351	0	0	0
T41	0	6	0	0
T52	0	7	0	0
T53	0	1	0	0
T59	0	7	0	0
T63	0	1	0	0
T64	0	1	0	0
T85	0	11	0	0

gen_assertions[3].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25297398	12609	0	0
T1	7111	15	0	0
T2	39848	42	0	0
T3	2856	0	0	0
T4	12425	0	0	0
T5	4373	4	0	0
T6	7225	2	0	0
T7	306481	157	0	0
T8	4644	2	0	0
T9	112447	65	0	0
T10	3592	0	0	0
T11	0	25	0	0
T12	0	7	0	0
T13	0	25	0	0

gen_assertions[3].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25297398	1096	0	0
T7	306481	25	0	0
T8	4644	0	0	0
T9	112447	0	0	0
T10	3592	0	0	0
T11	65294	0	0	0
T12	22575	7	0	0
T13	70072	0	0	0
T14	7399	0	0	0
T23	333360	0	0	0
T24	58537	0	0	0
T41	0	6	0	0
T52	0	8	0	0
T54	0	1	0	0
T55	0	17	0	0
T59	0	8	0	0
T85	0	12	0	0
T87	0	4	0	0
T88	0	8	0	0

gen_assertions[3].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25297398	12609	0	0
T1	7111	15	0	0
T2	39848	42	0	0
T3	2856	0	0	0
T4	12425	0	0	0
T5	4373	4	0	0
T6	7225	2	0	0
T7	306481	157	0	0
T8	4644	2	0	0
T9	112447	65	0	0
T10	3592	0	0	0
T11	0	25	0	0
T12	0	7	0	0
T13	0	25	0	0

gen_assertions[3].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25297398	1096	0	0
T7	306481	25	0	0
T8	4644	0	0	0
T9	112447	0	0	0
T10	3592	0	0	0
T11	65294	0	0	0
T12	22575	7	0	0
T13	70072	0	0	0
T14	7399	0	0	0
T23	333360	0	0	0
T24	58537	0	0	0
T41	0	6	0	0
T52	0	8	0	0
T54	0	1	0	0
T55	0	17	0	0
T59	0	8	0	0
T85	0	12	0	0
T87	0	4	0	0
T88	0	8	0	0

gen_assertions[4].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1597223	20955	0	0
T1	443	16	0	0
T2	2575	59	0	0
T3	177	1	0	0
T4	776	2	0	0
T5	272	4	0	0
T6	451	5	0	0
T7	19490	244	0	0
T8	289	5	0	0
T9	7042	100	0	0
T10	223	1	0	0

gen_assertions[4].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1597223	1117	0	0
T7	19490	25	0	0
T8	289	0	0	0
T9	7042	0	0	0
T10	223	0	0	0
T11	4173	0	0	0
T12	1409	7	0	0
T13	4449	0	0	0
T14	460	0	0	0
T23	21163	0	0	0
T24	3673	0	0	0
T41	0	6	0	0
T52	0	9	0	0
T55	0	18	0	0
T58	0	1	0	0
T59	0	9	0	0
T63	0	1	0	0
T85	0	11	0	0
T87	0	3	0	0

gen_assertions[4].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1597223	20955	0	0
T1	443	16	0	0
T2	2575	59	0	0
T3	177	1	0	0
T4	776	2	0	0
T5	272	4	0	0
T6	451	5	0	0
T7	19490	244	0	0
T8	289	5	0	0
T9	7042	100	0	0
T10	223	1	0	0

gen_assertions[4].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1597223	1117	0	0
T7	19490	25	0	0
T8	289	0	0	0
T9	7042	0	0	0
T10	223	0	0	0
T11	4173	0	0	0
T12	1409	7	0	0
T13	4449	0	0	0
T14	460	0	0	0
T23	21163	0	0	0
T24	3673	0	0	0
T41	0	6	0	0
T52	0	9	0	0
T55	0	18	0	0
T58	0	1	0	0
T59	0	9	0	0
T63	0	1	0	0
T85	0	11	0	0
T87	0	3	0	0

gen_assertions[5].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12648406	13891	0	0
T1	3555	16	0	0
T2	19921	45	0	0
T3	1426	0	0	0
T4	6211	0	0	0
T5	2185	4	0	0
T6	3613	4	0	0
T7	153235	166	0	0
T8	2320	4	0	0
T9	56231	75	0	0
T10	1794	0	0	0
T11	0	31	0	0
T12	0	10	0	0
T13	0	27	0	0

gen_assertions[5].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12648406	1173	0	0
T7	153235	22	0	0
T8	2320	0	0	0
T9	56231	0	0	0
T10	1794	0	0	0
T11	32641	0	0	0
T12	11287	10	0	0
T13	35031	0	0	0
T14	3698	0	0	0
T23	166696	0	0	0
T24	29264	0	0	0
T41	0	8	0	0
T52	0	10	0	0
T54	0	1	0	0
T55	0	17	0	0
T59	0	10	0	0
T85	0	7	0	0
T87	0	4	0	0
T88	0	10	0	0

gen_assertions[5].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12648406	13891	0	0
T1	3555	16	0	0
T2	19921	45	0	0
T3	1426	0	0	0
T4	6211	0	0	0
T5	2185	4	0	0
T6	3613	4	0	0
T7	153235	166	0	0
T8	2320	4	0	0
T9	56231	75	0	0
T10	1794	0	0	0
T11	0	31	0	0
T12	0	10	0	0
T13	0	27	0	0

gen_assertions[5].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12648406	1173	0	0
T7	153235	22	0	0
T8	2320	0	0	0
T9	56231	0	0	0
T10	1794	0	0	0
T11	32641	0	0	0
T12	11287	10	0	0
T13	35031	0	0	0
T14	3698	0	0	0
T23	166696	0	0	0
T24	29264	0	0	0
T41	0	8	0	0
T52	0	10	0	0
T54	0	1	0	0
T55	0	17	0	0
T59	0	10	0	0
T85	0	7	0	0
T87	0	4	0	0
T88	0	10	0	0

gen_assertions[6].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12648406	13960	0	0
T1	3555	16	0	0
T2	19921	45	0	0
T3	1426	0	0	0
T4	6211	0	0	0
T5	2185	4	0	0
T6	3613	4	0	0
T7	153235	168	0	0
T8	2320	4	0	0
T9	56231	75	0	0
T10	1794	0	0	0
T11	0	31	0	0
T12	0	12	0	0
T13	0	27	0	0

gen_assertions[6].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12648406	1237	0	0
T7	153235	23	0	0
T8	2320	0	0	0
T9	56231	0	0	0
T10	1794	0	0	0
T11	32641	0	0	0
T12	11287	12	0	0
T13	35031	0	0	0
T14	3698	0	0	0
T23	166696	0	0	0
T24	29264	0	0	0
T41	0	9	0	0
T52	0	11	0	0
T55	0	15	0	0
T59	0	10	0	0
T85	0	12	0	0
T87	0	4	0	0
T88	0	9	0	0
T89	0	5	0	0

gen_assertions[6].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12648406	13960	0	0
T1	3555	16	0	0
T2	19921	45	0	0
T3	1426	0	0	0
T4	6211	0	0	0
T5	2185	4	0	0
T6	3613	4	0	0
T7	153235	168	0	0
T8	2320	4	0	0
T9	56231	75	0	0
T10	1794	0	0	0
T11	0	31	0	0
T12	0	12	0	0
T13	0	27	0	0

gen_assertions[6].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12648406	1237	0	0
T7	153235	23	0	0
T8	2320	0	0	0
T9	56231	0	0	0
T10	1794	0	0	0
T11	32641	0	0	0
T12	11287	12	0	0
T13	35031	0	0	0
T14	3698	0	0	0
T23	166696	0	0	0
T24	29264	0	0	0
T41	0	9	0	0
T52	0	11	0	0
T55	0	15	0	0
T59	0	10	0	0
T85	0	12	0	0
T87	0	4	0	0
T88	0	9	0	0
T89	0	5	0	0

gen_assertions[7].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12648406	14000	0	0
T1	3555	16	0	0
T2	19921	45	0	0
T3	1426	0	0	0
T4	6211	0	0	0
T5	2185	4	0	0
T6	3613	4	0	0
T7	153235	169	0	0
T8	2320	4	0	0
T9	56231	75	0	0
T10	1794	0	0	0
T11	0	31	0	0
T12	0	11	0	0
T13	0	27	0	0

gen_assertions[7].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12648406	1280	0	0
T7	153235	26	0	0
T8	2320	0	0	0
T9	56231	0	0	0
T10	1794	0	0	0
T11	32641	0	0	0
T12	11287	11	0	0
T13	35031	0	0	0
T14	3698	0	0	0
T23	166696	0	0	0
T24	29264	0	0	0
T41	0	9	0	0
T52	0	12	0	0
T54	0	1	0	0
T55	0	14	0	0
T59	0	12	0	0
T85	0	13	0	0
T87	0	2	0	0
T88	0	13	0	0

gen_assertions[7].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12648406	14000	0	0
T1	3555	16	0	0
T2	19921	45	0	0
T3	1426	0	0	0
T4	6211	0	0	0
T5	2185	4	0	0
T6	3613	4	0	0
T7	153235	169	0	0
T8	2320	4	0	0
T9	56231	75	0	0
T10	1794	0	0	0
T11	0	31	0	0
T12	0	11	0	0
T13	0	27	0	0

gen_assertions[7].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12648406	1280	0	0
T7	153235	26	0	0
T8	2320	0	0	0
T9	56231	0	0	0
T10	1794	0	0	0
T11	32641	0	0	0
T12	11287	11	0	0
T13	35031	0	0	0
T14	3698	0	0	0
T23	166696	0	0	0
T24	29264	0	0	0
T41	0	9	0	0
T52	0	12	0	0
T54	0	1	0	0
T55	0	14	0	0
T59	0	12	0	0
T85	0	13	0	0
T87	0	2	0	0
T88	0	13	0	0