Unified Coverage Report :: Module :: rstmgr_csr_assert_fpv

Module : rstmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rstmgr_csr_assert_0/rstmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rstmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rstmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	19	19	100.00	19	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	19	19	100.00	19	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	12043616	8783	0	0
alert_regwen_rd_A	12043616	4826	0	0
cpu_regwen_rd_A	12043616	4804	0	0
sw_rst_ctrl_n_0_rd_A	12043616	10317	0	0
sw_rst_ctrl_n_1_rd_A	12043616	10064	0	0
sw_rst_ctrl_n_2_rd_A	12043616	10012	0	0
sw_rst_ctrl_n_3_rd_A	12043616	9734	0	0
sw_rst_ctrl_n_4_rd_A	12043616	9957	0	0
sw_rst_ctrl_n_5_rd_A	12043616	9963	0	0
sw_rst_ctrl_n_6_rd_A	12043616	10100	0	0
sw_rst_ctrl_n_7_rd_A	12043616	9727	0	0
sw_rst_regwen_0_rd_A	12043616	5443	0	0
sw_rst_regwen_1_rd_A	12043616	5485	0	0
sw_rst_regwen_2_rd_A	12043616	5296	0	0
sw_rst_regwen_3_rd_A	12043616	5441	0	0
sw_rst_regwen_4_rd_A	12043616	5238	0	0
sw_rst_regwen_5_rd_A	12043616	5424	0	0
sw_rst_regwen_6_rd_A	12043616	5313	0	0
sw_rst_regwen_7_rd_A	12043616	5234	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12043616	8783	0	0
T60	2717	32	0	0
T65	16874	2	0	0
T66	10088	637	0	0
T67	8641	423	0	0
T68	17085	2	0	0
T90	3815	134	0	0
T91	17557	3	0	0
T92	3052	15	0	0
T93	16476	6	0	0
T94	2751	16	0	0

alert_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12043616	4826	0	0
T13	30987	47	0	0
T14	3513	0	0	0
T23	146890	140	0	0
T24	26055	0	0	0
T34	65957	0	0	0
T35	5488	0	0	0
T36	5089	0	0	0
T37	3095	0	0	0
T38	18848	0	0	0
T39	5164	0	0	0
T89	0	467	0	0
T101	0	91	0	0
T103	0	206	0	0
T106	0	64	0	0
T107	0	56	0	0
T125	0	19	0	0
T126	0	264	0	0
T127	0	95	0	0

cpu_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12043616	4804	0	0
T13	30987	57	0	0
T14	3513	0	0	0
T23	146890	137	0	0
T24	26055	0	0	0
T34	65957	0	0	0
T35	5488	0	0	0
T36	5089	0	0	0
T37	3095	0	0	0
T38	18848	0	0	0
T39	5164	0	0	0
T89	0	383	0	0
T101	0	83	0	0
T103	0	194	0	0
T106	0	63	0	0
T107	0	45	0	0
T125	0	31	0	0
T126	0	254	0	0
T127	0	82	0	0

sw_rst_ctrl_n_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12043616	10317	0	0
T12	11196	211	0	0
T13	30987	52	0	0
T14	3513	0	0	0
T23	146890	209	0	0
T24	26055	0	0	0
T34	65957	0	0	0
T35	5488	0	0	0
T36	5089	0	0	0
T37	3095	0	0	0
T38	18848	0	0	0
T54	0	13	0	0
T56	0	21	0	0
T63	0	11	0	0
T88	0	88	0	0
T101	0	98	0	0
T107	0	67	0	0
T125	0	31	0	0

sw_rst_ctrl_n_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12043616	10064	0	0
T12	11196	179	0	0
T13	30987	57	0	0
T14	3513	0	0	0
T23	146890	144	0	0
T24	26055	0	0	0
T34	65957	0	0	0
T35	5488	0	0	0
T36	5089	0	0	0
T37	3095	0	0	0
T38	18848	0	0	0
T54	0	7	0	0
T56	0	6	0	0
T63	0	14	0	0
T88	0	95	0	0
T101	0	82	0	0
T107	0	37	0	0
T125	0	45	0	0

sw_rst_ctrl_n_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12043616	10012	0	0
T12	11196	160	0	0
T13	30987	73	0	0
T14	3513	0	0	0
T23	146890	192	0	0
T24	26055	0	0	0
T34	65957	0	0	0
T35	5488	0	0	0
T36	5089	0	0	0
T37	3095	0	0	0
T38	18848	0	0	0
T54	0	5	0	0
T56	0	8	0	0
T63	0	6	0	0
T88	0	129	0	0
T101	0	93	0	0
T107	0	51	0	0
T125	0	35	0	0

sw_rst_ctrl_n_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12043616	9734	0	0
T12	11196	166	0	0
T13	30987	53	0	0
T14	3513	0	0	0
T23	146890	170	0	0
T24	26055	0	0	0
T34	65957	0	0	0
T35	5488	0	0	0
T36	5089	0	0	0
T37	3095	0	0	0
T38	18848	0	0	0
T54	0	18	0	0
T56	0	2	0	0
T63	0	16	0	0
T88	0	100	0	0
T101	0	85	0	0
T107	0	56	0	0
T125	0	43	0	0

sw_rst_ctrl_n_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12043616	9957	0	0
T12	11196	169	0	0
T13	30987	76	0	0
T14	3513	0	0	0
T23	146890	115	0	0
T24	26055	0	0	0
T34	65957	0	0	0
T35	5488	0	0	0
T36	5089	0	0	0
T37	3095	0	0	0
T38	18848	0	0	0
T54	0	12	0	0
T56	0	15	0	0
T63	0	7	0	0
T88	0	137	0	0
T101	0	84	0	0
T107	0	35	0	0
T125	0	31	0	0

sw_rst_ctrl_n_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12043616	9963	0	0
T12	11196	159	0	0
T13	30987	66	0	0
T14	3513	0	0	0
T23	146890	112	0	0
T24	26055	0	0	0
T34	65957	0	0	0
T35	5488	0	0	0
T36	5089	0	0	0
T37	3095	0	0	0
T38	18848	0	0	0
T54	0	3	0	0
T63	0	7	0	0
T88	0	97	0	0
T89	0	499	0	0
T101	0	98	0	0
T107	0	56	0	0
T125	0	43	0	0

sw_rst_ctrl_n_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12043616	10100	0	0
T12	11196	182	0	0
T13	30987	64	0	0
T14	3513	0	0	0
T23	146890	170	0	0
T24	26055	0	0	0
T34	65957	0	0	0
T35	5488	0	0	0
T36	5089	0	0	0
T37	3095	0	0	0
T38	18848	0	0	0
T54	0	7	0	0
T56	0	7	0	0
T63	0	5	0	0
T88	0	126	0	0
T101	0	70	0	0
T107	0	40	0	0
T125	0	35	0	0

sw_rst_ctrl_n_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12043616	9727	0	0
T12	11196	184	0	0
T13	30987	54	0	0
T14	3513	0	0	0
T23	146890	156	0	0
T24	26055	0	0	0
T34	65957	0	0	0
T35	5488	0	0	0
T36	5089	0	0	0
T37	3095	0	0	0
T38	18848	0	0	0
T54	0	9	0	0
T56	0	5	0	0
T63	0	3	0	0
T88	0	90	0	0
T101	0	103	0	0
T107	0	48	0	0
T125	0	35	0	0

sw_rst_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12043616	5443	0	0
T12	11196	33	0	0
T13	30987	53	0	0
T14	3513	0	0	0
T23	146890	141	0	0
T24	26055	0	0	0
T34	65957	0	0	0
T35	5488	0	0	0
T36	5089	0	0	0
T37	3095	0	0	0
T38	18848	0	0	0
T54	0	1	0	0
T88	0	13	0	0
T89	0	427	0	0
T101	0	107	0	0
T107	0	61	0	0
T125	0	11	0	0
T128	0	31	0	0

sw_rst_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12043616	5485	0	0
T12	11196	50	0	0
T13	30987	60	0	0
T14	3513	0	0	0
T23	146890	147	0	0
T24	26055	0	0	0
T34	65957	0	0	0
T35	5488	0	0	0
T36	5089	0	0	0
T37	3095	0	0	0
T38	18848	0	0	0
T54	0	7	0	0
T63	0	4	0	0
T88	0	25	0	0
T89	0	452	0	0
T101	0	96	0	0
T107	0	45	0	0
T125	0	43	0	0

sw_rst_regwen_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12043616	5296	0	0
T12	11196	25	0	0
T13	30987	58	0	0
T14	3513	0	0	0
T23	146890	122	0	0
T24	26055	0	0	0
T34	65957	0	0	0
T35	5488	0	0	0
T36	5089	0	0	0
T37	3095	0	0	0
T38	18848	0	0	0
T54	0	4	0	0
T56	0	1	0	0
T88	0	21	0	0
T89	0	432	0	0
T101	0	69	0	0
T107	0	50	0	0
T125	0	40	0	0

sw_rst_regwen_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12043616	5441	0	0
T12	11196	30	0	0
T13	30987	38	0	0
T14	3513	0	0	0
T23	146890	161	0	0
T24	26055	0	0	0
T34	65957	0	0	0
T35	5488	0	0	0
T36	5089	0	0	0
T37	3095	0	0	0
T38	18848	0	0	0
T54	0	1	0	0
T56	0	2	0	0
T63	0	5	0	0
T88	0	7	0	0
T101	0	94	0	0
T107	0	54	0	0
T125	0	60	0	0

sw_rst_regwen_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12043616	5238	0	0
T12	11196	15	0	0
T13	30987	44	0	0
T14	3513	0	0	0
T23	146890	137	0	0
T24	26055	0	0	0
T34	65957	0	0	0
T35	5488	0	0	0
T36	5089	0	0	0
T37	3095	0	0	0
T38	18848	0	0	0
T54	0	7	0	0
T63	0	8	0	0
T88	0	11	0	0
T89	0	466	0	0
T101	0	92	0	0
T107	0	68	0	0
T125	0	28	0	0

sw_rst_regwen_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12043616	5424	0	0
T12	11196	36	0	0
T13	30987	59	0	0
T14	3513	0	0	0
T23	146890	150	0	0
T24	26055	0	0	0
T34	65957	0	0	0
T35	5488	0	0	0
T36	5089	0	0	0
T37	3095	0	0	0
T38	18848	0	0	0
T56	0	4	0	0
T88	0	25	0	0
T89	0	427	0	0
T101	0	96	0	0
T107	0	67	0	0
T125	0	62	0	0
T128	0	21	0	0

sw_rst_regwen_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12043616	5313	0	0
T12	11196	23	0	0
T13	30987	44	0	0
T14	3513	0	0	0
T23	146890	126	0	0
T24	26055	0	0	0
T34	65957	0	0	0
T35	5488	0	0	0
T36	5089	0	0	0
T37	3095	0	0	0
T38	18848	0	0	0
T54	0	11	0	0
T56	0	6	0	0
T63	0	4	0	0
T88	0	21	0	0
T101	0	84	0	0
T107	0	44	0	0
T125	0	30	0	0

sw_rst_regwen_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12043616	5234	0	0
T12	11196	26	0	0
T13	30987	54	0	0
T14	3513	0	0	0
T23	146890	133	0	0
T24	26055	0	0	0
T34	65957	0	0	0
T35	5488	0	0	0
T36	5089	0	0	0
T37	3095	0	0	0
T38	18848	0	0	0
T54	0	3	0	0
T56	0	10	0	0
T63	0	4	0	0
T88	0	8	0	0
T101	0	89	0	0
T107	0	61	0	0
T125	0	33	0	0