Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	587247	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

352836

1

T1

4165

T2

126

T3

128

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	501098	1			T1	6231		T2	186		T3	186
values[0x0]	219846	1			T1	2571		T2	98		T3	96
values[0x1]	219139	1			T1	2566		T2	95		T3	97

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	492947	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

447136

1

T1

5343

T2

173

T3

173

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	3409	1			T1	41		T2	1		T4	1
valid_sources[0x01]	4083	1			T1	30		T2	1		T4	7
valid_sources[0x02]	3255	1			T1	34		T4	4		T5	3
valid_sources[0x03]	3112	1			T1	64		T2	1		T4	3
valid_sources[0x04]	3364	1			T1	43		T2	2		T4	8
valid_sources[0x05]	3664	1			T1	34		T4	1		T5	8
valid_sources[0x06]	3501	1			T1	49		T4	3		T5	2
valid_sources[0x07]	4143	1			T1	45		T4	8		T5	4
valid_sources[0x08]	3319	1			T1	43		T4	2		T5	2
valid_sources[0x09]	3938	1			T1	51		T2	1		T4	3
valid_sources[0x0a]	3443	1			T1	37		T2	3		T4	2
valid_sources[0x0b]	2786	1			T1	56		T2	4		T5	4
valid_sources[0x0c]	3818	1			T1	42		T2	3		T4	1
valid_sources[0x0d]	3404	1			T1	56		T2	1		T4	3
valid_sources[0x0e]	4320	1			T1	47		T2	3		T4	1
valid_sources[0x0f]	3458	1			T1	30		T5	5		T11	1
valid_sources[0x10]	3265	1			T1	34		T2	5		T4	2
valid_sources[0x11]	3495	1			T1	26		T4	3		T5	4
valid_sources[0x12]	2990	1			T1	46		T2	1		T4	1
valid_sources[0x13]	4046	1			T1	21		T2	3		T4	3
valid_sources[0x14]	2917	1			T1	27		T4	3		T5	5
valid_sources[0x15]	3083	1			T1	42		T2	3		T4	1
valid_sources[0x16]	3019	1			T1	58		T2	2		T4	2
valid_sources[0x17]	3302	1			T1	51		T2	1		T4	8
valid_sources[0x18]	3485	1			T1	77		T2	3		T4	3
valid_sources[0x19]	2892	1			T1	35		T2	3		T4	6
valid_sources[0x1a]	2966	1			T1	63		T4	3		T5	1
valid_sources[0x1b]	3107	1			T1	60		T2	2		T4	2
valid_sources[0x1c]	2946	1			T1	57		T2	2		T4	3
valid_sources[0x1d]	2793	1			T1	24		T2	1		T4	2
valid_sources[0x1e]	6448	1			T1	59		T2	4		T4	1
valid_sources[0x1f]	3024	1			T1	41		T4	3		T11	2
valid_sources[0x20]	4009	1			T1	34		T2	1		T4	7
valid_sources[0x21]	3905	1			T1	42		T4	5		T5	5
valid_sources[0x22]	3001	1			T1	34		T2	2		T4	6
valid_sources[0x23]	3676	1			T1	43		T2	2		T4	2
valid_sources[0x24]	3324	1			T1	47		T2	3		T4	2
valid_sources[0x25]	3288	1			T1	31		T4	6		T5	5
valid_sources[0x26]	3237	1			T1	44		T2	2		T4	5
valid_sources[0x27]	3977	1			T1	44		T2	1		T4	1
valid_sources[0x28]	2841	1			T1	38		T2	2		T4	10
valid_sources[0x29]	3190	1			T1	42		T2	2		T4	3
valid_sources[0x2a]	3690	1			T1	36		T2	1		T4	2
valid_sources[0x2b]	3481	1			T1	37		T2	1		T5	4
valid_sources[0x2c]	3293	1			T1	35		T2	1		T5	10
valid_sources[0x2d]	3582	1			T1	43		T2	3		T4	5
valid_sources[0x2e]	3892	1			T1	34		T2	1		T4	6
valid_sources[0x2f]	3670	1			T1	72		T2	2		T4	4
valid_sources[0x30]	3251	1			T1	34		T4	8		T5	5
valid_sources[0x31]	3920	1			T1	43		T5	4		T6	1
valid_sources[0x32]	3302	1			T1	29		T2	2		T4	4
valid_sources[0x33]	3355	1			T1	22		T2	3		T4	2
valid_sources[0x34]	3106	1			T1	55		T2	1		T4	4
valid_sources[0x35]	3821	1			T1	46		T2	1		T4	2
valid_sources[0x36]	3533	1			T1	55		T2	1		T4	1
valid_sources[0x37]	2824	1			T1	44		T2	5		T4	2
valid_sources[0x38]	3784	1			T1	36		T4	3		T5	7
valid_sources[0x39]	3343	1			T1	34		T4	4		T5	5
valid_sources[0x3a]	3224	1			T1	38		T2	3		T4	6
valid_sources[0x3b]	6431	1			T1	38		T2	3		T4	2
valid_sources[0x3c]	3722	1			T1	34		T4	2		T5	4
valid_sources[0x3d]	4236	1			T1	43		T2	2		T4	3
valid_sources[0x3e]	3686	1			T1	49		T2	1		T5	2
valid_sources[0x3f]	3319	1			T1	45		T2	1		T4	2
valid_sources[0x40]	2928	1			T1	71		T2	2		T5	1
valid_sources[0x41]	3596	1			T1	38		T4	3		T5	4
valid_sources[0x42]	3314	1			T1	39		T2	4		T4	3
valid_sources[0x43]	2827	1			T1	55		T2	5		T5	8
valid_sources[0x44]	3334	1			T1	21		T2	1		T4	1
valid_sources[0x45]	4032	1			T1	22		T5	3		T6	30
valid_sources[0x46]	3094	1			T1	82		T2	1		T4	4
valid_sources[0x47]	7391	1			T1	62		T5	3		T6	45
valid_sources[0x48]	3053	1			T1	28		T2	1		T4	4
valid_sources[0x49]	2991	1			T1	39		T2	1		T4	3
valid_sources[0x4a]	4061	1			T1	22		T2	1		T4	6
valid_sources[0x4b]	3691	1			T1	43		T2	3		T4	2
valid_sources[0x4c]	2948	1			T1	43		T2	5		T4	7
valid_sources[0x4d]	3688	1			T1	48		T4	1		T5	3
valid_sources[0x4e]	3069	1			T1	44		T2	5		T4	3
valid_sources[0x4f]	3179	1			T1	60		T4	2		T5	2
valid_sources[0x50]	3174	1			T1	47		T4	3		T5	3
valid_sources[0x51]	3543	1			T1	27		T2	1		T4	4
valid_sources[0x52]	3566	1			T1	39		T2	1		T4	1
valid_sources[0x53]	3172	1			T1	31		T4	1		T5	2
valid_sources[0x54]	3866	1			T1	64		T2	2		T4	7
valid_sources[0x55]	3593	1			T1	36		T2	2		T4	4
valid_sources[0x56]	3439	1			T1	38		T2	1		T4	2
valid_sources[0x57]	3997	1			T1	59		T4	4		T5	1
valid_sources[0x58]	3093	1			T1	58		T2	5		T4	3
valid_sources[0x59]	3403	1			T1	52		T2	2		T5	2
valid_sources[0x5a]	3303	1			T1	52		T2	2		T4	1
valid_sources[0x5b]	3519	1			T1	60		T2	1		T4	5
valid_sources[0x5c]	3054	1			T1	48		T2	3		T5	3
valid_sources[0x5d]	6578	1			T1	40		T2	3		T4	1
valid_sources[0x5e]	6641	1			T1	23		T2	2		T4	1
valid_sources[0x5f]	3741	1			T1	36		T2	9		T4	4
valid_sources[0x60]	2979	1			T1	26		T2	2		T4	6
valid_sources[0x61]	2969	1			T1	53		T2	1		T4	3
valid_sources[0x62]	4499	1			T1	43		T4	1		T5	1
valid_sources[0x63]	4476	1			T1	56		T2	3		T5	4
valid_sources[0x64]	3300	1			T1	68		T2	4		T4	2
valid_sources[0x65]	3095	1			T1	42		T4	4		T5	4
valid_sources[0x66]	3517	1			T1	41		T2	2		T4	3
valid_sources[0x67]	7062	1			T1	64		T2	2		T4	3
valid_sources[0x68]	3661	1			T1	49		T2	1		T4	2
valid_sources[0x69]	3247	1			T1	41		T2	4		T4	3
valid_sources[0x6a]	3319	1			T1	52		T2	4		T4	2
valid_sources[0x6b]	3090	1			T1	45		T4	5		T5	5
valid_sources[0x6c]	3399	1			T1	30		T2	2		T4	1
valid_sources[0x6d]	4679	1			T1	53		T2	1		T4	1
valid_sources[0x6e]	3921	1			T1	47		T2	5		T4	3
valid_sources[0x6f]	6380	1			T1	34		T2	1		T4	2
valid_sources[0x70]	6453	1			T1	12		T2	1		T5	3
valid_sources[0x71]	3031	1			T1	36		T4	6		T5	2
valid_sources[0x72]	3722	1			T1	63		T4	2		T5	4
valid_sources[0x73]	3717	1			T1	65		T2	2		T4	3
valid_sources[0x74]	4138	1			T1	43		T4	4		T5	3
valid_sources[0x75]	3486	1			T1	71		T2	2		T4	2
valid_sources[0x76]	3393	1			T1	12		T2	1		T4	1
valid_sources[0x77]	3330	1			T1	27		T2	1		T4	6
valid_sources[0x78]	3588	1			T1	41		T2	3		T4	5
valid_sources[0x79]	3557	1			T1	23		T4	1		T5	2
valid_sources[0x7a]	3261	1			T1	48		T2	3		T4	1
valid_sources[0x7b]	4740	1			T1	39		T2	3		T4	4
valid_sources[0x7c]	3154	1			T1	27		T2	1		T4	1
valid_sources[0x7d]	3056	1			T1	35		T2	1		T4	1
valid_sources[0x7e]	3010	1			T1	39		T2	1		T4	7
valid_sources[0x7f]	4024	1			T1	35		T4	1		T5	5
valid_sources[0x80]	2903	1			T1	51		T2	1		T4	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

234933

1

T1

2885

T2

78

T3

83

values[0x0]

all_enables

biggest_size

76957

1

T1

871

T2

36

T3

35

values[0x1]

all_enables

biggest_size

40946

1

T1

409

T2

12

T3

10