Unified Coverage Report :: Module :: rstmgr_cascading_sva_if

Module : rstmgr_cascading_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_cascading_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_cascading_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_cascading_sva_if

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	100	1	1	100.00
ALWAYS	103	1	1	100.00
ALWAYS	107	1	1	100.00
ALWAYS	127	1	1	100.00
ALWAYS	138	1	1	100.00
ALWAYS	141	1	1	100.00
ALWAYS	144	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
100	1	1
103	1	1
107	1	1
127	1	1
138	1	1
141	1	1
144	1	1

---

Cond Coverage for Module : rstmgr_cascading_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       103
 EXPRESSION (((!scanmode)) || scan_rst_ni)
             ------1------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T6,T13
1	0	Covered	T1,T3,T6

 LINE       107
 EXPRESSION (por_n_i[rstmgr_pkg::DomainAonSel] && ((!scanmode)))
             ----------------1----------------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Module : rstmgr_cascading_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	31	31	100.00	31	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	31	31	100.00	31	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CascadeEffAonToRstPorAboveFall_A	52153252	8353	0	0
CascadeEffAonToRstPorAboveRise_A	52153252	8353	0	0
CascadeEffAonToRstPorIoAboveFall_A	50065776	8353	0	0
CascadeEffAonToRstPorIoAboveRise_A	50065776	8353	0	0
CascadeEffAonToRstPorIoDiv2AboveFall_A	25033440	8353	0	0
CascadeEffAonToRstPorIoDiv2AboveRise_A	25033440	8353	0	0
CascadeEffAonToRstPorIoDiv4AboveFall_A	12516441	8353	0	0
CascadeEffAonToRstPorIoDiv4AboveRise_A	12516441	8353	0	0
CascadeEffAonToRstPorUcbAboveFall_A	25033601	8353	0	0
CascadeEffAonToRstPorUcbAboveRise_A	25033601	8353	0	0
CascadeLcToLcAboveFall_A	52153252	20916	0	0
CascadeLcToLcAboveRise_A	52153252	20916	0	0
CascadeLcToLcAonAboveFall_A	1579988	20916	0	0
CascadeLcToLcAonAboveRise_A	1579988	20916	0	0
CascadeLcToLcShadowedAboveFall_A	52153252	20916	0	0
CascadeLcToLcShadowedAboveRise_A	52153252	20916	0	0
CascadePorToAonAboveFall_A	1579988	6672	0	0
CascadeSysToSysAboveFall_A	52153252	20916	0	0
CascadeSysToSysAboveRise_A	52153252	20916	0	0
ScanRstToAonRise_A	1579988	199	0	0
StablePorToAonRise_A	1579988	8353	0	0
g_power_domains[0].CascadeLcToSysAboveFall_A	11108636	20916	0	0
g_power_domains[0].CascadeLcToSysAboveRise_A	11108636	20916	0	0
g_power_domains[0].CascadeLocalRstToLcAboveFall_A	11108636	20916	0	0
g_power_domains[0].CascadeLocalRstToLcAboveRise_A	11108636	20916	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A	12516441	20916	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A	12516441	20916	0	0
g_power_domains[1].CascadeLcToSysAboveFall_A	11108636	20916	0	0
g_power_domains[1].CascadeLcToSysAboveRise_A	11108636	20916	0	0
g_power_domains[1].CascadeLocalRstToLcAboveFall_A	11108636	20916	0	0
g_power_domains[1].CascadeLocalRstToLcAboveRise_A	11108636	20916	0	0

CascadeEffAonToRstPorAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52153252	8353	0	0
T1	356875	72	0	0
T2	18996	2	0	0
T3	24170	2	0	0
T4	11528	1	0	0
T5	31249	1	0	0
T6	181663	18	0	0
T7	24338	8	0	0
T8	11927	2	0	0
T9	11331	1	0	0
T10	8081	1	0	0

CascadeEffAonToRstPorAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52153252	8353	0	0
T1	356875	72	0	0
T2	18996	2	0	0
T3	24170	2	0	0
T4	11528	1	0	0
T5	31249	1	0	0
T6	181663	18	0	0
T7	24338	8	0	0
T8	11927	2	0	0
T9	11331	1	0	0
T10	8081	1	0	0

CascadeEffAonToRstPorIoAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50065776	8353	0	0
T1	342609	72	0	0
T2	18241	2	0	0
T3	23208	2	0	0
T4	11066	1	0	0
T5	29997	1	0	0
T6	174400	18	0	0
T7	23351	8	0	0
T8	11453	2	0	0
T9	10878	1	0	0
T10	7758	1	0	0

CascadeEffAonToRstPorIoAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50065776	8353	0	0
T1	342609	72	0	0
T2	18241	2	0	0
T3	23208	2	0	0
T4	11066	1	0	0
T5	29997	1	0	0
T6	174400	18	0	0
T7	23351	8	0	0
T8	11453	2	0	0
T9	10878	1	0	0
T10	7758	1	0	0

CascadeEffAonToRstPorIoDiv2AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25033440	8353	0	0
T1	171298	72	0	0
T2	9119	2	0	0
T3	11600	2	0	0
T4	5532	1	0	0
T5	14999	1	0	0
T6	87204	18	0	0
T7	11674	8	0	0
T8	5725	2	0	0
T9	5438	1	0	0
T10	3877	1	0	0

CascadeEffAonToRstPorIoDiv2AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25033440	8353	0	0
T1	171298	72	0	0
T2	9119	2	0	0
T3	11600	2	0	0
T4	5532	1	0	0
T5	14999	1	0	0
T6	87204	18	0	0
T7	11674	8	0	0
T8	5725	2	0	0
T9	5438	1	0	0
T10	3877	1	0	0

CascadeEffAonToRstPorIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12516441	8353	0	0
T1	85652	72	0	0
T2	4558	2	0	0
T3	5799	2	0	0
T4	2765	1	0	0
T5	7499	1	0	0
T6	43601	18	0	0
T7	5841	8	0	0
T8	2861	2	0	0
T9	2718	1	0	0
T10	1938	1	0	0

CascadeEffAonToRstPorIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12516441	8353	0	0
T1	85652	72	0	0
T2	4558	2	0	0
T3	5799	2	0	0
T4	2765	1	0	0
T5	7499	1	0	0
T6	43601	18	0	0
T7	5841	8	0	0
T8	2861	2	0	0
T9	2718	1	0	0
T10	1938	1	0	0

CascadeEffAonToRstPorUcbAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25033601	8353	0	0
T1	171291	72	0	0
T2	9117	2	0	0
T3	11602	2	0	0
T4	5532	1	0	0
T5	14999	1	0	0
T6	87207	18	0	0
T7	11669	8	0	0
T8	5725	2	0	0
T9	5438	1	0	0
T10	3878	1	0	0

CascadeEffAonToRstPorUcbAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25033601	8353	0	0
T1	171291	72	0	0
T2	9117	2	0	0
T3	11602	2	0	0
T4	5532	1	0	0
T5	14999	1	0	0
T6	87207	18	0	0
T7	11669	8	0	0
T8	5725	2	0	0
T9	5438	1	0	0
T10	3878	1	0	0

CascadeLcToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52153252	20916	0	0
T1	356875	227	0	0
T2	18996	6	0	0
T3	24170	6	0	0
T4	11528	1	0	0
T5	31249	1	0	0
T6	181663	55	0	0
T7	24338	8	0	0
T8	11927	6	0	0
T9	11331	1	0	0
T10	8081	1	0	0

CascadeLcToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52153252	20916	0	0
T1	356875	227	0	0
T2	18996	6	0	0
T3	24170	6	0	0
T4	11528	1	0	0
T5	31249	1	0	0
T6	181663	55	0	0
T7	24338	8	0	0
T8	11927	6	0	0
T9	11331	1	0	0
T10	8081	1	0	0

CascadeLcToLcAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1579988	20916	0	0
T1	11074	227	0	0
T2	568	6	0	0
T3	724	6	0	0
T4	345	1	0	0
T5	937	1	0	0
T6	5532	55	0	0
T7	731	8	0	0
T8	357	6	0	0
T9	339	1	0	0
T10	240	1	0	0

CascadeLcToLcAonAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1579988	20916	0	0
T1	11074	227	0	0
T2	568	6	0	0
T3	724	6	0	0
T4	345	1	0	0
T5	937	1	0	0
T6	5532	55	0	0
T7	731	8	0	0
T8	357	6	0	0
T9	339	1	0	0
T10	240	1	0	0

CascadeLcToLcShadowedAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52153252	20916	0	0
T1	356875	227	0	0
T2	18996	6	0	0
T3	24170	6	0	0
T4	11528	1	0	0
T5	31249	1	0	0
T6	181663	55	0	0
T7	24338	8	0	0
T8	11927	6	0	0
T9	11331	1	0	0
T10	8081	1	0	0

CascadeLcToLcShadowedAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52153252	20916	0	0
T1	356875	227	0	0
T2	18996	6	0	0
T3	24170	6	0	0
T4	11528	1	0	0
T5	31249	1	0	0
T6	181663	55	0	0
T7	24338	8	0	0
T8	11927	6	0	0
T9	11331	1	0	0
T10	8081	1	0	0

CascadePorToAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1579988	6672	0	0
T1	11074	37	0	0
T2	568	1	0	0
T3	724	1	0	0
T4	345	1	0	0
T5	937	1	0	0
T6	5532	10	0	0
T7	731	8	0	0
T8	357	1	0	0
T9	339	1	0	0
T10	240	1	0	0

CascadeSysToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52153252	20916	0	0
T1	356875	227	0	0
T2	18996	6	0	0
T3	24170	6	0	0
T4	11528	1	0	0
T5	31249	1	0	0
T6	181663	55	0	0
T7	24338	8	0	0
T8	11927	6	0	0
T9	11331	1	0	0
T10	8081	1	0	0

CascadeSysToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52153252	20916	0	0
T1	356875	227	0	0
T2	18996	6	0	0
T3	24170	6	0	0
T4	11528	1	0	0
T5	31249	1	0	0
T6	181663	55	0	0
T7	24338	8	0	0
T8	11927	6	0	0
T9	11331	1	0	0
T10	8081	1	0	0

ScanRstToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1579988	199	0	0
T1	11074	1	0	0
T2	568	0	0	0
T3	724	0	0	0
T4	345	0	0	0
T5	937	0	0	0
T6	5532	1	0	0
T7	731	0	0	0
T8	357	0	0	0
T9	339	0	0	0
T10	240	0	0	0
T28	0	3	0	0
T29	0	5	0	0
T56	0	1	0	0
T80	0	1	0	0
T81	0	1	0	0
T90	0	1	0	0
T91	0	4	0	0
T92	0	2	0	0

StablePorToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1579988	8353	0	0
T1	11074	72	0	0
T2	568	2	0	0
T3	724	2	0	0
T4	345	1	0	0
T5	937	1	0	0
T6	5532	18	0	0
T7	731	8	0	0
T8	357	2	0	0
T9	339	1	0	0
T10	240	1	0	0

g_power_domains[0].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11108636	20916	0	0
T1	68871	227	0	0
T2	4365	6	0	0
T3	5463	6	0	0
T4	2723	1	0	0
T5	7408	1	0	0
T6	38774	55	0	0
T7	5294	8	0	0
T8	2477	6	0	0
T9	2628	1	0	0
T10	1848	1	0	0

g_power_domains[0].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11108636	20916	0	0
T1	68871	227	0	0
T2	4365	6	0	0
T3	5463	6	0	0
T4	2723	1	0	0
T5	7408	1	0	0
T6	38774	55	0	0
T7	5294	8	0	0
T8	2477	6	0	0
T9	2628	1	0	0
T10	1848	1	0	0

g_power_domains[0].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11108636	20916	0	0
T1	68871	227	0	0
T2	4365	6	0	0
T3	5463	6	0	0
T4	2723	1	0	0
T5	7408	1	0	0
T6	38774	55	0	0
T7	5294	8	0	0
T8	2477	6	0	0
T9	2628	1	0	0
T10	1848	1	0	0

g_power_domains[0].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11108636	20916	0	0
T1	68871	227	0	0
T2	4365	6	0	0
T3	5463	6	0	0
T4	2723	1	0	0
T5	7408	1	0	0
T6	38774	55	0	0
T7	5294	8	0	0
T8	2477	6	0	0
T9	2628	1	0	0
T10	1848	1	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12516441	20916	0	0
T1	85652	227	0	0
T2	4558	6	0	0
T3	5799	6	0	0
T4	2765	1	0	0
T5	7499	1	0	0
T6	43601	55	0	0
T7	5841	8	0	0
T8	2861	6	0	0
T9	2718	1	0	0
T10	1938	1	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12516441	20916	0	0
T1	85652	227	0	0
T2	4558	6	0	0
T3	5799	6	0	0
T4	2765	1	0	0
T5	7499	1	0	0
T6	43601	55	0	0
T7	5841	8	0	0
T8	2861	6	0	0
T9	2718	1	0	0
T10	1938	1	0	0

g_power_domains[1].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11108636	20916	0	0
T1	68871	227	0	0
T2	4365	6	0	0
T3	5463	6	0	0
T4	2723	1	0	0
T5	7408	1	0	0
T6	38774	55	0	0
T7	5294	8	0	0
T8	2477	6	0	0
T9	2628	1	0	0
T10	1848	1	0	0

g_power_domains[1].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11108636	20916	0	0
T1	68871	227	0	0
T2	4365	6	0	0
T3	5463	6	0	0
T4	2723	1	0	0
T5	7408	1	0	0
T6	38774	55	0	0
T7	5294	8	0	0
T8	2477	6	0	0
T9	2628	1	0	0
T10	1848	1	0	0

g_power_domains[1].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11108636	20916	0	0
T1	68871	227	0	0
T2	4365	6	0	0
T3	5463	6	0	0
T4	2723	1	0	0
T5	7408	1	0	0
T6	38774	55	0	0
T7	5294	8	0	0
T8	2477	6	0	0
T9	2628	1	0	0
T10	1848	1	0	0

g_power_domains[1].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11108636	20916	0	0
T1	68871	227	0	0
T2	4365	6	0	0
T3	5463	6	0	0
T4	2723	1	0	0
T5	7408	1	0	0
T6	38774	55	0	0
T7	5294	8	0	0
T8	2477	6	0	0
T9	2628	1	0	0
T10	1848	1	0	0