Unified Coverage Report :: Module :: rstmgr_sw_rst_sva_if

Module : rstmgr_sw_rst_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_sw_rst_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_sw_rst_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_sw_rst_sva_if

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
21	8	8

---

Cond Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Covered	Percent
Conditions	24	24	100.00
Logical	24	24	100.00
Non-Logical	0	0
Event	0	0

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[0])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[1])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[2])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[3])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[4])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[5])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[6])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[7])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions[0].RstEnOff_A	12516441	13389	0	0
gen_assertions[0].RstEnOn_A	12516441	1009	0	0
gen_assertions[0].RstNOff_A	12516441	13389	0	0
gen_assertions[0].RstNOn_A	12516441	1009	0	0
gen_assertions[1].RstEnOff_A	50065776	12178	0	0
gen_assertions[1].RstEnOn_A	50065776	962	0	0
gen_assertions[1].RstNOff_A	50065776	12178	0	0
gen_assertions[1].RstNOn_A	50065776	962	0	0
gen_assertions[2].RstEnOff_A	25033440	12236	0	0
gen_assertions[2].RstEnOn_A	25033440	985	0	0
gen_assertions[2].RstNOff_A	25033440	12236	0	0
gen_assertions[2].RstNOn_A	25033440	985	0	0
gen_assertions[3].RstEnOff_A	25033601	12298	0	0
gen_assertions[3].RstEnOn_A	25033601	1035	0	0
gen_assertions[3].RstNOff_A	25033601	12298	0	0
gen_assertions[3].RstNOn_A	25033601	1035	0	0
gen_assertions[4].RstEnOff_A	1579988	20718	0	0
gen_assertions[4].RstEnOn_A	1579988	1073	0	0
gen_assertions[4].RstNOff_A	1579988	20718	0	0
gen_assertions[4].RstNOn_A	1579988	1073	0	0
gen_assertions[5].RstEnOff_A	12516441	13647	0	0
gen_assertions[5].RstEnOn_A	12516441	1122	0	0
gen_assertions[5].RstNOff_A	12516441	13647	0	0
gen_assertions[5].RstNOn_A	12516441	1122	0	0
gen_assertions[6].RstEnOff_A	12516441	13679	0	0
gen_assertions[6].RstEnOn_A	12516441	1155	0	0
gen_assertions[6].RstNOff_A	12516441	13679	0	0
gen_assertions[6].RstNOn_A	12516441	1155	0	0
gen_assertions[7].RstEnOff_A	12516441	13768	0	0
gen_assertions[7].RstEnOn_A	12516441	1247	0	0
gen_assertions[7].RstNOff_A	12516441	13768	0	0
gen_assertions[7].RstNOn_A	12516441	1247	0	0

gen_assertions[0].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12516441	13389	0	0
T1	85652	159	0	0
T2	4558	5	0	0
T3	5799	5	0	0
T4	2765	1	0	0
T5	7499	2	0	0
T6	43601	37	0	0
T7	5841	0	0	0
T8	2861	4	0	0
T9	2718	3	0	0
T10	1938	0	0	0
T11	0	4	0	0
T12	0	4	0	0

gen_assertions[0].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12516441	1009	0	0
T1	85652	4	0	0
T2	4558	1	0	0
T3	5799	1	0	0
T4	2765	1	0	0
T5	7499	2	0	0
T6	43601	0	0	0
T7	5841	0	0	0
T8	2861	0	0	0
T9	2718	3	0	0
T10	1938	0	0	0
T11	0	4	0	0
T13	0	1	0	0
T26	0	4	0	0
T29	0	11	0	0

gen_assertions[0].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12516441	13389	0	0
T1	85652	159	0	0
T2	4558	5	0	0
T3	5799	5	0	0
T4	2765	1	0	0
T5	7499	2	0	0
T6	43601	37	0	0
T7	5841	0	0	0
T8	2861	4	0	0
T9	2718	3	0	0
T10	1938	0	0	0
T11	0	4	0	0
T12	0	4	0	0

gen_assertions[0].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12516441	1009	0	0
T1	85652	4	0	0
T2	4558	1	0	0
T3	5799	1	0	0
T4	2765	1	0	0
T5	7499	2	0	0
T6	43601	0	0	0
T7	5841	0	0	0
T8	2861	0	0	0
T9	2718	3	0	0
T10	1938	0	0	0
T11	0	4	0	0
T13	0	1	0	0
T26	0	4	0	0
T29	0	11	0	0

gen_assertions[1].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50065776	12178	0	0
T1	342609	144	0	0
T2	18241	4	0	0
T3	23208	5	0	0
T4	11066	3	0	0
T5	29997	5	0	0
T6	174400	36	0	0
T7	23351	0	0	0
T8	11453	4	0	0
T9	10878	3	0	0
T10	7758	0	0	0
T11	0	4	0	0
T12	0	3	0	0

gen_assertions[1].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50065776	962	0	0
T1	342609	3	0	0
T2	18241	0	0	0
T3	23208	1	0	0
T4	11066	3	0	0
T5	29997	5	0	0
T6	174400	0	0	0
T7	23351	0	0	0
T8	11453	0	0	0
T9	10878	3	0	0
T10	7758	0	0	0
T11	0	4	0	0
T13	0	1	0	0
T15	0	1	0	0
T26	0	5	0	0
T29	0	14	0	0

gen_assertions[1].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50065776	12178	0	0
T1	342609	144	0	0
T2	18241	4	0	0
T3	23208	5	0	0
T4	11066	3	0	0
T5	29997	5	0	0
T6	174400	36	0	0
T7	23351	0	0	0
T8	11453	4	0	0
T9	10878	3	0	0
T10	7758	0	0	0
T11	0	4	0	0
T12	0	3	0	0

gen_assertions[1].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50065776	962	0	0
T1	342609	3	0	0
T2	18241	0	0	0
T3	23208	1	0	0
T4	11066	3	0	0
T5	29997	5	0	0
T6	174400	0	0	0
T7	23351	0	0	0
T8	11453	0	0	0
T9	10878	3	0	0
T10	7758	0	0	0
T11	0	4	0	0
T13	0	1	0	0
T15	0	1	0	0
T26	0	5	0	0
T29	0	14	0	0

gen_assertions[2].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25033440	12236	0	0
T1	171298	147	0	0
T2	9119	4	0	0
T3	11600	4	0	0
T4	5532	4	0	0
T5	14999	6	0	0
T6	87204	36	0	0
T7	11674	0	0	0
T8	5725	4	0	0
T9	5438	5	0	0
T10	3877	0	0	0
T11	0	7	0	0
T12	0	3	0	0

gen_assertions[2].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25033440	985	0	0
T1	171298	5	0	0
T2	9119	0	0	0
T3	11600	0	0	0
T4	5532	4	0	0
T5	14999	6	0	0
T6	87204	0	0	0
T7	11674	0	0	0
T8	5725	0	0	0
T9	5438	5	0	0
T10	3877	0	0	0
T11	0	7	0	0
T26	0	6	0	0
T29	0	14	0	0
T80	0	5	0	0
T81	0	22	0	0
T82	0	4	0	0

gen_assertions[2].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25033440	12236	0	0
T1	171298	147	0	0
T2	9119	4	0	0
T3	11600	4	0	0
T4	5532	4	0	0
T5	14999	6	0	0
T6	87204	36	0	0
T7	11674	0	0	0
T8	5725	4	0	0
T9	5438	5	0	0
T10	3877	0	0	0
T11	0	7	0	0
T12	0	3	0	0

gen_assertions[2].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25033440	985	0	0
T1	171298	5	0	0
T2	9119	0	0	0
T3	11600	0	0	0
T4	5532	4	0	0
T5	14999	6	0	0
T6	87204	0	0	0
T7	11674	0	0	0
T8	5725	0	0	0
T9	5438	5	0	0
T10	3877	0	0	0
T11	0	7	0	0
T26	0	6	0	0
T29	0	14	0	0
T80	0	5	0	0
T81	0	22	0	0
T82	0	4	0	0

gen_assertions[3].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25033601	12298	0	0
T1	171291	147	0	0
T2	9117	4	0	0
T3	11602	4	0	0
T4	5532	6	0	0
T5	14999	8	0	0
T6	87207	36	0	0
T7	11669	0	0	0
T8	5725	4	0	0
T9	5438	5	0	0
T10	3878	0	0	0
T11	0	8	0	0
T12	0	3	0	0

gen_assertions[3].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25033601	1035	0	0
T1	171291	6	0	0
T2	9117	0	0	0
T3	11602	0	0	0
T4	5532	6	0	0
T5	14999	8	0	0
T6	87207	0	0	0
T7	11669	0	0	0
T8	5725	0	0	0
T9	5438	5	0	0
T10	3878	0	0	0
T11	0	8	0	0
T13	0	1	0	0
T15	0	1	0	0
T26	0	6	0	0
T29	0	11	0	0
T80	0	7	0	0

gen_assertions[3].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25033601	12298	0	0
T1	171291	147	0	0
T2	9117	4	0	0
T3	11602	4	0	0
T4	5532	6	0	0
T5	14999	8	0	0
T6	87207	36	0	0
T7	11669	0	0	0
T8	5725	4	0	0
T9	5438	5	0	0
T10	3878	0	0	0
T11	0	8	0	0
T12	0	3	0	0

gen_assertions[3].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25033601	1035	0	0
T1	171291	6	0	0
T2	9117	0	0	0
T3	11602	0	0	0
T4	5532	6	0	0
T5	14999	8	0	0
T6	87207	0	0	0
T7	11669	0	0	0
T8	5725	0	0	0
T9	5438	5	0	0
T10	3878	0	0	0
T11	0	8	0	0
T13	0	1	0	0
T15	0	1	0	0
T26	0	6	0	0
T29	0	11	0	0
T80	0	7	0	0

gen_assertions[4].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1579988	20718	0	0
T1	11074	227	0	0
T2	568	6	0	0
T3	724	7	0	0
T4	345	7	0	0
T5	937	9	0	0
T6	5532	55	0	0
T7	731	2	0	0
T8	357	6	0	0
T9	339	7	0	0
T10	240	1	0	0

gen_assertions[4].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1579988	1073	0	0
T1	11074	3	0	0
T2	568	0	0	0
T3	724	1	0	0
T4	345	6	0	0
T5	937	8	0	0
T6	5532	0	0	0
T7	731	0	0	0
T8	357	0	0	0
T9	339	6	0	0
T10	240	0	0	0
T11	0	9	0	0
T26	0	10	0	0
T29	0	13	0	0
T80	0	7	0	0
T81	0	26	0	0

gen_assertions[4].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1579988	20718	0	0
T1	11074	227	0	0
T2	568	6	0	0
T3	724	7	0	0
T4	345	7	0	0
T5	937	9	0	0
T6	5532	55	0	0
T7	731	2	0	0
T8	357	6	0	0
T9	339	7	0	0
T10	240	1	0	0

gen_assertions[4].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1579988	1073	0	0
T1	11074	3	0	0
T2	568	0	0	0
T3	724	1	0	0
T4	345	6	0	0
T5	937	8	0	0
T6	5532	0	0	0
T7	731	0	0	0
T8	357	0	0	0
T9	339	6	0	0
T10	240	0	0	0
T11	0	9	0	0
T26	0	10	0	0
T29	0	13	0	0
T80	0	7	0	0
T81	0	26	0	0

gen_assertions[5].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12516441	13647	0	0
T1	85652	160	0	0
T2	4558	5	0	0
T3	5799	4	0	0
T4	2765	7	0	0
T5	7499	7	0	0
T6	43601	37	0	0
T7	5841	0	0	0
T8	2861	4	0	0
T9	2718	7	0	0
T10	1938	0	0	0
T11	0	10	0	0
T12	0	4	0	0

gen_assertions[5].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12516441	1122	0	0
T1	85652	6	0	0
T2	4558	1	0	0
T3	5799	0	0	0
T4	2765	7	0	0
T5	7499	7	0	0
T6	43601	0	0	0
T7	5841	0	0	0
T8	2861	0	0	0
T9	2718	7	0	0
T10	1938	0	0	0
T11	0	10	0	0
T26	0	11	0	0
T29	0	15	0	0
T80	0	6	0	0
T81	0	26	0	0

gen_assertions[5].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12516441	13647	0	0
T1	85652	160	0	0
T2	4558	5	0	0
T3	5799	4	0	0
T4	2765	7	0	0
T5	7499	7	0	0
T6	43601	37	0	0
T7	5841	0	0	0
T8	2861	4	0	0
T9	2718	7	0	0
T10	1938	0	0	0
T11	0	10	0	0
T12	0	4	0	0

gen_assertions[5].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12516441	1122	0	0
T1	85652	6	0	0
T2	4558	1	0	0
T3	5799	0	0	0
T4	2765	7	0	0
T5	7499	7	0	0
T6	43601	0	0	0
T7	5841	0	0	0
T8	2861	0	0	0
T9	2718	7	0	0
T10	1938	0	0	0
T11	0	10	0	0
T26	0	11	0	0
T29	0	15	0	0
T80	0	6	0	0
T81	0	26	0	0

gen_assertions[6].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12516441	13679	0	0
T1	85652	160	0	0
T2	4558	5	0	0
T3	5799	4	0	0
T4	2765	8	0	0
T5	7499	9	0	0
T6	43601	37	0	0
T7	5841	0	0	0
T8	2861	4	0	0
T9	2718	7	0	0
T10	1938	0	0	0
T11	0	10	0	0
T12	0	4	0	0

gen_assertions[6].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12516441	1155	0	0
T1	85652	6	0	0
T2	4558	1	0	0
T3	5799	0	0	0
T4	2765	8	0	0
T5	7499	9	0	0
T6	43601	0	0	0
T7	5841	0	0	0
T8	2861	0	0	0
T9	2718	7	0	0
T10	1938	0	0	0
T11	0	10	0	0
T26	0	9	0	0
T29	0	11	0	0
T80	0	8	0	0
T81	0	23	0	0

gen_assertions[6].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12516441	13679	0	0
T1	85652	160	0	0
T2	4558	5	0	0
T3	5799	4	0	0
T4	2765	8	0	0
T5	7499	9	0	0
T6	43601	37	0	0
T7	5841	0	0	0
T8	2861	4	0	0
T9	2718	7	0	0
T10	1938	0	0	0
T11	0	10	0	0
T12	0	4	0	0

gen_assertions[6].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12516441	1155	0	0
T1	85652	6	0	0
T2	4558	1	0	0
T3	5799	0	0	0
T4	2765	8	0	0
T5	7499	9	0	0
T6	43601	0	0	0
T7	5841	0	0	0
T8	2861	0	0	0
T9	2718	7	0	0
T10	1938	0	0	0
T11	0	10	0	0
T26	0	9	0	0
T29	0	11	0	0
T80	0	8	0	0
T81	0	23	0	0

gen_assertions[7].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12516441	13768	0	0
T1	85652	160	0	0
T2	4558	4	0	0
T3	5799	4	0	0
T4	2765	8	0	0
T5	7499	11	0	0
T6	43601	37	0	0
T7	5841	0	0	0
T8	2861	4	0	0
T9	2718	7	0	0
T10	1938	0	0	0
T11	0	12	0	0
T12	0	4	0	0

gen_assertions[7].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12516441	1247	0	0
T1	85652	6	0	0
T2	4558	0	0	0
T3	5799	0	0	0
T4	2765	8	0	0
T5	7499	11	0	0
T6	43601	0	0	0
T7	5841	0	0	0
T8	2861	0	0	0
T9	2718	7	0	0
T10	1938	0	0	0
T11	0	12	0	0
T26	0	11	0	0
T29	0	11	0	0
T80	0	6	0	0
T81	0	31	0	0
T82	0	7	0	0

gen_assertions[7].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12516441	13768	0	0
T1	85652	160	0	0
T2	4558	4	0	0
T3	5799	4	0	0
T4	2765	8	0	0
T5	7499	11	0	0
T6	43601	37	0	0
T7	5841	0	0	0
T8	2861	4	0	0
T9	2718	7	0	0
T10	1938	0	0	0
T11	0	12	0	0
T12	0	4	0	0

gen_assertions[7].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12516441	1247	0	0
T1	85652	6	0	0
T2	4558	0	0	0
T3	5799	0	0	0
T4	2765	8	0	0
T5	7499	11	0	0
T6	43601	0	0	0
T7	5841	0	0	0
T8	2861	0	0	0
T9	2718	7	0	0
T10	1938	0	0	0
T11	0	12	0	0
T26	0	11	0	0
T29	0	11	0	0
T80	0	6	0	0
T81	0	31	0	0
T82	0	7	0	0