Unified Coverage Report :: Module :: rstmgr_csr_assert_fpv

Module : rstmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rstmgr_csr_assert_0/rstmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rstmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rstmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	19	19	100.00	19	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	19	19	100.00	19	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	11857355	7303	0	0
alert_regwen_rd_A	11857355	5265	0	0
cpu_regwen_rd_A	11857355	5254	0	0
sw_rst_ctrl_n_0_rd_A	11857355	10604	0	0
sw_rst_ctrl_n_1_rd_A	11857355	10356	0	0
sw_rst_ctrl_n_2_rd_A	11857355	10601	0	0
sw_rst_ctrl_n_3_rd_A	11857355	10334	0	0
sw_rst_ctrl_n_4_rd_A	11857355	10437	0	0
sw_rst_ctrl_n_5_rd_A	11857355	10533	0	0
sw_rst_ctrl_n_6_rd_A	11857355	10588	0	0
sw_rst_ctrl_n_7_rd_A	11857355	10550	0	0
sw_rst_regwen_0_rd_A	11857355	5813	0	0
sw_rst_regwen_1_rd_A	11857355	5715	0	0
sw_rst_regwen_2_rd_A	11857355	5889	0	0
sw_rst_regwen_3_rd_A	11857355	6000	0	0
sw_rst_regwen_4_rd_A	11857355	5685	0	0
sw_rst_regwen_5_rd_A	11857355	5703	0	0
sw_rst_regwen_6_rd_A	11857355	5582	0	0
sw_rst_regwen_7_rd_A	11857355	5737	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11857355	7303	0	0
T59	9863	1	0	0
T61	20687	2	0	0
T62	20908	1	0	0
T63	4405	27	0	0
T64	2716	4	0	0
T65	5297	24	0	0
T83	8148	442	0	0
T84	2478	3	0	0
T85	20320	1	0	0
T89	20148	3	0	0

alert_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11857355	5265	0	0
T6	38774	79	0	0
T7	5294	0	0	0
T8	2477	0	0	0
T9	2628	0	0	0
T10	1848	0	0	0
T11	3103	0	0	0
T12	2337	0	0	0
T13	4587	0	0	0
T14	2597	0	0	0
T52	1786	0	0	0
T56	0	158	0	0
T81	0	85	0	0
T91	0	77	0	0
T94	0	61	0	0
T97	0	299	0	0
T121	0	39	0	0
T122	0	35	0	0
T123	0	46	0	0
T124	0	132	0	0

cpu_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11857355	5254	0	0
T6	38774	64	0	0
T7	5294	0	0	0
T8	2477	0	0	0
T9	2628	0	0	0
T10	1848	0	0	0
T11	3103	0	0	0
T12	2337	0	0	0
T13	4587	0	0	0
T14	2597	0	0	0
T52	1786	0	0	0
T56	0	176	0	0
T81	0	86	0	0
T91	0	69	0	0
T94	0	48	0	0
T97	0	316	0	0
T121	0	56	0	0
T122	0	31	0	0
T123	0	17	0	0
T124	0	107	0	0

sw_rst_ctrl_n_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11857355	10604	0	0
T3	5463	21	0	0
T4	2723	0	0	0
T5	7408	0	0	0
T6	38774	84	0	0
T7	5294	0	0	0
T8	2477	0	0	0
T9	2628	0	0	0
T10	1848	0	0	0
T11	3103	0	0	0
T16	0	5	0	0
T44	0	1	0	0
T52	1786	0	0	0
T56	0	278	0	0
T81	0	360	0	0
T91	0	132	0	0
T125	0	21	0	0
T126	0	18	0	0
T127	0	46	0	0

sw_rst_ctrl_n_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11857355	10356	0	0
T3	5463	6	0	0
T4	2723	0	0	0
T5	7408	0	0	0
T6	38774	60	0	0
T7	5294	0	0	0
T8	2477	0	0	0
T9	2628	0	0	0
T10	1848	0	0	0
T11	3103	0	0	0
T16	0	2	0	0
T44	0	3	0	0
T52	1786	0	0	0
T56	0	229	0	0
T81	0	435	0	0
T91	0	86	0	0
T125	0	21	0	0
T126	0	8	0	0
T127	0	79	0	0

sw_rst_ctrl_n_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11857355	10601	0	0
T3	5463	18	0	0
T4	2723	0	0	0
T5	7408	0	0	0
T6	38774	28	0	0
T7	5294	0	0	0
T8	2477	0	0	0
T9	2628	0	0	0
T10	1848	0	0	0
T11	3103	0	0	0
T16	0	13	0	0
T44	0	9	0	0
T52	1786	0	0	0
T56	0	300	0	0
T81	0	421	0	0
T91	0	115	0	0
T125	0	35	0	0
T126	0	15	0	0
T127	0	45	0	0

sw_rst_ctrl_n_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11857355	10334	0	0
T3	5463	5	0	0
T4	2723	0	0	0
T5	7408	0	0	0
T6	38774	65	0	0
T7	5294	0	0	0
T8	2477	0	0	0
T9	2628	0	0	0
T10	1848	0	0	0
T11	3103	0	0	0
T16	0	14	0	0
T44	0	4	0	0
T52	1786	0	0	0
T56	0	220	0	0
T81	0	446	0	0
T91	0	108	0	0
T125	0	24	0	0
T126	0	13	0	0
T127	0	47	0	0

sw_rst_ctrl_n_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11857355	10437	0	0
T3	5463	3	0	0
T4	2723	0	0	0
T5	7408	0	0	0
T6	38774	54	0	0
T7	5294	0	0	0
T8	2477	0	0	0
T9	2628	0	0	0
T10	1848	0	0	0
T11	3103	0	0	0
T16	0	4	0	0
T44	0	5	0	0
T52	1786	0	0	0
T56	0	250	0	0
T81	0	466	0	0
T91	0	90	0	0
T125	0	23	0	0
T126	0	6	0	0
T127	0	48	0	0

sw_rst_ctrl_n_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11857355	10533	0	0
T3	5463	10	0	0
T4	2723	0	0	0
T5	7408	0	0	0
T6	38774	73	0	0
T7	5294	0	0	0
T8	2477	0	0	0
T9	2628	0	0	0
T10	1848	0	0	0
T11	3103	0	0	0
T16	0	8	0	0
T44	0	8	0	0
T52	1786	0	0	0
T56	0	224	0	0
T81	0	405	0	0
T91	0	74	0	0
T125	0	25	0	0
T126	0	21	0	0
T127	0	89	0	0

sw_rst_ctrl_n_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11857355	10588	0	0
T3	5463	15	0	0
T4	2723	0	0	0
T5	7408	0	0	0
T6	38774	69	0	0
T7	5294	0	0	0
T8	2477	0	0	0
T9	2628	0	0	0
T10	1848	0	0	0
T11	3103	0	0	0
T44	0	5	0	0
T52	1786	0	0	0
T56	0	246	0	0
T81	0	426	0	0
T91	0	136	0	0
T94	0	50	0	0
T125	0	25	0	0
T126	0	21	0	0
T127	0	79	0	0

sw_rst_ctrl_n_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11857355	10550	0	0
T3	5463	16	0	0
T4	2723	0	0	0
T5	7408	0	0	0
T6	38774	59	0	0
T7	5294	0	0	0
T8	2477	0	0	0
T9	2628	0	0	0
T10	1848	0	0	0
T11	3103	0	0	0
T16	0	18	0	0
T44	0	7	0	0
T52	1786	0	0	0
T56	0	172	0	0
T81	0	433	0	0
T91	0	114	0	0
T125	0	26	0	0
T126	0	20	0	0
T127	0	65	0	0

sw_rst_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11857355	5813	0	0
T3	5463	5	0	0
T4	2723	0	0	0
T5	7408	0	0	0
T6	38774	47	0	0
T7	5294	0	0	0
T8	2477	0	0	0
T9	2628	0	0	0
T10	1848	0	0	0
T11	3103	0	0	0
T44	0	4	0	0
T52	1786	0	0	0
T56	0	177	0	0
T81	0	69	0	0
T91	0	82	0	0
T94	0	83	0	0
T97	0	292	0	0
T126	0	14	0	0
T128	0	7	0	0

sw_rst_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11857355	5715	0	0
T3	5463	8	0	0
T4	2723	0	0	0
T5	7408	0	0	0
T6	38774	71	0	0
T7	5294	0	0	0
T8	2477	0	0	0
T9	2628	0	0	0
T10	1848	0	0	0
T11	3103	0	0	0
T44	0	12	0	0
T52	1786	0	0	0
T56	0	159	0	0
T81	0	56	0	0
T91	0	52	0	0
T94	0	40	0	0
T97	0	334	0	0
T126	0	6	0	0
T128	0	6	0	0

sw_rst_regwen_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11857355	5889	0	0
T3	5463	11	0	0
T4	2723	0	0	0
T5	7408	0	0	0
T6	38774	62	0	0
T7	5294	0	0	0
T8	2477	0	0	0
T9	2628	0	0	0
T10	1848	0	0	0
T11	3103	0	0	0
T44	0	3	0	0
T52	1786	0	0	0
T56	0	144	0	0
T81	0	72	0	0
T91	0	78	0	0
T94	0	59	0	0
T97	0	264	0	0
T126	0	3	0	0
T128	0	8	0	0

sw_rst_regwen_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11857355	6000	0	0
T6	38774	74	0	0
T7	5294	0	0	0
T8	2477	0	0	0
T9	2628	0	0	0
T10	1848	0	0	0
T11	3103	0	0	0
T12	2337	0	0	0
T13	4587	0	0	0
T14	2597	0	0	0
T44	0	9	0	0
T52	1786	0	0	0
T56	0	172	0	0
T81	0	59	0	0
T91	0	57	0	0
T94	0	40	0	0
T97	0	343	0	0
T121	0	49	0	0
T126	0	10	0	0
T128	0	2	0	0

sw_rst_regwen_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11857355	5685	0	0
T3	5463	5	0	0
T4	2723	0	0	0
T5	7408	0	0	0
T6	38774	36	0	0
T7	5294	0	0	0
T8	2477	0	0	0
T9	2628	0	0	0
T10	1848	0	0	0
T11	3103	0	0	0
T44	0	8	0	0
T52	1786	0	0	0
T56	0	148	0	0
T81	0	73	0	0
T91	0	61	0	0
T94	0	72	0	0
T97	0	312	0	0
T126	0	3	0	0
T128	0	13	0	0

sw_rst_regwen_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11857355	5703	0	0
T3	5463	12	0	0
T4	2723	0	0	0
T5	7408	0	0	0
T6	38774	53	0	0
T7	5294	0	0	0
T8	2477	0	0	0
T9	2628	0	0	0
T10	1848	0	0	0
T11	3103	0	0	0
T52	1786	0	0	0
T56	0	161	0	0
T81	0	61	0	0
T91	0	80	0	0
T94	0	59	0	0
T97	0	302	0	0
T121	0	45	0	0
T126	0	8	0	0
T128	0	2	0	0

sw_rst_regwen_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11857355	5582	0	0
T3	5463	11	0	0
T4	2723	0	0	0
T5	7408	0	0	0
T6	38774	63	0	0
T7	5294	0	0	0
T8	2477	0	0	0
T9	2628	0	0	0
T10	1848	0	0	0
T11	3103	0	0	0
T44	0	10	0	0
T52	1786	0	0	0
T56	0	131	0	0
T81	0	75	0	0
T91	0	61	0	0
T94	0	53	0	0
T97	0	295	0	0
T126	0	4	0	0
T128	0	1	0	0

sw_rst_regwen_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11857355	5737	0	0
T3	5463	4	0	0
T4	2723	0	0	0
T5	7408	0	0	0
T6	38774	53	0	0
T7	5294	0	0	0
T8	2477	0	0	0
T9	2628	0	0	0
T10	1848	0	0	0
T11	3103	0	0	0
T44	0	8	0	0
T52	1786	0	0	0
T56	0	152	0	0
T81	0	86	0	0
T91	0	80	0	0
T94	0	24	0	0
T97	0	312	0	0
T126	0	4	0	0
T128	0	7	0	0