Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	634855	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

378845

1

T2

290

T3

1083

T5

871

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	540585	1			T1	1		T2	379		T3	1500
values[0x0]	236075	1			T2	163		T3	867		T5	583
values[0x1]	237040	1			T2	170		T3	833		T5	604

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	532518	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

481182

1

T1

1

T2

354

T3

1406

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	5046	1			T2	4		T5	3		T6	1
valid_sources[0x01]	4507	1			T2	1		T5	15		T10	6
valid_sources[0x02]	4223	1			T2	3		T5	5		T10	9
valid_sources[0x03]	4955	1			T2	1		T5	12		T6	1
valid_sources[0x04]	3207	1			T2	4		T5	8		T6	1
valid_sources[0x05]	3508	1			T2	3		T5	15		T10	11
valid_sources[0x06]	3646	1			T2	2		T5	7		T6	1
valid_sources[0x07]	4211	1			T2	3		T5	19		T6	1
valid_sources[0x08]	3428	1			T2	2		T5	4		T6	1
valid_sources[0x09]	3159	1			T2	1		T5	4		T6	2
valid_sources[0x0a]	3318	1			T2	1		T5	7		T10	15
valid_sources[0x0b]	3054	1			T2	5		T5	7		T6	1
valid_sources[0x0c]	3395	1			T2	4		T5	7		T6	1
valid_sources[0x0d]	4482	1			T2	1		T5	16		T8	6
valid_sources[0x0e]	3420	1			T2	3		T5	15		T6	1
valid_sources[0x0f]	4167	1			T2	3		T5	3		T6	2
valid_sources[0x10]	3404	1			T2	4		T5	11		T10	10
valid_sources[0x11]	3567	1			T2	2		T5	5		T8	3
valid_sources[0x12]	3537	1			T5	7		T6	1		T8	31
valid_sources[0x13]	3360	1			T5	4		T6	2		T10	22
valid_sources[0x14]	4173	1			T2	1		T5	1		T6	1
valid_sources[0x15]	3345	1			T2	4		T5	7		T10	9
valid_sources[0x16]	5401	1			T2	2		T5	7		T10	8
valid_sources[0x17]	4151	1			T2	2		T5	3		T6	2
valid_sources[0x18]	5527	1			T2	4		T5	17		T9	1
valid_sources[0x19]	3593	1			T5	5		T6	2		T10	10
valid_sources[0x1a]	3694	1			T2	2		T5	10		T10	3
valid_sources[0x1b]	3058	1			T2	2		T5	8		T6	1
valid_sources[0x1c]	3909	1			T2	4		T5	2		T6	2
valid_sources[0x1d]	3205	1			T5	9		T10	15		T11	7
valid_sources[0x1e]	3370	1			T2	2		T5	4		T6	2
valid_sources[0x1f]	3107	1			T2	4		T5	12		T10	14
valid_sources[0x20]	6984	1			T2	5		T5	20		T6	1
valid_sources[0x21]	3398	1			T2	1		T5	8		T10	14
valid_sources[0x22]	8226	1			T2	4		T5	3		T6	1
valid_sources[0x23]	4133	1			T1	1		T2	2		T5	16
valid_sources[0x24]	3224	1			T5	8		T6	4		T10	6
valid_sources[0x25]	3134	1			T5	5		T6	2		T10	7
valid_sources[0x26]	3128	1			T2	2		T5	4		T10	16
valid_sources[0x27]	5274	1			T2	7		T5	17		T8	8
valid_sources[0x28]	3206	1			T2	2		T5	22		T8	8
valid_sources[0x29]	3269	1			T2	7		T5	17		T6	1
valid_sources[0x2a]	4316	1			T2	1		T5	6		T10	8
valid_sources[0x2b]	3834	1			T2	2		T5	1		T6	2
valid_sources[0x2c]	3941	1			T2	3		T5	8		T8	18
valid_sources[0x2d]	3591	1			T2	4		T5	8		T10	7
valid_sources[0x2e]	4238	1			T2	2		T5	11		T6	5
valid_sources[0x2f]	4843	1			T2	6		T5	15		T10	12
valid_sources[0x30]	3732	1			T2	2		T5	14		T10	12
valid_sources[0x31]	3339	1			T2	3		T5	1		T6	4
valid_sources[0x32]	3747	1			T2	2		T5	18		T10	19
valid_sources[0x33]	3398	1			T2	2		T5	9		T8	4
valid_sources[0x34]	4327	1			T2	3		T5	5		T10	12
valid_sources[0x35]	4613	1			T2	1		T5	5		T8	10
valid_sources[0x36]	3694	1			T5	19		T6	1		T10	11
valid_sources[0x37]	3804	1			T5	9		T10	7		T11	4
valid_sources[0x38]	3303	1			T2	3		T5	11		T6	1
valid_sources[0x39]	3597	1			T2	5		T5	7		T10	12
valid_sources[0x3a]	3597	1			T2	7		T5	7		T6	1
valid_sources[0x3b]	3980	1			T2	2		T5	13		T6	5
valid_sources[0x3c]	3628	1			T2	5		T5	11		T10	7
valid_sources[0x3d]	3406	1			T2	5		T5	12		T6	2
valid_sources[0x3e]	3426	1			T2	1		T5	25		T6	1
valid_sources[0x3f]	3188	1			T5	3		T6	1		T10	10
valid_sources[0x40]	3507	1			T2	1		T5	17		T6	1
valid_sources[0x41]	4005	1			T2	4		T5	8		T6	3
valid_sources[0x42]	3245	1			T5	12		T6	2		T10	8
valid_sources[0x43]	3525	1			T2	2		T5	12		T10	5
valid_sources[0x44]	3032	1			T2	5		T5	17		T10	2
valid_sources[0x45]	3923	1			T2	1		T5	1		T6	3
valid_sources[0x46]	4547	1			T2	1		T5	7		T10	13
valid_sources[0x47]	3885	1			T2	1		T5	15		T10	10
valid_sources[0x48]	4479	1			T2	2		T5	11		T10	11
valid_sources[0x49]	3823	1			T2	4		T5	1		T10	18
valid_sources[0x4a]	3500	1			T2	1		T5	10		T6	1
valid_sources[0x4b]	3705	1			T2	2		T5	10		T6	1
valid_sources[0x4c]	3274	1			T2	5		T5	14		T10	12
valid_sources[0x4d]	3271	1			T5	7		T6	1		T10	10
valid_sources[0x4e]	3993	1			T2	3		T5	6		T10	21
valid_sources[0x4f]	3654	1			T2	3		T5	1		T10	7
valid_sources[0x50]	3667	1			T2	3		T5	6		T8	21
valid_sources[0x51]	3348	1			T2	1		T5	1		T6	1
valid_sources[0x52]	3577	1			T2	2		T5	5		T6	9
valid_sources[0x53]	3538	1			T2	2		T5	16		T10	16
valid_sources[0x54]	3717	1			T2	1		T5	3		T10	18
valid_sources[0x55]	3125	1			T2	6		T5	7		T10	4
valid_sources[0x56]	3314	1			T2	4		T5	11		T6	2
valid_sources[0x57]	3348	1			T2	3		T5	8		T10	12
valid_sources[0x58]	3219	1			T2	5		T5	15		T10	11
valid_sources[0x59]	3656	1			T2	1		T5	9		T10	17
valid_sources[0x5a]	3179	1			T2	2		T5	13		T6	1
valid_sources[0x5b]	3533	1			T2	2		T5	11		T6	3
valid_sources[0x5c]	3022	1			T2	3		T5	21		T10	10
valid_sources[0x5d]	3784	1			T2	1		T5	5		T6	1
valid_sources[0x5e]	3173	1			T2	1		T5	10		T6	3
valid_sources[0x5f]	3755	1			T2	5		T4	1		T5	10
valid_sources[0x60]	3493	1			T2	7		T5	14		T10	17
valid_sources[0x61]	3010	1			T2	4		T5	1		T10	6
valid_sources[0x62]	3320	1			T2	4		T5	7		T6	3
valid_sources[0x63]	3745	1			T2	4		T5	8		T9	2
valid_sources[0x64]	4093	1			T2	7		T5	9		T10	4
valid_sources[0x65]	3253	1			T2	3		T5	6		T10	15
valid_sources[0x66]	4397	1			T2	5		T5	28		T6	2
valid_sources[0x67]	3367	1			T2	9		T5	5		T10	15
valid_sources[0x68]	4128	1			T2	2		T5	7		T10	13
valid_sources[0x69]	3530	1			T2	3		T5	8		T6	3
valid_sources[0x6a]	3615	1			T2	1		T5	15		T6	1
valid_sources[0x6b]	4647	1			T2	4		T5	10		T9	6
valid_sources[0x6c]	3517	1			T2	3		T5	8		T6	1
valid_sources[0x6d]	3695	1			T2	2		T5	4		T6	1
valid_sources[0x6e]	3951	1			T2	5		T5	11		T6	1
valid_sources[0x6f]	3933	1			T2	5		T5	7		T10	8
valid_sources[0x70]	3155	1			T2	1		T5	4		T8	14
valid_sources[0x71]	3327	1			T2	1		T5	11		T6	4
valid_sources[0x72]	3435	1			T2	1		T10	7		T11	8
valid_sources[0x73]	3941	1			T2	4		T5	12		T6	3
valid_sources[0x74]	4366	1			T2	3		T5	3		T6	1
valid_sources[0x75]	3921	1			T2	7		T5	7		T10	9
valid_sources[0x76]	4886	1			T2	1		T5	4		T10	9
valid_sources[0x77]	3258	1			T5	8		T10	20		T22	4
valid_sources[0x78]	4319	1			T2	2		T5	4		T6	1
valid_sources[0x79]	5181	1			T5	4		T10	4		T11	9
valid_sources[0x7a]	3461	1			T2	2		T5	3		T10	10
valid_sources[0x7b]	4193	1			T2	3		T5	18		T10	14
valid_sources[0x7c]	3694	1			T2	4		T5	9		T6	3
valid_sources[0x7d]	4350	1			T2	1		T5	3		T6	4
valid_sources[0x7e]	4139	1			T2	3		T5	4		T10	21
valid_sources[0x7f]	4700	1			T2	2		T5	22		T10	15
valid_sources[0x80]	3992	1			T2	3		T5	12		T6	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

253298

1

T2

201

T3

667

T5

565

values[0x0]

all_enables

biggest_size

82105

1

T2

49

T3

299

T5

205

values[0x1]

all_enables

biggest_size

43442

1

T2

40

T3

117

T5

101